CN118043970A - Hybrid CMOS micro LED display layout - Google Patents

Abstract

A CMOS power supply layer is described that includes staggered contact regions (alternating V _led and V _cat contact regions) on at least two long sides of a μled display region. In this way, V _led and cathode current are injected uniformly along four sides of the μled display panel. The large cathode current distribution rings on the V _led and V _cat circuits are used to distribute current along the four sides of the panel. The current distribution ring surrounds the pixel die area. An insulating region on the cathode current redistribution ring adjacent to one of the plurality of microbumps may be included.

Description

Hybrid CMOS Micro LED Display Layout

Technical Field

Embodiments of the present disclosure relate generally to light emitting diode (LED) devices. More particularly, embodiments are directed to layout structures of CMOS driver electronics for individually controlling pixel brightness of micro-LEDs.

Background technique

A light emitting diode (LED) is a semiconductor light source that emits visible light when an electric current flows through it. LEDs combine a p-type semiconductor with an n-type semiconductor. LEDs typically use Group III compound semiconductors. Group III compound semiconductors provide stable operation at higher temperatures than devices using other semiconductors. Group III compounds are typically formed on a substrate formed of sapphire or silicon carbide (SiC).

LEDs have become an attractive light source for many applications. From road signs and traffic signals, LEDs are now dominating in general lighting, automotive, mobile electronic devices, camera flashes, display backlighting, horticulture, and sanitary applications. Typical benefits of LEDs over competing light sources are increased efficiency, longer service life, and adaptability to a wide variety of form factors.

Highly compact pixelated light emitting diode (LED) devices, such as micro-LED arrays for advanced automotive forward lighting, can include a monolithic large-area high-power LED die mixed with CMOS driver electronics for individual control of pixel brightness. Linear drive schemes are one of the most practical solutions for such control electronics, especially for large pixel array configurations.

The difficulties associated with this system involve the CMOS wiring used to interconnect all pixel contacts with the power supply and integrated circuit driver. A cost-effective solution must minimize the number of metal layers used for the power planes. However, minimizing the number of metal layers used for the power planes may compromise the performance of the layout for evenly distributing current, leading to undesirable current crowding effects, where excessive current density levels negatively impact heat losses and reliability associated with electromigration at the contact interfaces.

Therefore, there exists a need for a layout architecture that optimizes current distribution in a hybrid LED die/CMOS monolithic architecture.

Summary of the invention

The disclosed techniques and embodiments are directed to a CMOS power plane. In one or more embodiments, the CMOS power plane includes: a cathode redistribution ring having an inner portion and an outer portion, the inner portion surrounding the periphery of a die pixel region, the outer portion including a regional common power supply voltage V _led interlaced with cathode current distribution regions; and a plurality of cathode microbumps contacting the inner portion of the cathode redistribution ring along the periphery of the die pixel region.

Other embodiments of the present disclosure are directed to CMOS layouts. In one or more embodiments, the CMOS layout includes: a power layer on a substrate, the power layer having a plurality of alternating V _led contact areas and cathode contact areas uniformly dispersed along at least two sides of the power layer; a cathode current redistribution ring extending along four sides of the power layer; a plurality of cathode microbumps connecting each of the plurality of alternating V _led contact areas and cathode contact areas to corresponding p contacts of a plurality of pixels; and a common cathode grid electrically connecting the plurality of pixels and the plurality of microbumps.

Other embodiments are directed to a CMOS power layer. In one or more embodiments, the CMOS power layer includes: a cathode redistribution ring having an inner portion and an outer portion, the inner portion surrounding the periphery of the die pixel area, the outer portion including a region common power supply voltage V _led interleaved with cathode current distribution regions along a first side, a second side, a third side, and a fourth side of the CMOS power layer; and a plurality of cathode microbumps contacting the inner portion of the cathode redistribution ring along the periphery of the die pixel area.

Other embodiments are directed to CMOS layouts. In one or more embodiments, the CMOS layout includes: a power layer on a substrate, the power layer having a plurality of alternating V _led contact areas and cathode contact areas dispersed along a first side, a second side, a third side, and a fourth side of the power layer; a cathode current redistribution ring extending along the first side, the second side, the third side, and the fourth side of the power layer; a plurality of cathode microbumps connecting each of the plurality of alternating V _led contact areas and cathode contact areas to a corresponding p-contact of a plurality of pixels; and a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode microbumps.

Other embodiments are directed to a CMOS power plane. In one or more embodiments, the CMOS power plane includes: a cathode redistribution ring having an inner portion and an outer portion, the inner portion surrounding the periphery of the die pixel region, the outer portion including a region common power supply voltage V _led interlaced with the cathode current distribution region; a plurality of cathode microbumps contacting the inner portion of the cathode redistribution ring along the periphery of the die pixel region; and an insulating region on the cathode redistribution ring adjacent to one of the plurality of cathode microbumps.

Other embodiments are directed to CMOS layouts. In one or more embodiments, the CMOS layout includes: a power layer on a substrate, the power layer having a plurality of alternating V _led contact areas and cathode contact areas uniformly dispersed along at least two sides of the power layer; a cathode current redistribution ring extending along four sides of the power layer; a plurality of cathode microbumps connecting each of the plurality of alternating V _led contact areas and cathode contact areas to corresponding p contacts of a plurality of pixels; an insulating region adjacent to one of the plurality of cathode microbumps on the cathode current redistribution ring; and a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode microbumps.

BRIEF DESCRIPTION OF THE DRAWINGS

To facilitate a detailed understanding of the above-listed features of the present disclosure, the present disclosure briefly summarized above may be described in more detail with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate typical embodiments of the present disclosure and therefore should not be considered to limit its scope, as the present disclosure may allow for other equivalent embodiments. The embodiments as described herein are illustrated in the figures of the accompanying drawings by way of example and not limitation, in which similar reference numerals indicate similar elements.

The patent or application file contains at least one drawing executed in color. Copies of the patent or patent application publication in color drawing(s) will be provided by the Office upon request and payment of the necessary fee.

FIG. 1A illustrates a top view of a CMOS top layer of a CMOS power layer according to one or more embodiments;

FIG. 1B is a cross-sectional view taken along line A of FIG. 1A according to one or more embodiments;

FIG. 1C is a cross-sectional view taken along line B of FIG. 1A according to one or more embodiments;

1D illustrates a top view of the CMOS second current distribution layer of the CMOS power layer of FIG. 1A according to one or more embodiments;

FIG. 1E illustrates a top view of a common cathode of the CMOS power layer of FIG. 1A according to one or more embodiments;

FIG. 2A illustrates a top view of a CMOS top layer of a CMOS power layer according to one or more embodiments;

2B illustrates a top view of the CMOS second current distribution layer of the CMOS power layer of FIG. 2A according to one or more embodiments;

2C illustrates a top view of a common cathode of the CMOS power layer of FIG. 2A according to one or more embodiments;

3A illustrates a top view of a CMOS top layer with an isolation region of a CMOS power layer according to one or more embodiments;

FIG. 3B is an enlarged view of a region 370 of the CMOS power layer of FIG. 3A according to one or more embodiments;

FIG. 4A is a current density diagram of a CMOS power plane according to one or more embodiments;

FIG. 4B is a current density diagram of a CMOS power layer according to one or more embodiments;

FIG. 5A is a graph of current density of a microbump according to one or more embodiments;

FIG. 5B is a graph of current density of a microbump according to one or more embodiments; and

FIG. 6 shows a block diagram of an example of a visualization system using a μLED array of one or more embodiments.

To facilitate understanding, where possible, the same reference numerals have been used to denote common elements in the drawings. The drawings are not drawn to scale. For example, the height and width of the countertops are not drawn to scale.

Detailed ways

Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

According to one or more embodiments, the term "substrate" as used herein refers to an intermediate or final structure having a surface or a portion of a surface on which a process is performed. Additionally, in some embodiments, reference to a substrate also refers to only a portion of a substrate, unless the context clearly indicates otherwise. Furthermore, according to some embodiments, reference to depositing on a substrate includes depositing on a bare substrate, or depositing on a substrate having one or more layers, films, features, or materials deposited or formed thereon.

In one or more embodiments, "substrate" means any substrate or material surface formed on a substrate on which film processing is performed during a fabrication process. In exemplary embodiments, depending on the application, the substrate surface on which processing is performed includes materials such as silicon, silicon oxide, silicon on insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, gallium arsenide, glass, sapphire, and any other suitable material (such as metals, metal nitrides, group III-nitrides (e.g., GaN, AlN, InN, and other alloys), metal alloys, and other conductive materials). Substrates include, but are not limited to, light emitting diode (LED) devices. In some embodiments, the substrate is exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and/or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in some embodiments, any of the disclosed film processing steps is also performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such an underlying layer as indicated by the context. Thus, for example, where a film/layer or portion of a film/layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.

In this disclosure, the terms "wafer" and "substrate" will be used interchangeably. Thus, as used herein, a wafer serves as a substrate for forming the LED devices described herein.

In order to deploy LEDs for high-density display applications or large-area medium-density applications, the characteristic size of the LED unit is expected to be 100 microns or less, with typical values ranging from 8 to 25 microns. Such LEDs are generally referred to as micro-LEDs (μLEDs). Micro-display technology based on micro-LEDs is still in the early stages of commercial deployment, but for some applications, it is expected to slowly replace existing display technologies, such as liquid crystal displays on silicon (LCDoS) or organic light-emitting diodes on silicon (OLEDoS) displays. One of the biggest obstacles to commercializing micro-LED displays is the transfer technology by which the pixelated LEDs are attached to the backplane.

The embodiments described herein describe CMOS driver electronics for individually controlling pixel brightness of micro-LEDs. The CMOS power plane layout of one or more embodiments uses small staggered contact areas (alternating V _led and V _cat contact areas) on at least two long sides of the micro-LED display area. In the CMOS power plane layout of one or more embodiments, it is advantageous that V _led and cathode currents are injected uniformly along the four sides of the panel. Additionally, a large loop on the V _led and V _cat circuits is used to distribute current along the four sides of the panel.

Complementary Metal Oxide Semiconductor (CMOS) - also known as Complementary Symmetric Metal Oxide Semiconductor (COS-MOS) - is a type of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) fabrication process that uses complementary and symmetrical p-type and n-type MOSFET pairs to implement logic functions. CMOS technology is used to construct integrated circuit (IC) chips. CMOS refers to a specific style of digital circuit design and a family of processes used to implement that circuit on an integrated circuit (chip). CMOS circuits consume less power than logic families with resistive loads.

The CMOS power supply circuit layout has two functions: applying a positive V _led potential to each CMOS driver unit and applying a ground potential to the pixel common cathode. For this purpose, two different circuits are required: (1) V _cat circuit: to electrically connect the CMOS ground contact to the common cathode grid of the LED pixels; and (2) V _led potential circuit: to apply a positive potential (V _led ) to each CMOS driver unit.

CMOS layouts can generally be divided into layers designated for digital circuits, small signal analog circuits, and powertrain. The latter is preferably reduced to one or two layers (particularly the top or bottom layer) to facilitate current distribution and interconnection with external components (such as LED tube cores). With respect to the latter, a peripheral ring around the tube core is typically used to connect the pixel common cathode grid to the _Vcat circuit. In one or more embodiments, the ring connection is as close to the tube core area as possible to reduce ohmic losses. The interconnection between the common cathode and the ground circuit cannot be located in the tube core area because the minimum area required to interconnect the two layers may not be suitable for the current limiting space between pixels. The interconnection of the common cathode grid to the power layer is achieved by microbumps of a size similar to the pixel size (approximately 40×40μm). Since the current flowing through the entire device is very high, and since the length of the first microbump row is limited, the current density in the microbump is very high, thereby increasing the risk of reliability failure of the metal interconnect. Therefore, limiting the current density in the microbump is a key design requirement.

In addition, the thickness of the CMOS power layer is limited by process constraints. For example, using sputtering or electroplating, the process thickness of the CMOS power line is limited to a few microns. As a result, the sheet resistance of the diffusion layer will be limited and the electrical losses in the diffusion layer will be significant. To solve this problem, additional current distribution layers connected in parallel through vias are usually used.

Traditionally, the CMOS power layer layout uses a portion of the CMOS backplane for the V _led potential and another portion of the backplane for the V _cat potential. In the traditional CMOS power layer layout, a u-shaped cathode circuit (with a potential of V _cat ) surrounds the V _led circuit and contacts the microbump. The u-shaped cathode circuit serves as a current distribution area for the cathode circuit. The problem with this configuration is that the cathode current is injected on three sides of the panel. The current in the second current distribution layer is forced to flow to the side edges. Because it is not wide enough, the resistance is high. This is the main problem that causes uneven current distribution through the common cathode microbump. With this CMOS layout, the current is not injected evenly along the four sides of the die area. As a result, one or more current distribution layers connected in parallel are required to evenly distribute the cathode current on the four sides of the LED pixel area and reduce the microbump current density.

Therefore, additional layers connected in parallel are needed to redistribute the current along the remaining sides of the die area. Therefore, the additional layers are mainly used to distribute the current, rather than to reduce ohmic losses. As for V _led , the current is injected only on one side of the panel, resulting in a significant voltage drop between the top and bottom sides of the die area. As a result, the current distribution in the die area is not uniform and the current density in the microbumps is very high.

Therefore, referring to Figures 1A-1C, one or more embodiments provide a CMOS power layer layout 100, in which small staggered cathode distribution areas (alternating _Vcat and _Vled contact areas 102, 104) and large cathode redistribution rings 112 are used to distribute current around the four sides of the tube core area. With this layout, the current is evenly distributed over the four sides of the tube core area, and the additional current distribution layers connected in parallel can be mainly used to reduce ohmic losses. As a result, the ohmic power loss and current density in the microbump are significantly reduced. In addition, only one type of cathode microbump (microbump (uBump) or microbump (μBump)) 106 is required, which simplifies the CMOS panel manufacturing process.

Those skilled in the art will appreciate that, for ease of illustration, the plurality of microbumps 106 are not drawn to scale, and the microbumps 106 shown are represented as being larger than they actually are. Additionally, those skilled in the art will appreciate that several rows of microbumps 106 can be used to interconnect with a common cathode of a CMOS (not shown). In practice, the minimum size of the microbumps is limited by process constraints. In one or more embodiments of the hybrid CMOS μLED display, the diameter of the anode microbump is smaller than the pixel size, and the cathode microbump 106 has the same or similar size as the anode microbump 114.

An overview of a CMOS power layer 100 with staggered regions 102, 104 and cathode redistribution ring 112 according to the present invention is shown in Figures 1A-1E. Figures 1B and 1C are cross-sectional views 100A and 100B, respectively, of the μLED display region 100 shown in Figure 1A taken along lines A and B. Figure 1A is a top view 100 of the CMOS top layer. Figure 1D is a view 150 of the CMOS second current distribution layer. Figure 1E is a view 155 of the common cathode.

1A to 1C, in one or more embodiments, the CMOS power layer 120 uses small staggered contact areas (alternating V _led 104 contact areas and V _cat 102 contact areas) on at least two long sides 108 of the μLED display area 100. As used herein, "staggered" refers to the interspersing and alternation of V _led 104 and cathode 102 contact areas, so that the V _led 104 contact area is adjacent to two cathode 102 contact areas. In this way, the V _led 104 and cathode 102 currents are uniformly injected along the four sides 108, 110 of the panel.

In one or more embodiments, a large cathode redistribution ring 112 on the _Vcat circuit and a common supply voltage _Vled 154 on the _Vled circuit are used to distribute current along the four sides 108, 110 of the panel. Note that the cathode redistribution ring 112 of one or more embodiments is a complete ring and not a u-shaped ring. As shown, only the top and bottom sides of the display 100 are used for current injection. In one or more embodiments, the cathode redistribution ring 112 surrounds the pixel die area, the common cathode grid 130. Note that for ease of drawing, the common cathode grid 130 in FIG. 1A has been drawn so that no grid covers the cathode microbumps 106 so that the cathode microbumps 106 can be seen. Those skilled in the art will understand that the common cathode grid 130 can extend above the cathode microbumps 106, as shown in FIG. 1B and FIG. 1C.

The pixel die area, common cathode grid 130 includes a plurality of pixels 116, as shown in Figures 1B and 1C. Although only two pixels 116 are shown, it is understood by those skilled in the art that any number of pixels may exist depending on the size of the pixel 116 and the size of the die. In some embodiments, there may be 86 pixels. In other embodiments, there may be 170 pixels or more. Pixel 116 may have any suitable size known to those skilled in the art. In some embodiments, pixel 116 may be a 40 μm pixel, or a 30 μm pixel, or a 20 μm pixel.

In one or more embodiments, the staggered region is made of at least three contact regions (alternating V _cat 102 contact regions and V _led 104 contact regions). In the embodiment shown in FIG. 1A , the staggered region is made of ten cathode contacts 102 and eight V _led contact 104 regions periodically distributed along the two long sides 108 of the CMOS panel 100. In one or more embodiments, the greater the number of alternating V _led 104 and cathode 102 contact regions, the better the current distribution will be. Therefore, in one or more embodiments, more than three or more than five contact regions are used. In some embodiments, there are at least ten cathode 102 contact regions and at least eight V _led 104 contact regions.

In one or more embodiments, the alternating V _led 104 and cathode 102 contact areas are located on the two long sides 108 of the CMOS panel 100 and are not located on the two short sides 110 of the panel 100 .

1B and 1C, an architecture with a common cathode grid 130 and CMOS panel 120 protrusions (microbumps 114) to the p or anode contact 124 of each pixel 116 is used. One advantage of this configuration is that the CMOS layout is symmetrical and the path lengths between the die area and the cathode contact are the same, providing good current injection uniformity. In one or more embodiments, a driver circuit 140 is used to control the current provided to each pixel individually.

In one or more embodiments, the staggered region length can vary between hundreds of microns and several millimeters. In one or more embodiments, the staggered regions can be symmetrical. In other embodiments, the staggered regions can be asymmetrical. Each staggered region with different polarities is electrically isolated by a region several microns wide. In one or more embodiments, a top CMOS current distribution layer for the _Vcat path is used because it simplifies the interconnection with the common cathode contact. In some embodiments, a second current distribution layer (or multiple current distribution layers) is used for the _Vled path. The _Vled current will reach the second current distribution layer connected to the p-contact 124 of each driver unit through the electrical vias located on the contact area. In one or more embodiments, a large cathode redistribution ring 112 surrounding the four sides of the die area is used to evenly distribute current around the die.

Referring to FIG. 1D , a top view of the CMOS second current distribution layer 150 is illustrated. In one or more embodiments, the common power supply voltage V _led 154 surrounds the perimeter of the V _led grid 136 and includes a V _led 104 contact area. The common power supply voltage V _led 154 has staggered cathode current distribution areas 102. In one or more embodiments, the cathode current does not flow through the cathode current distribution areas 102. Therefore, in some embodiments not shown, the cathode current distribution areas 102 may not exist, thereby expanding the common power supply voltage V _led 154.

IE illustrates a common cathode 155 according to one or more embodiments. The outer region of the cathode redistribution ring 112 overlaps the cathode microbumps 106. The cathode redistribution ring 112 surrounds the common cathode grid 130. The common cathode grid 130 contacts each pixel 116 at the pixel side.

In one or more embodiments not shown, as an alternative, an inverted architecture in which a common anode (rather than a common cathode) and a CMOS panel protrudes to the n-contact of each pixel may also be used. In this case, NMOS transistors will be used in driver 140 instead of PMOS transistors.

2A-2C show an alternative embodiment in which a CMOS power layer layout 200 has small staggered cathode distribution areas 202, 204 (alternating _Vcat and _Vled contact areas 202, 204) and a large cathode redistribution ring 212 for current distribution around the four sides of the die area. With this layout, the current is evenly distributed over the four sides of the die area, and the additional current distribution layers connected in parallel can be used primarily to reduce ohmic losses. As a result, ohmic power losses and current density in the microbumps are significantly reduced. In addition, only one type of cathode microbump (uBump or μBump) 206 is required, which simplifies the CMOS panel manufacturing process.

Figure 2A is a view 200 of a CMOS top layer. Figure 2B is a view 250 of a CMOS second current distribution layer. Figure 2C is a view 255 of a common cathode.

2A, all four sides of the panel 200 can be used to place staggered contact areas. In one or more embodiments, the free space on the short side 210 of the panel is used to place addressing circuits, driver components, sensors (sense), etc. Staggered V _led contact areas 204 and cathode 202 contact areas are placed around the four sides 208, 210 of the panel 200.

In one or more embodiments, a large cathode redistribution ring 212 on the V _led and V _cat circuits is used to distribute current along the four sides 208, 210 of the panel. Note that the cathode redistribution ring 212 of one or more embodiments is a full ring and not a u-shaped ring. As shown, only the top and bottom sides of the display 200 are used for current injection. In one or more embodiments, the cathode redistribution ring 212 surrounds the pixel die area, the common cathode grid 230. The pixel die area 230 includes a plurality of pixels (not shown).

In one or more embodiments, the staggered region is made of at least three contact regions (alternating V _cat 202 contact regions and V _led 204 contact regions). In the embodiment shown in FIG. 2A , the staggered region is made of ten cathode contacts 202 and eight V _led contact 204 regions periodically distributed along the four sides 208 , 210 of the CMOS panel 200. In one or more embodiments, the greater the number of alternating V _led 204 and cathode 202 contact regions, the better the current distribution will be. Therefore, in one or more embodiments, more than three or more than five contact regions are used. In some embodiments, there are at least ten cathode 202 contact regions and at least eight V _led 204 contact regions.

In one or more embodiments, alternating V _led 204 and cathode 202 contact areas are located on the long sides 208 of the CMOS panel 200 and along both short sides 210 of the panel 200 .

In one or more embodiments, the staggered region length can vary between hundreds of microns and several millimeters. In one or more embodiments, the staggered regions can be symmetrical. In other embodiments, the staggered regions can be asymmetrical. Each staggered region with different polarities is electrically isolated by a region several microns wide. In one or more embodiments, a top CMOS current distribution layer for the _Vcat path is used because it simplifies the interconnection with the common cathode contact. In some embodiments, a second current distribution layer (or multiple current distribution layers) is used for the _Vled path. The _Vled current will pass through the electrical vias located on the contact area to reach the second current distribution layer connected to the p contact of each driver unit. In one or more embodiments, a large cathode redistribution ring 212 surrounding the four sides of the die area is used to evenly distribute current around the die.

Referring to FIG. 2B , a CMOS second current distribution layer 250 is illustrated. In one or more embodiments, a common power supply voltage V _led 254 surrounds the periphery of the die area 230 and includes a V _led 204 contact area. The common power supply voltage V _led 254 has staggered cathode current distribution areas 202. In one or more embodiments, the cathode current does not flow through the cathode current distribution area 202. Therefore, in some embodiments not shown, the cathode current distribution area 202 may not exist, thereby expanding the common power supply voltage V _led 254.

2C illustrates a common cathode 255 according to one or more embodiments. The outer area of the cathode redistribution ring 212 overlaps the cathode microbumps 206. The cathode redistribution ring 212 surrounds the common cathode grid 230. The common cathode grid 230 contacts each pixel on the pixel side.

Traditionally, the CMOS power layer _Vcat layout has very high current density in the outermost cathode microbumps. This may be caused by the external contact pads mainly supplying current to the outermost corner cathode microbumps. Over time, high current density and temperature can accelerate the failure mechanism of metal-to-metal connections. If cracks or delamination occur in one cathode microbump, current will not flow through this microbump, and the maximum current density of adjacent microbumps will also increase sequentially.

3A and 3B, in one or more embodiments, a solution to reduce current density in microbumps 306 is to include an insulating region 360 between the outer _Vcat pads and the outermost microbumps 306x in common cathode grid 330. FIG3B is an enlarged view of region 370 of FIG3A.

In one or more embodiments, the DC current between the external _Vcat pad in the common cathode grid 330 and the outermost corner microbump 306x can then be reduced, and the current density in the cathode microbump 306 can be reduced accordingly. In one or more embodiments, the insulating region 360 allows the risk of failure of the outermost corner microbump 306x due to high current density to be reduced. The insulating region 360 does not completely prevent the current from reaching the outermost corner microbump 306x. To this end, there will be a gap 345 of at least 10μm between the insulating region 360 and the outermost corner cathode microbump 306x. In order to reduce current injection on at least two microbumps 306, the length of the insulating region 360 will be at least 80μm. In one or more embodiments, the insulating region 360 includes two vertical etch lines to reduce current injection from both sides.

In some embodiments, the insulating region 360 comprises an etched opening. In other embodiments, the insulating region 360 comprises a dielectric material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), aluminum nitride (AlN), and combinations thereof. One skilled in the art will recognize that the use of a chemical formula such as SiO to represent silicon oxide does not imply any particular stoichiometric relationship between the elements. The chemical formula simply identifies the major elements of the film.

Visualization systems, such as virtual reality systems and augmented reality systems, are becoming increasingly common in fields such as entertainment, education, medicine, and business.

In a virtual reality system, a display may present a view of a scene (such as a three-dimensional scene) to a user. The user may move within the scene, such as by repositioning the user's head or by walking. The virtual reality system may detect the user's movement and change the view of the scene to account for the movement. For example, when the user rotates the user's head, the system may present a view of the scene that changes in the view direction to match the user's gaze. In this way, the virtual reality system may simulate the user's presence in the three-dimensional scene. In addition, the virtual reality system may receive tactile sensory input, such as from a wearable position sensor, and may optionally provide tactile feedback to the user.

In an augmented reality system, a display can incorporate elements from the user's surroundings into the view of a scene. For example, an augmented reality system can add text subtitles and/or visual elements to the view of the user's surroundings. For example, a retailer can use an augmented reality system to show a user what a piece of furniture would look like in a room in the user's home by combining a visualization of the piece of furniture on top of a captured image of the user's surroundings. As the user moves around the user's room, the visualization takes into account the user's movement and changes the visualization of the furniture in a manner consistent with the movement. For example, an augmented reality system can place a virtual chair in a room. The user can stand in front of the virtual chair location in the room to view the front of the chair. The user can move to an area behind the virtual chair location in the room to view the back of the chair. In this way, the augmented reality system can add elements to the dynamic view of the user's surroundings.

6 shows a block diagram of an example of a visualization system 10 utilizing a μLED array of one or more embodiments. The visualization system 10 may include a wearable housing 12, such as a headset or goggles. The housing 12 may mechanically support and house the elements detailed below. In some examples, one or more of the elements detailed below may be included in one or more additional housings that may be separate from the wearable housing 12 and may be coupled to the wearable housing 12 wirelessly and/or via a wired connection. For example, a separate housing may reduce the weight of the wearable goggles, such as by including batteries, radios, and other elements. The housing 12 may include one or more batteries 14 that may power any or all of the elements detailed below. The housing 12 may include circuitry that may be electrically coupled to an external power source, such as a wall outlet, to charge the battery 14. The housing 12 may include one or more radios 16 to wirelessly communicate with a server or network via a suitable protocol, such as WiFi.

The visualization system 10 may include one or more sensors 18, such as optical sensors, audio sensors, tactile sensors, thermal sensors, gyroscope sensors, time-of-flight sensors, triangulation-based sensors, and the like. In some examples, one or more of these sensors may sense the location, position, and/or orientation of the user. In some examples, one or more sensors 18 may generate sensor signals in response to the sensed location, position, and/or orientation. The sensor signals may include sensor data corresponding to the sensed location, position, and/or orientation. For example, the sensor data may include a depth map of the surrounding environment. In some examples, such as for an augmented reality system, one or more sensors 18 may capture real-time video images of the surrounding environment near the user.

The visualization system 10 may include one or more video generation processors 20. The one or more video generation processors 20 may receive scene data representing a three-dimensional scene from a server and/or a storage medium, such as a set of position coordinates of an object in the scene or a depth map of the scene. The one or more video generation processors 20 may receive one or more sensor signals from one or more sensors 18. In response to the scene data representing the surrounding environment and at least one sensor signal representing the location and/or orientation of the user relative to the surrounding environment, the one or more video generation processors 20 may generate at least one video signal corresponding to a view of the scene. In some examples, the one or more video generation processors 20 may generate two video signals, one for each eye of the user, the two video signals representing views of the scene from the perspective of the left eye and the right eye of the user, respectively. In some examples, the one or more video generation processors 20 may generate more than two video signals and combine the video signals to provide one video signal for both eyes, two video signals for both eyes, or other combinations.

The visualization system 10 may include one or more light sources 22 that may provide light for a display of the visualization system 10. Suitable light sources 22 may include light emitting diodes, monolithic light emitting diodes, multiple light emitting diodes, arrays of light emitting diodes, arrays of light emitting diodes disposed on a common substrate, segmented light emitting diodes disposed on a single substrate and having individually addressable and controllable (and/or controllable in groups and/or molecular sets) light emitting diode elements, arrays of micro light emitting diodes (microLEDs), and the like.

The light emitting diode may be a white light emitting diode. For example, the white light emitting diode may emit excitation light, such as blue light or violet light. The white light emitting diode may include one or more phosphors that may absorb some or all of the excitation light and, in response, may emit phosphor light (such as yellow light) having a wavelength greater than the wavelength of the excitation light.

One or more light sources 22 may include light emitting elements having different colors or wavelengths. For example, the light source may include a red light emitting diode that may emit red light, a green light emitting diode that may emit green light, and a blue light emitting diode that may emit blue light. The red light, green light, and blue light are combined in a specific ratio to produce any suitable color that is visually perceptible in the visible portion of the electromagnetic spectrum.

The visualization system 10 may include one or more modulators 24. The modulators 24 may be implemented in one of at least two configurations.

In a first configuration, modulator 24 may include circuitry that can directly modulate light source 22. For example, light source 22 may include an array of light emitting diodes, and modulator 24 may directly modulate the electrical power, voltage, and/or current directed to each light emitting diode in the array to form modulated light. Modulation may be performed in an analog manner and/or in a digital manner. In some examples, light source 22 may include an array of red light emitting diodes, an array of green light emitting diodes, and an array of blue light emitting diodes, and modulator 24 may directly modulate the red light emitting diodes, the green light emitting diodes, and the blue light emitting diodes to form modulated light to produce a particular image.

In a second configuration, the modulator 24 may include a modulation panel, such as a liquid crystal panel. The light source 22 may generate uniform illumination or nearly uniform illumination to illuminate the modulation panel. The modulation panel may include pixels. Each pixel may selectively attenuate a corresponding portion of the modulation panel area in response to an electrical modulation signal to form modulated light. In some examples, the modulator 24 may include a plurality of modulation panels that may modulate light of different colors. For example, the modulator 24 may include a red modulation panel that may attenuate red light from a red light source (such as a red light emitting diode), a green modulation panel that may attenuate green light from a green light source (such as a green light emitting diode), and a blue modulation panel that may attenuate blue light from a blue light source (such as a blue light emitting diode).

In some examples of the second configuration, the modulator 24 may receive uniform white light or nearly uniform white light from a white light source, such as a white light emitting diode. The modulation panel may include a wavelength selective filter on each pixel of the modulation panel. The panel pixels may be arranged in groups, such as three or four groups, where each group may form a pixel of a color image. For example, each group may include a panel pixel with a red filter, a panel pixel with a green filter, and a panel pixel with a blue filter. Other suitable configurations may also be used.

The visualization system 10 may include one or more modulation processors 26 that may receive a video signal (such as from one or more video generation processors 20) and in response may generate an electrical modulation signal. For configurations in which the modulator 24 directly modulates the light source 22, the electrical modulation signal may drive the light source 24. For configurations in which the modulator 24 includes a modulation panel, the electrical modulation signal may drive the modulation panel.

The visualization system 10 may include one or more beam combiners 28 (also referred to as beam splitters 28) that may combine light beams of different colors to form a single polychromatic light beam. For configurations in which the light source 22 may include a plurality of light emitting diodes of different colors, the visualization system 10 may include one or more wavelength-sensitive (e.g., dichroic) beam splitters 28 that may combine light of different colors to form a single polychromatic light beam.

The visualization system 10 can direct the modulated light toward the eyes of the observer in one of at least two configurations. In the first configuration, the visualization system 10 can be used as a projector and can include suitable projection optics 30 that can project the modulated light onto one or more screens 32. The screen 32 can be positioned at a suitable distance from the user's eyes. The visualization system 10 can optionally include one or more lenses 34 that can position a virtual image of the screen 32 at a suitable distance from the eyes, such as a close-focus distance, such as 500mm, 750mm, or another suitable distance. In some examples, the visualization system 10 can include a single screen 32 so that the modulated light can be directed toward both eyes of the user. In some examples, the visualization system 10 can include two screens 32 so that the modulated light from each screen 32 can be directed toward the corresponding eye of the user. In some examples, the visualization system 10 can include more than two screens 32. In a second configuration, the visualization system 10 can direct the modulated light directly into one or both eyes of the observer. For example, projection optics 30 may form an image on the retina of one eye of a user, or may form an image on each retina of both eyes of a user.

For some configurations of the augmented reality system, the visualization system 10 may include a display that is at least partially transparent so that the user can view the user's surroundings through the display. For such configurations, the augmented reality system may generate modulated light corresponding to an enhancement of the surroundings, rather than the surroundings themselves. For example, in the example of a retailer displaying chairs, the augmented reality system may direct modulated light corresponding to the chairs, rather than the rest of the room, toward the screen or toward the user's eyes.

The present disclosure is now described with reference to the following examples. Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or implemented in various ways.

Example

Comparative Example 1

A CMOS layout with two current distribution layers was formed. The CMOS layout has a u-shaped cathode ring. The current density of the CMOS layout was calculated. As shown in FIG. 4A , the current density is non-uniform.

Example 2

A CMOS layout with eight staggered current distribution regions was formed. The current density of the CMOS layout with eight staggered current distribution regions was calculated. As shown in FIG. 4B , the current density is uniform.

Table 1 shows a comparison of power losses between a Comparative Example 1 CMOS layout with two current distribution layers and an Example 2 CMOS layout with staggered regions on the bottom and top panel sides and with a continuous current distribution ring. In the power layer layout of one or more embodiments, ohmic losses are reduced by more than 40%. The average current density through the cathode microbump is also much lower.

Table 1: Comparison of power losses

Example 3

A CMOS layout with eight staggered current distribution regions was formed. The layout had no insulating region between the external _Vcat pads and the outermost micro-bump vias. The current density was measured and shown in FIG7A .

Example 4

A CMOS layout with eight staggered current distribution regions was formed. The layout had an insulating region between the external _Vcat pad and the outermost microbump via. Current density was measured. FIGS. 5A and 5B compare the current density in the cathode microbump between a layout with (Example 4) and without (Example 3) an insulating region between the external _Vcat contact region and the outermost corner microbump. The current density in the outermost corner cathode microbump of the layout with the insulating region was reduced by more than 30%.

Example

Various embodiments are listed below. It will be understood that the embodiments listed below can be combined with all aspects of the scope of the present invention and other embodiments.

Embodiment (a) A CMOS power layer comprises: a cathode redistribution ring having an inner portion and an outer portion, the inner portion surrounding the periphery of a die pixel region, the outer portion comprising a common power supply voltage V _led interleaved with a cathode current distribution region; and a plurality of cathode microbumps contacting the inner portion of the cathode redistribution ring along the periphery of the die pixel region.

Embodiment (b) The CMOS power layer according to embodiment (a), wherein the common power voltage V _led and the cathode current distribution region are staggered on both sides of the die pixel region.

Embodiment (c) The CMOS power layer according to embodiments (a) to (b), wherein the common power voltage V _led and the cathode current distribution region are staggered on four sides of the die pixel region.

Embodiment (d) The CMOS power layer according to embodiments (a) to (c), wherein there are at least three common power supply voltages V _led interleaved with at least three cathode current distribution regions.

Embodiment (e) The CMOS power layer according to embodiments (a) to (d), further comprising an insulating region on the cathode redistribution ring adjacent to one of the plurality of cathode micro-bumps.

Embodiment (f) The CMOS power layer according to embodiments (a) to (e), wherein the insulating region comprises an etched line.

Embodiment (g) The CMOS power layer according to embodiments (a) to (f), wherein the insulating region comprises a dielectric material.

Embodiment (h) The CMOS power layer according to embodiments (a) to (g), further comprising a plurality of PMOS transistors connected to the die pixel region.

Embodiment (i) The CMOS power layer of embodiments (a) to (h), wherein the plurality of cathode micro-bumps are electrically connected to a common cathode grid.

Embodiment (j) The CMOS power layer according to embodiments (a) to (i), wherein the die pixel region comprises a plurality of pixels.

Embodiment (k) The CMOS power layer according to embodiments (a) to (j), wherein the size of the insulating region is greater than 80 μm.

Embodiment (l). A CMOS layout includes: a power layer on a substrate, the power layer having a plurality of alternating V _led contact areas and cathode contact areas uniformly dispersed along at least two sides of the power layer; a cathode current redistribution ring extending along four sides of the power layer; a plurality of cathode microbumps connecting each of the plurality of alternating V _led contact areas and cathode contact areas to corresponding p contacts of a plurality of pixels; and a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode microbumps.

Embodiment (m) The CMOS layout according to embodiment (l), wherein the V _led contact region and the cathode contact region are staggered on both sides.

Embodiment (n) The CMOS layout according to embodiments (l) to (m), wherein the V _led contact regions and the cathode contact regions are staggered on four sides.

Embodiment (o) The CMOS layout of embodiments (1) to (n) wherein there are at least three V _led contact regions alternating with at least three cathode contact regions.

Embodiment (p) The CMOS layout according to embodiments (1) to (o), further comprising an insulating region adjacent to one of the plurality of cathode micro-bumps on the cathode current redistribution ring.

Embodiment (q). The CMOS layout of embodiments (l) to (p), wherein the insulating region comprises an etched line.

Embodiment (r) The CMOS layout of embodiments (l) to (q), wherein the insulating region comprises a dielectric material.

Embodiment (s) The CMOS layout according to embodiments (l) to (r), further comprising a plurality of PMOS transistors connected in parallel to at least one of the plurality of pixels.

Embodiment (t) The CMOS layout according to embodiments (1) to (s), wherein the size of the insulating region is greater than 80 μm.

Embodiment (u). A CMOS power layer, comprising: a cathode redistribution ring having an inner portion and an outer portion, the inner portion surrounding the periphery of a die pixel region, the outer portion comprising a region common power voltage V _led interleaved with cathode current distribution regions along a first side, a second side, a third side, and a fourth side of the CMOS power layer; and a plurality of cathode microbumps contacting the inner portion of the cathode redistribution ring along the periphery of the die pixel region.

Embodiment (v) The CMOS power layer of embodiment (u), wherein there are at least three common supply voltage V _led regions interleaved with at least three cathode current distribution regions.

Embodiment (w) The CMOS power layer according to embodiments (u) to (v), further comprising an insulating region on the cathode redistribution ring adjacent to one of the plurality of cathode micro-bumps.

Embodiment (x) The CMOS power layer according to embodiments (u) to (w), wherein the insulating region comprises an etched line.

Embodiment (y). The CMOS power layer according to embodiments (u) to (x), wherein the insulating region comprises a dielectric material.

Embodiment (z) The CMOS power layer according to embodiments (u) to (y), further comprising a plurality of PMOS transistors connected to the die pixel region.

Embodiment (aa). The CMOS power layer of embodiments (u) to (z), wherein the plurality of cathode micro-bumps are electrically connected to a common cathode grid.

Embodiment (bb) The CMOS power layer according to embodiments (u) to (aa), wherein the die pixel region comprises a plurality of pixels.

Embodiment (cc) The CMOS power layer according to embodiments (u) to (bb), wherein the size of the insulating region is greater than 80 μm.

Embodiment (dd) The CMOS power layer of embodiments (u) to (cc), wherein the insulating region is at least 10 μm away from one of the plurality of cathode micro-bumps.

Embodiment (ee). A CMOS layout includes: a power layer on a substrate, the power layer having a plurality of alternating V _led contact areas and cathode contact areas dispersed along a first side, a second side, a third side, and a fourth side of the power layer; a cathode current redistribution ring extending along the first side, the second side, the third side, and the fourth side of the power layer; a plurality of cathode microbumps connecting each of the plurality of alternating V _led contact areas and cathode contact areas to a corresponding p-contact of a plurality of pixels; and a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode microbumps.

Embodiment (ff) The CMOS layout of embodiment (ee) wherein there are at least three V _led contact regions alternating with at least three cathode contact regions.

Embodiment (gg) The CMOS layout of embodiments (ee) to (ff), further comprising an insulating region on the cathode current redistribution ring adjacent to one of the plurality of cathode micro-bumps.

Embodiment (hh). The CMOS layout of embodiments (ee) to (gg), wherein the insulating region comprises an etched line.

Embodiment (ii) The CMOS layout according to embodiments (ee) to (hh), further comprising a plurality of PMOS transistors connected in parallel to at least one of the plurality of pixels.

Embodiment (jj) The CMOS power layer according to embodiments (ee) to (ii), wherein the size of the insulating region is greater than 80 μm.

Embodiment (kk) The CMOS layout of embodiments (ee) to (jj), wherein the insulating region is at least 10 μm away from one of the plurality of cathode micro-bumps.

Embodiment (ll). The CMOS layout of embodiments (ee) to (kk), wherein the insulating region comprises a dielectric material.

Embodiment (mm) The CMOS layout according to embodiments (ee) to (ll), wherein the alternating V _led contact regions and cathode contact regions are evenly distributed along the first side, the second side, the third side and the fourth side of the power layer.

Embodiment (nn). A CMOS power layer comprises: a cathode redistribution ring having an inner portion and an outer portion, the inner portion surrounding the periphery of a die pixel region, the outer portion comprising a region common power supply voltage V _led interlaced with cathode current distribution regions; a plurality of cathode microbumps contacting the inner portion of the cathode redistribution ring along the periphery of the die pixel region; and an insulating region on the cathode redistribution ring adjacent to one of the plurality of cathode microbumps.

Embodiment (oo) The CMOS power layer according to embodiment (nn), wherein the common power supply voltage V _led and the cathode current distribution area are staggered on both sides of the die pixel area.

Embodiment (pp) The CMOS power layer according to embodiments (nn) to (oo), wherein the common power voltage V _led and the cathode current distribution region are staggered on four sides of the die pixel region.

Embodiment (qq) The CMOS power layer according to embodiments (nn) to (pp), wherein there are at least three common power supply voltages V _led interleaved with at least three cathode current distribution regions.

Embodiment (rr). The CMOS power layer of embodiments (nn) to (qq), wherein the insulating region comprises an etched line.

Embodiment (ss) The CMOS power layer of embodiments (nn) to (rr), wherein the insulating region comprises a dielectric material.

Embodiment (tt). The CMOS power layer of embodiments (nn) to (ss), wherein the plurality of cathode micro-bumps are electrically connected to a common cathode grid.

Embodiment (uu). The CMOS power layer of embodiments (nn) to (tt), wherein the die pixel region comprises a plurality of pixels.

Embodiment (vv) The CMOS power layer according to embodiments (nn) to (uu), wherein the size of the insulating region is greater than 80 μm.

Embodiment (ww) The CMOS power layer according to embodiments (nn) to (vv), wherein the insulating region is at least 10 μm away from one of the plurality of cathode micro-bumps.

Embodiment (xx) The CMOS power layer of embodiments (nn) to (ww), wherein there are eight common power supply voltages V _led interleaved with ten cathode current distribution areas.

Embodiment (yy). A CMOS layout includes: a power layer on a substrate, the power layer having a plurality of alternating V _led contact areas and cathode contact areas uniformly dispersed along at least two sides of the power layer; a cathode current redistribution ring extending along four sides of the power layer; a plurality of cathode microbumps connecting each of the plurality of alternating V _led contact areas and cathode contact areas to corresponding p contacts of a plurality of pixels; an insulating region adjacent to one of the plurality of cathode microbumps on the cathode current redistribution ring; and a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode microbumps.

Embodiment (zz). The CMOS layout according to embodiment (yy), wherein the V _led contact region and the cathode contact region are staggered on both sides.

Embodiment (aaa). The CMOS layout of embodiments (yy) to (zz), wherein the V _led contact regions and the cathode contact regions are staggered on four sides.

Embodiment (bbb) The CMOS layout of embodiments (yy) to (aaa) wherein there are at least three V _led contact regions alternating with at least three cathode contact regions.

Embodiment (ccc) The CMOS layout of embodiments (yy) to (bbb), wherein the insulating region comprises an etched line.

Embodiment (ddd). The CMOS layout of embodiments (yy) to (ccc), wherein the insulating region comprises a dielectric material.

Embodiment (eee) The CMOS layout according to embodiments (yy) to (ddd), further comprising a plurality of PMOS transistors connected in parallel to at least one of the plurality of pixels.

Embodiment (fff) The CMOS layout according to embodiments (yy) to (eee), wherein the size of the insulating region is larger than 80 μm.

Embodiment (ggg) The CMOS layout of embodiments (yy) to (fff), wherein the insulating region is at least 10 μm away from one of the plurality of cathode micro-bumps.

In the context of describing the materials and methods discussed herein (especially in the context of the following claims), the use of the terms "one" and "an" and "the" and similar references should be interpreted as covering both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein, the description of the range of values herein is intended only to be used as a shorthand method for individually referring to each individual value falling within the range, and each individual value is incorporated into this specification as if it is individually described herein. Unless otherwise indicated herein or clearly contradicted by the context in other ways, all methods described herein can be performed in any suitable order. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the materials and methods, and unless otherwise claimed, does not limit the scope. Any language in this specification should not be interpreted as indicating that any unclaimed element is essential for practicing the disclosed materials and methods.

Throughout the specification, the terms first, second, third, etc. may be used to describe various elements herein, and these elements should not be limited by these terms. These terms may be used to distinguish one element from another.

Throughout this specification, reference to a layer, region, or substrate being "on" or extending to another element means that it may be directly on or directly extended to another element, or there may be intermediate elements. When an element is referred to as being "directly on" or "directly extending to" another element, there may be no presence of intermediate elements. In addition, when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to another element and/or connected or coupled to another element via one or more intermediate elements. When an element is referred to as being "directly connected" or "directly coupled" to another element, there is no presence of intermediate elements between the element and the other element. It will be understood that these terms are intended to cover different orientations of elements, in addition to any orientation depicted in the figures.

Relative terms such as "below," "above," "upper," "lower," "horizontal," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

Throughout this specification, reference to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in an embodiment," or "in an embodiment" throughout this specification does not necessarily refer to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics are combined in any suitable manner.

Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrations of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, it is intended that the present disclosure include modifications and variations within the scope of the appended claims and their equivalents.

Claims (20)

1. A CMOS power layer, comprising: a cathode redistribution ring having an inner portion surrounding the perimeter of the die pixel region and an outer portion including a common supply voltage V _led interleaved with cathode current distribution regions; and A plurality of cathode micro-bumps contact an inner portion of the cathode redistribution ring along a perimeter of the die pixel area. 2 . The CMOS power layer according to claim 1 , wherein the common power supply voltage V _led and the cathode current distribution region are staggered on both sides of the die pixel region. 3 . The CMOS power layer according to claim 1 , wherein the common power supply voltage V _led and the cathode current distribution region are staggered on four sides of the die pixel region. 4 . The CMOS power plane of claim 1 , wherein there are at least three common supply voltages V _led interleaved with at least three cathode current distribution regions. 5 . The CMOS power layer of claim 1 , further comprising an insulating region on the cathode redistribution ring adjacent to one of the plurality of cathode micro-bumps. The CMOS power layer of claim 5 , wherein the insulating region comprises an etched line. 7. The CMOS power layer of claim 5, wherein the insulating region comprises a dielectric material. 8. The CMOS power plane of claim 1, further comprising a plurality of PMOS transistors connected to the die pixel region. 9. The CMOS power layer of claim 1, wherein the plurality of cathode micro-bumps are electrically connected to a common cathode grid. 10. The CMOS power plane of claim 1, wherein the die pixel region comprises a plurality of pixels. 11. The CMOS power layer according to claim 5, wherein the size of the insulating region is greater than 80 μm. 12. A CMOS layout comprising: a power layer on a substrate, the power layer having a plurality of alternating V _led contact areas and cathode contact areas uniformly distributed along at least two sides of the power layer; a cathode current redistribution ring extending along four sides of the power layer; a plurality of cathode microbumps connecting each of the plurality of alternating V _led contact regions and the cathode contact regions to corresponding p contacts of a plurality of pixels; and A common cathode grid electrically connects the plurality of pixels and the plurality of cathode micro-bumps. 13. The CMOS layout of claim 12, wherein the V _led contact region and the cathode contact region are staggered on both sides. 14. The CMOS layout of claim 12, wherein the V _led contact regions and the cathode contact regions are staggered on four sides. 15. The CMOS layout of claim 12, wherein there are at least three _Vled contact regions alternating with at least three cathode contact regions. 16. The CMOS layout of claim 12, further comprising an insulating region on the cathode current redistribution ring adjacent to one of the plurality of cathode micro-bumps. 17. The CMOS power layer of claim 16, wherein the insulating region comprises an etched line. 18. The CMOS power layer of claim 17, wherein the insulating region comprises a dielectric material. 19. The CMOS layout of claim 12, further comprising a plurality of PMOS transistors connected in parallel with at least one of the plurality of pixels. 20. The CMOS layout of claim 16, wherein the size of the insulating region is greater than 80 μm.