CN118039605A - Semiconductor packaging structure and preparation method thereof - Google Patents

Abstract

The present disclosure provides a semiconductor packaging structure and a preparation method thereof, wherein the semiconductor packaging structure includes an interposer, a conductive via and a capacitor; the interposer includes a first surface and a second surface opposite to each other in the thickness direction, and the conductive via and the capacitor are arranged in the interposer at intervals; the opposite ends of the conductive via extend to the first surface and the second surface respectively; the capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer stacked in sequence; at least part of the first electrode layer is close to the first surface, and the interposer is electrically led out of the first surface through the first conductive structure; at least part of the second electrode layer is close to the second surface, and the interposer is electrically led out of the second surface through the second conductive structure. The present disclosure can effectively simplify the structure of the capacitor in the semiconductor packaging structure, reduce the difficulty of its preparation, and improve the capacitance at the same time.

Description

Semiconductor packaging structure and preparation method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure and a preparation method thereof.

Background technique

Semiconductor packaging is a process in which multiple semiconductor devices are arranged in a packaging structure in a vertical stack or horizontally side by side manner, and the packaging structure is used to protect the semiconductor devices. It is widely used in semiconductor equipment or devices.

Semiconductor packaging includes a packaging substrate, a semiconductor device to be packaged, and a packaging layer. The semiconductor device to be packaged can be multiple chips, and multiple chips are stacked or arranged side by side on the packaging substrate. The outside of the multiple chips is packaged through the packaging layer to avoid chip exposure and ensure the protection effect of the chip. Among them, a silicon interposer (SiInterposer) is provided between different chips as a metal interconnection structure to realize signal connection between different chips. A through silicon via structure (Through Silicon Vias, TSV for short) and a deep trench capacitor (Deep Trench Capacitor, DTC for short) are provided in the silicon interposer.

However, the structure of the deep trench capacitor in the silicon interposer is relatively complex, the manufacturing is relatively difficult, and the capacitance needs to be improved.

Summary of the invention

The present disclosure provides a semiconductor packaging structure and a preparation method thereof, which can effectively simplify the structure of a capacitor in the semiconductor packaging structure, reduce the difficulty of preparation thereof, and improve the capacitance.

In a first aspect, the present disclosure provides a semiconductor package structure, including an interposer, a conductive via, and a capacitor;

The intermediary layer comprises a first surface and a second surface opposite to each other in a thickness direction, and the conductive vias and the capacitor spacers are arranged in the intermediary layer;

The opposite ends of the conductive through hole extend to the first surface and the second surface respectively; the capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer stacked in sequence; at least part of the first electrode layer is close to the first surface, and the intermediate layer is electrically led out through the first surface through the first conductive structure; at least part of the second electrode layer is close to the second surface, and the intermediate layer is electrically led out through the second conductive structure through the second surface.

In the above semiconductor packaging structure, optionally, the capacitor includes a plurality of capacitors, and the plurality of capacitors are arranged at intervals in the intermediate layer.

In the above semiconductor package structure, optionally, one end of the first electrode layer close to the first surface, one end of the conductive through hole close to the first surface, and the first surface are flush.

In the above semiconductor package structure, optionally, a third conductive structure is further included, and one end of the conductive through hole close to the first surface is connected to the third conductive structure, and the interposer is electrically led out through the third conductive structure;

The first conductive structure and the third conductive structure are in the same layer and made of the same material.

In the above-mentioned semiconductor packaging structure, optionally, there is a gap between the second electrode layer close to the second surface and the second surface, the second conductive structure is embedded in the intermediate layer between the second surface and the second electrode layer, one end of the second conductive structure is connected to the second electrode layer, and the other end of the second conductive structure is led to the second surface.

In the above semiconductor package structure, optionally, it further includes a fourth conductive structure, the fourth conductive structure is located on the second surface, and the second conductive structure is connected to the fourth conductive structure;

When there are multiple capacitors, the second electrode layers of the multiple capacitors are connected to the same fourth conductive structure through the second conductive structure; or, when there are multiple fourth conductive structures, the second electrode layers of the multiple capacitors are connected to different fourth conductive structures through the corresponding second conductive structures.

In the above semiconductor packaging structure, optionally, it also includes a fifth conductive structure, which is located on the second surface, and one end of the conductive through hole close to the second surface is flush with the second surface and connected to the fifth conductive structure, and the intermediate layer is electrically led out through the fifth conductive structure.

In the above semiconductor packaging structure, optionally, the interposer includes an interposer body layer and a dielectric layer, the dielectric layer is disposed close to the first surface of the interposer, and the interposer body layer is disposed close to the second surface of the interposer;

Furthermore, at least a portion of the dielectric layer is distributed between the conductive via and the interposer body layer; and/or at least a portion of the dielectric layer is distributed between the capacitor and the interposer body layer.

In a second aspect, the present disclosure provides a method for preparing a semiconductor packaging structure, comprising:

Providing an interposer, the interposer comprising a first surface and a second surface opposite to each other in a thickness direction;

Conductive vias and capacitors are formed in the intermediary layer. The conductive vias and capacitors are arranged at intervals. The opposite ends of the conductive vias extend to the first surface and the second surface respectively. The capacitor includes a first electrode layer, a capacitor dielectric layer, and a second electrode layer stacked in sequence; at least a portion of the first electrode layer is close to the first surface, and the intermediary layer is electrically led out through the first surface through the first conductive structure; at least a portion of the second electrode layer is close to the second surface, and the intermediary layer is electrically led out through the second surface through the second conductive structure.

In the above-mentioned method for preparing a semiconductor package structure, optionally, forming a conductive via and a capacitor includes:

forming a conductive via in the interposer;

A capacitor groove is formed in the intermediary layer, wherein the bottom of the capacitor groove and the bottom of the conductive through hole are both spaced apart from the bottom of the intermediary layer, and the distance between the bottom of the capacitor groove and the bottom of the intermediary layer is greater than the distance between the bottom of the conductive through hole and the bottom of the intermediary layer;

A capacitor is formed in the capacitor trench.

In the above-mentioned method for preparing a semiconductor package structure, optionally, forming a capacitor in the capacitor trench includes:

forming a second electrode layer, the second electrode layer being located in the capacitor trench, and forming a first trench in the second electrode layer;

forming a capacitor dielectric layer, the capacitor dielectric layer being located in the first groove, and forming a second groove in the capacitor dielectric layer;

A first electrode layer is formed, the first electrode layer is located in the second groove, and the first electrode layer, the capacitor dielectric layer and the second electrode layer together form a capacitor.

In the above-mentioned method for preparing a semiconductor package structure, optionally, after forming the capacitor, the method further comprises:

Planarizing the top of the conductive via, the top of the capacitor, and the top of the interposer so that the top surface of the conductive via, the top surface of the capacitor, and the top surface of the interposer are flush, and the top surface of the interposer forms the first surface;

A first conductive structure and a third conductive structure are formed, the first conductive structure is connected to the first electrode layer, the third conductive structure is connected to the top of the conductive through hole, and the first conductive structure and the third conductive structure are in the same layer and material.

In the above-mentioned method for preparing a semiconductor package structure, optionally, after forming the first conductive structure and the third conductive structure, the method further includes:

Processing the bottom of the interposer to expose the bottom of the conductive through hole; the processed bottom surface of the interposer forms the second surface;

forming a fourth trench, wherein the fourth trench is located in the interposer layer at the bottom of the capacitor and exposes the second electrode layer of the capacitor;

forming a second conductive structure, wherein the second conductive structure is located in the fourth trench and connected to the exposed second electrode layer;

forming a fourth conductive structure, the fourth conductive structure being located at the bottom of the interposer and connected to the second conductive structure;

A fifth conductive structure is formed, where the fifth conductive structure is located at the bottom of the interposer and connected to the exposed bottom of the conductive through hole.

In the above-mentioned method for preparing a semiconductor packaging structure, optionally, there are multiple capacitors, and the multiple capacitors are arranged at intervals in the intermediate layer;

The second electrode layers of multiple capacitors are all connected to the same fourth conductive structure through the second conductive structure; or, there are multiple fourth conductive structures, and the second electrode layers of multiple capacitors are connected to different fourth conductive structures through corresponding second conductive structures.

In the above-mentioned method for preparing a semiconductor package structure, optionally, providing an interposer includes:

Forming an intermediary body layer;

forming a dielectric layer, the dielectric layer being located on the intermediary body layer, the intermediary body layer and the dielectric layer together forming the intermediary layer, the dielectric layer being disposed close to the first surface of the intermediary layer, and the intermediary body layer being disposed close to the second surface of the intermediary layer;

Furthermore, at least a portion of the dielectric layer is distributed between the conductive via and the interposer body layer; and/or at least a portion of the dielectric layer is distributed between the capacitor and the interposer body layer.

The semiconductor packaging structure and preparation method provided by the present disclosure are as follows: by arranging an interposer, a conductive through hole and a capacitor in the semiconductor packaging structure, the conductive through hole and the capacitor are arranged in the interposer at intervals, and the interposer can protect both. By extending the two ends of the conductive through hole to the first side and the second side of the interposer respectively, it is convenient to connect the components located on both sides of the interposer through the conductive through hole to realize signal transmission between different components. The capacitor can effectively suppress the circuit noise of the conductive through hole and reduce the influence of the circuit voltage on the components packaged by the semiconductor packaging structure. By arranging the first electrode layer and the second electrode layer of the capacitor close to the first side and the second side respectively, and leading the interposer from the first side and the second side respectively through different conductive structures, the structure of the capacitor can be effectively simplified, reducing its preparation difficulty, helping to improve the capacitance of the capacitor, and optimizing the performance of the semiconductor packaging structure.

The construction of the present disclosure as well as other inventive objects and advantageous effects thereof will be more clearly understood through the description of the preferred embodiments in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG1 is a schematic structural diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure;

FIG2 is a schematic diagram of a process for preparing a semiconductor packaging structure according to an embodiment of the present disclosure;

3 is a schematic diagram of a process of forming a conductive via and a capacitor in a method for preparing a semiconductor packaging structure provided by an embodiment of the present disclosure;

FIG4 is a schematic diagram of a process of forming a capacitor in a method for preparing a semiconductor packaging structure provided by an embodiment of the present disclosure;

FIG5 is a schematic diagram of a structure for forming an interposer and conductive vias according to an embodiment of the present disclosure;

FIG6 is a schematic diagram of a structure for forming a capacitor trench according to an embodiment of the present disclosure;

FIG7 is a schematic diagram of a structure for forming a second electrode layer and a capacitor dielectric layer according to an embodiment of the present disclosure;

FIG8 is a schematic diagram of a structure for forming a conductive material according to an embodiment of the present disclosure;

FIG9 is a schematic diagram of a structure for forming a conductive via and a capacitor according to an embodiment of the present disclosure;

FIG10 is a schematic diagram of a structure for forming a first conductive structure and a third conductive structure according to an embodiment of the present disclosure;

FIG11 is a schematic structural diagram of an end portion of an exposed conductive through hole close to the second surface provided by an embodiment of the present disclosure;

FIG. 12 is a schematic structural diagram of forming a second conductive structure provided in an embodiment of the present disclosure.

Description of reference numerals:

100, intermediary layer; 100a, first surface; 100b, second surface; 101, intermediary body layer; 102, dielectric layer; 200, conductive via; 300, capacitor; 301, first electrode layer; 302, capacitor dielectric layer; 303, second electrode layer; 304, extended barrier layer; 400, first conductive structure; 500, second conductive structure; 600, third conductive structure; 700, fourth conductive structure; 800, fifth conductive structure; 900, capacitor trench; 901, second trench; 903, first mask layer; 904, conductive material; 905, sixth conductive structure; 906, second mask layer; 907, etching barrier layer; 908, dielectric layer.

Detailed ways

In semiconductor packaging, a silicon interposer is set between different chips. The silicon interposer serves as a metal interconnect structure to achieve signal transmission between chips. A large number of TSVs and DTCs are integrated in the silicon interposer. The two ends of the TSV are connected to the chips on both sides of the silicon interposer to ensure the interconnection capability of the silicon interposer to the chips. As the driving strength of semiconductor devices increases, the devices have higher current density and greater current transients, resulting in large voltage fluctuations in the circuits where TSVs connect chips in semiconductor packaging, and affecting the working performance of the chips. In response to this, DTC can be used as a decoupling capacitor to suppress noise in the circuits where TSVs connect chips, thereby alleviating the impact of voltage fluctuations on the chips.

In the related art, DTC includes multiple stacked electrode layers, and a dielectric layer is arranged between each two adjacent electrode layers. In the semiconductor package, the multiple electrode layers of DTC are electrically led out through the same side of the silicon interposer. The connection points of the electrical lead-out of the multiple electrode layers are mutually offset on the same side of the silicon interposer, and are respectively located at different depths in the semiconductor package. Multiple conductive pillars are arranged on one side of the silicon interposer. The conductive pillars are at different depths in the semiconductor package, and are respectively connected to the connection points of the conductive layers at different depths, and the electrical signals of different conductive layers are led out through different conductive pillars.

In the above structure, the structure of DTC is relatively complex. To prepare DTC by photolithography, different masks need to be used multiple times, which makes the process cost high. In addition, the depth of the conductive column electrically derived from the electrode layer of DTC is different in the semiconductor package. When forming the conductive plug hole connected to each electrode layer, it is difficult to control the etching depth, the yield is low, and the alignment accuracy of the conductive column and the electrode layer of DTC is required to be high, which increases the difficulty of preparing the conductive column. By setting multiple electrode layers, DTC has a limited increase in capacitance, and the structure of DTC also limits the capacitance of the capacitor.

The semiconductor packaging structure and preparation method provided by the present disclosure are as follows: by arranging an interposer, a conductive through hole and a capacitor in the semiconductor packaging structure, the conductive through hole and the capacitor are arranged in the interposer at intervals, and the interposer can protect both. By extending the two ends of the conductive through hole to the first side and the second side of the interposer respectively, it is convenient to connect the components located on both sides of the interposer through the conductive through hole to realize signal transmission between different components. The capacitor can effectively suppress the circuit noise of the conductive through hole and reduce the influence of the circuit voltage on the components packaged by the semiconductor packaging structure. By arranging the first electrode layer and the second electrode layer of the capacitor close to the first side and the second side respectively, and leading the interposer from the first side and the second side respectively through different conductive structures, the structure of the capacitor can be effectively simplified, reducing its preparation difficulty, helping to improve the capacitance of the capacitor, and optimizing the performance of the semiconductor packaging structure.

In order to make the purpose, technical solution and advantages of the present disclosure clearer, the technical solution in the embodiment of the present disclosure will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present disclosure. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limitations on the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure. The embodiments of the present disclosure are described in detail below in conjunction with the drawings.

Fig. 1 is a schematic diagram of a semiconductor package structure provided by an embodiment of the present disclosure. Referring to Fig. 1 , in a first aspect, the present disclosure provides a semiconductor package structure.

The semiconductor package structure includes an interposer 100 , a conductive via 200 and a capacitor 300 . The interposer 100 includes a first surface 100 a and a second surface 100 b opposite to each other along a thickness direction. The conductive via 200 and the capacitor 300 are arranged in the interposer 100 at intervals.

The opposite ends of the conductive through hole 200 extend to the first surface 100a and the second surface 100b respectively; the capacitor 300 includes a first electrode layer 301, a capacitor dielectric layer 302 and a second electrode layer 303 stacked in sequence; at least part of the first electrode layer 301 is close to the first surface 100a, and through the first conductive structure 400, the intermediate layer 100 is electrically led out through the first surface 100a; at least part of the second electrode layer 303 is close to the second surface 100b, and through the second conductive structure 500, the intermediate layer 100 is electrically led out through the second surface 100b.

It should be noted that the interposer 100 can provide a structural basis for the conductive via 200 and the capacitor 300, and the interposer 100 can be doped or undoped silicon, or silicon on insulator (SOI). The interposer 100 can also be a compound semiconductor of germanium, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide and/or indium arsenide. The thickness direction of the interposer 100 can be the direction shown by X in FIG. 1, and the first surface 100a and the second surface 100b of the interposer 100 opposite to each other along the thickness direction can be the top and bottom surfaces of the interposer 100 shown in FIG. 1.

The conductive vias 200 and the capacitors 300 are arranged at intervals in the interposer 100. The conductive vias 200 and the capacitors 300 may be arranged at intervals along a direction perpendicular to the first surface 100a to the second surface 100b. The direction perpendicular to the first surface 100a to the second surface 100b may be the direction shown by Y in FIG. 1. The conductive vias 200 and the capacitors 300 are arranged at intervals to avoid electrical interference between the two. The opposite ends of the conductive vias 200 extend to the first surface 100a and the second surface 100b, respectively. The two ends of the conductive vias 200 may be electrically connected to the elements on the opposite sides of the interposer 100, respectively, to achieve interconnection of the elements. In some embodiments, the conductive vias 200 and the capacitors 300 may also be arranged at intervals along a direction having an angle less than 90 degrees with the Y direction. This embodiment does not limit the direction in which the two are arranged at intervals.

At least part of the first electrode layer 301 of the capacitor 300 in the present disclosure is close to the first surface 100a, and at least part of the second electrode layer 303 is close to the second surface 100b. The capacitor 300 is distributed in the entire intermediate layer 100 along the thickness direction of the intermediate layer 100. In this way, the depth of the capacitor 300 in the intermediate layer 100 can be effectively increased, thereby helping to improve the capacitance of the capacitor 300.

The first electrode layer 301 close to the first surface 100a is electrically led out of the intermediary layer 100 through the first conductive structure 400 via the first surface 100a, and the second electrode layer 303 close to the second surface 100b is electrically led out of the intermediary layer 100 through the second conductive structure 500 via the second surface 100b. In this way, the first conductive structure 400 and the second conductive structure 500 are respectively distributed on opposite sides of the intermediary layer 100 along the thickness direction, which can effectively avoid mutual interference between the two and reduce the difficulty of setting the electrical lead-out structure of the capacitor 300. In addition, only one electrode layer is distributed on the same side of the intermediary layer 100 along the thickness direction, so the alignment difficulty of the electrode layer and the conductive structure is relatively small. The present disclosure can not only effectively simplify the structure of the capacitor 300, reduce the difficulty of preparing the capacitor 300, but also help to increase the capacitance of the capacitor 300.

It should be noted that "electrically extracting" in the present disclosure may refer to electrically connecting through a conductive structure to achieve signal conduction. Electrically extracting the intermediary layer means extracting the signal from the intermediary layer through a conductive structure, or transmitting the signal to the intermediary layer.

Specifically, the interposer 100 includes an interposer body layer 101 and a dielectric layer 102, wherein the dielectric layer 102 is disposed close to the first surface 100a of the interposer 100, and the interposer body layer 101 is disposed close to the second surface 100b of the interposer 100. The interposer body layer 101 may be a semiconductor material, such as silicon, germanium, or silicon germanium, and the dielectric layer 102 may be an electrical insulating material, such as silicon oxide, germanium oxide, silicon oxynitride, or silicon germanium oxide. The dielectric layer 102 is disposed close to the first surface 100a of the interposer 100, and the side of the dielectric layer 102 away from the interposer body layer 101 is the first surface 100a of the interposer 100. The interposer body layer 101 is disposed close to the second surface 100b of the interposer 100, and the side of the interposer body layer 101 away from the dielectric layer 102 is the second surface 100b of the interposer 100.

In some embodiments, at least part of the dielectric layer 102 is distributed between the conductive via 200 and the interposer body layer 101. At least part of the dielectric layer 102 is distributed between the capacitor 300 and the interposer body layer 101. It should be noted that, based on the fact that the interposer body layer 101 is a semiconductor material, the dielectric layer 102 distributed between the interposer body layer 101 and the conductive via 200 can effectively avoid the problem of electrical conduction between the two, and ensure the stability of signal transmission inside the conductive via 200. Similarly, the dielectric layer 102 distributed between the interposer body layer 101 and the capacitor 300 can avoid electrical conduction between the two, and ensure the storage stability of the electrical signal in the capacitor 300.

In the semiconductor packaging structure of the present disclosure, the capacitor 300 includes a plurality of capacitors 300, and the plurality of capacitors 300 are arranged at intervals. The plurality of capacitors 300 can effectively increase the capacitance in the semiconductor packaging structure, thereby utilizing the capacitor 300 to suppress the noise in the conductive via 200 connection circuit, and ensure the packaging effect of the semiconductor packaging structure. The number of capacitors 300 can be equal to the number of conductive vias 200, and one capacitor 300 is provided corresponding to one conductive via 200. In other embodiments, the number of capacitors 300 may be more than the number of conductive vias 200, or less than the number of conductive vias 200, and the present disclosure does not limit this. In some embodiments, the plurality of capacitors 300 may be arranged at intervals in a direction perpendicular to the first surface 100a to the second surface 100b.

In capacitor 300 , the second electrode layer 303 is a tubular structure, the capacitor dielectric layer 302 is located on the inner wall of the tubular second electrode layer 303 and forms a tubular region, and the first electrode layer 301 is filled in the tubular region; a diffusion barrier layer is also provided between the first electrode layer 301 and the capacitor dielectric layer 302 .

It should be noted that the bottom of the second electrode layer 303 of the tubular structure is close to the second surface 100b and is electrically led out through the second conductive structure 500. The first electrode layer 301 is filled in the tubular area surrounded by the capacitor dielectric layer 302, and the first electrode layer 301 close to the tube mouth is close to the first surface 100a and is electrically led out through the first conductive structure 400. Based on the fact that the capacitor 300 is distributed throughout the intermediary layer 100 along the thickness direction of the intermediary layer 100 in the present disclosure, the depth of the capacitor 300 is large, and the second electrode layer 303 of the tubular structure can effectively improve the structural stability of the capacitor 300 and avoid the problem of collapse or tilt of the capacitor 300 during the manufacturing process. In addition, the second electrode layer 303 of the tubular structure can effectively increase the area of the second electrode layer 303, and correspondingly increase the corresponding area of the second electrode layer 303 and the first electrode layer 301, thereby helping to increase the capacitance.

The material of the first electrode layer 301 may be a metal material including copper, and the material of the capacitor dielectric layer 302 may be a high dielectric constant material. The high dielectric constant material may include but is not limited to silicon dioxide, silicon carbide, aluminum oxide, aluminum pentoxide, yttrium oxide, hafnium oxide, hafnium dioxide, zirconium dioxide, strontium carbonate, and zirconium oxide. The material of the second electrode layer 303 may be a metal material including tungsten.

The diffusion barrier layer between the first electrode layer 301 and the capacitor dielectric layer 302 can effectively prevent the metal material of the first electrode layer 301 from expanding, improve the adhesion of the first electrode layer 301 in the cylindrical region of the capacitor dielectric layer 302, and ensure the structural stability of the capacitor 300. Taking the material of the first electrode layer 301 as copper, the material of the diffusion barrier layer can be thallium. The first electrode layer 301 can be formed by an electroplating process, and a copper seed layer can be first deposited in the cylindrical region of the capacitor dielectric layer 302, and then a complete first electrode layer 301 is formed by electroplating.

As shown in FIG1 , one end of the first electrode layer 301 close to the first surface 100a, one end of the conductive through hole 200 close to the first surface 100a and the first surface 100a are flush. Compared with the related art, the electrode layer of the capacitor 300 has different depths in the semiconductor packaging structure, resulting in the need to set the depths of the conductive columns to be different, and the difficulty of setting the conductive columns is relatively large. The present disclosure sets the end of the first electrode layer 301 close to the first surface 100a to be flush with the first surface 100a, which can effectively reduce the difficulty of setting the first conductive structure 400. In addition, the end of the conductive through hole 200 close to the first surface 100a is also set to be flush with the first surface 100a, which is convenient for setting the electrical lead-out structure of the conductive through hole 200.

In some embodiments, there are multiple second conductive structures 500 connected to the same capacitor 300, and the multiple second conductive structures 500 are arranged at intervals. In this way, the electrical extraction efficiency of the second electrode layer 303 of the capacitor 300 can be improved. When part of the second conductive structure 500 is damaged, the remaining second conductive structures 500 can achieve the purpose of electrical extraction, so the multiple second conductive structures 500 can ensure the stability of the electrical extraction of the second electrode layer 303. As shown in FIG. 1, there are three second conductive structures 500 corresponding to one capacitor 300. The second conductive structures 500 can also be 2, 4 or more, and the present disclosure does not limit this. In some embodiments, the multiple second conductive structures 500 can be arranged at intervals along a direction perpendicular to the first surface 100a to the second surface 100b.

In other embodiments, the first conductive structure 400 may be multiple, and the multiple first conductive structures 400 may also be arranged at intervals along a direction perpendicular to the first surface 100a to the second surface 100b to improve the electrical extraction efficiency and stability of the first electrode layer 301.

The semiconductor packaging structure disclosed in the present invention further includes a third conductive structure 600. One end of the conductive via 200 close to the first surface 100a is connected to the third conductive structure 600, and the interposer 100 is electrically led out through the third conductive structure 600. The first conductive structure 400 and the third conductive structure 600 are of the same layer and material.

It should be noted that the third conductive structure 600 is used to electrically connect the conductive via 200 and the element located on the first surface 100a of the interposer 100. Since the end of the conductive via 200 close to the first surface 100a of the interposer 100 is flush with the first surface 100a, it can be prepared in the same layer as the first conductive structure 400 of the capacitor 300, and the same material is selected for both, so as to reduce the difficulty of preparing the semiconductor packaging structure.

1 , a multi-layer dielectric layer 908 and an etch stop layer 907 are disposed on one side of the first surface 100a of the interposer 100, and the etch stop layer 907 is located between adjacent dielectric layers 908. The first conductive structure 400 and the third conductive structure 600 can be formed by etching and deposition in the multi-layer dielectric layer 908. One layer of the etch stop layer 907 is located on the first surface 100a of the interposer 100, and the etch stop layer 907 can effectively protect the structure of the interposer 100 and avoid affecting the first surface 100a of the interposer 100 during the etching process.

Specifically, there is a gap between the second electrode layer 303 close to the second surface 100b and the second surface 100b, and the second conductive structure 500 is embedded in the intermediate layer 100 between the second surface 100b and the second electrode layer 303, one end of the second conductive structure 500 is connected to the second electrode layer 303, and the other end of the second conductive structure 500 is led to the second surface 100b.

It should be noted that the spacing between the second electrode layer 303 close to the second surface 100b and the second surface 100b can be 5-10μm, and the present disclosure does not limit the specific value of the spacing. In the process of the semiconductor packaging structure, this spacing can prevent the second electrode layer 303 from being directly exposed to the outside of the interposer 100, thereby reducing the stability of the capacitor 300. The second conductive structure 500 is embedded in the interposer 100 between the second surface 100b and the second electrode layer 303. The interposer 100 can be used to protect the second conductive structure 500 to avoid electrical interference between different second conductive structures 500, or between the second conductive structure 500 and the conductive through hole 200. The second conductive structure 500 can be a via with a conductive function.

The semiconductor package structure of the present disclosure further includes a fourth conductive structure 700, which is located on the second surface 100b, and the second conductive structure 500 is connected to the fourth conductive structure 700. The fourth conductive structure 700 may be a redistribution layer, and the fourth conductive structure 700 is used to electrically lead the signal of the second electrode layer 303 out of the interposer 100, and transmit it to the element located on the second surface 100b of the interposer 100.

When there are multiple capacitors 300, the fourth conductive structure 700 can be arranged in the following two ways:

As a feasible implementation, the second electrode layers 303 of the plurality of capacitors 300 are all connected to the same fourth conductive structure 700 through the second conductive structure 500. In this way, the electrical signals of the second electrode layers 303 of the plurality of capacitors 300 are all led out through the same fourth conductive structure 700, reducing the difficulty of setting the electrical lead-out of the capacitors 300. In addition, the fourth conductive structure 700 can control the writing of the electrical signals of the second electrode layers 303 of the plurality of capacitors 300, reducing the control difficulty of the semiconductor packaging structure. The two capacitors 300 shown in FIG. 1 are both electrically led out through the same fourth conductive structure 700.

In some embodiments, ends of some conductive vias 200 close to the second surface 100 b may also be electrically connected to the fourth conductive structure 700 , and electrically led out through the fourth conductive structure 700 .

As another achievable implementation, there are multiple fourth conductive structures 700, and the second electrode layers 303 of multiple capacitors 300 are connected to different fourth conductive structures 700 through corresponding second conductive structures 500. The second electrode layers 303 of different capacitors 300 are electrically led out through different fourth conductive structures 700, respectively, and multiple capacitors 300 can be controlled separately to meet various control requirements of the semiconductor packaging structure.

The semiconductor packaging structure disclosed in the present invention also includes a fifth conductive structure 800, which is located on the second surface 100b. One end of the conductive through hole 200 close to the second surface 100b is flush with the second surface 100b and connected to the fifth conductive structure 800, and the interposer 100 is electrically led out through the fifth conductive structure 800.

It should be noted that the fifth conductive structure 800 can be a bump or a micro bump (μbump) located on the second surface 100b of the interposer 100. The end of the conductive via 200 close to the second surface 100b is flush with the second surface 100b and is connected to the fifth conductive structure 800 to facilitate the extraction of its electrical signal while avoiding affecting the capacitor 300 or other conductive vias 200 adjacent to the conductive via 200.

1, in order to meet different connection requirements of the semiconductor package structure, a sixth conductive structure 905 may be further provided, the sixth conductive structure 905 is located on one side of the first surface 100a of the interposer 100, and the sixth conductive structure 905 may be electrically connected to the third conductive structure 600 through a via provided in the dielectric layer 908. The sixth conductive structure 905 may have one or more layers, and when the sixth conductive structure 905 has multiple layers, it may be distributed in different layers of the dielectric layer 908. The sixth conductive structure 905 may also be further electrically connected to other external components through vias.

FIG1 shows a second mask layer 906 , through which a groove is formed on a side of the sixth conductive structure 905 away from the intermediate layer 100 , and then a via hole can be formed by depositing a conductive material 904 in the groove to facilitate electrical connection between the sixth conductive structure 905 and other external components.

Figure 2 is a schematic diagram of the process of the method for preparing a semiconductor packaging structure provided in an embodiment of the present disclosure, Figure 3 is a schematic diagram of the process of forming a conductive via and a capacitor in the method for preparing a semiconductor packaging structure provided in an embodiment of the present disclosure, Figure 4 is a schematic diagram of the process of forming a capacitor in the method for preparing a semiconductor packaging structure provided in an embodiment of the present disclosure, Figure 5 is a schematic diagram of the structure of forming an intermediate layer and a conductive via provided in an embodiment of the present disclosure, Figure 6 is a schematic diagram of the structure of forming a capacitor groove provided in an embodiment of the present disclosure, Figure 7 is a schematic diagram of the structure of forming a second electrode layer and a capacitor dielectric layer provided in an embodiment of the present disclosure, Figure 8 is a schematic diagram of the structure of forming a conductive material provided in an embodiment of the present disclosure, Figure 9 is a schematic diagram of the structure of forming a conductive via and a capacitor provided in an embodiment of the present disclosure, Figure 10 is a schematic diagram of the structure of forming a first conductive structure and a third conductive structure provided in an embodiment of the present disclosure, Figure 11 is a schematic diagram of the structure of exposing the end of the conductive via close to the second surface provided in an embodiment of the present disclosure, and Figure 12 is a schematic diagram of the structure of forming a second conductive structure provided in an embodiment of the present disclosure.

In a second aspect, as shown in FIG. 2 , the present disclosure provides a method for preparing a semiconductor packaging structure, comprising:

S100: providing an interposer, wherein the interposer comprises a first surface and a second surface opposite to each other along a thickness direction.

Specifically, providing the intermediary layer 100 may include: forming an intermediary body layer 101; forming a dielectric layer 102, wherein the dielectric layer 102 is located on the intermediary body layer 101, the intermediary body layer 101 and the dielectric layer 102 together form the intermediary layer 100, the dielectric layer 102 is distributed close to the first surface 100a of the intermediary layer 100, and the intermediary body layer 101 is distributed close to the second surface 100b of the intermediary layer 100.

It should be noted that both the interposer body layer 101 and the dielectric layer 102 can be formed by deposition. The deposition thickness of the interposer body layer 101 and the dielectric layer 102 can be adjusted according to the depth of the conductive via 200 and the capacitor 300, which is not limited in the present disclosure.

S200: Conductive vias and capacitors are formed in the intermediary layer, the conductive vias and the capacitors are arranged at intervals, and the opposite ends of the conductive vias extend to the first surface and the second surface respectively, and the capacitor includes a first electrode layer, a capacitor dielectric layer, and a second electrode layer stacked in sequence; at least a portion of the first electrode layer is close to the first surface, and the intermediary layer is electrically led out through the first surface through the first conductive structure; at least a portion of the second electrode layer is close to the second surface, and the intermediary layer is electrically led out through the second surface through the second conductive structure.

Specifically, forming the conductive via 200 and the capacitor 300 includes:

S201: forming a conductive via in the interposer. The conductive via 200 can be formed by mask etching and deposition. A mask layer (not shown) is formed on the interposer 100, and the mask opening of the mask layer corresponds to the position of the conductive via 200 to be formed. A groove is formed in the interposer 100 by etching. A conductive material 904 is deposited in the groove to form the conductive via 200. The conductive material 904 can be a metal material including copper and tungsten.

S202: forming a capacitor trench in the intermediary layer, wherein the bottom of the capacitor trench and the bottom of the conductive through hole are both spaced apart from the bottom of the intermediary layer, and the distance between the bottom of the capacitor trench and the bottom of the intermediary layer is greater than the distance between the bottom of the conductive through hole and the bottom of the intermediary layer.

5 and 6 , the capacitor trench 900 may be formed by mask etching, that is, a first mask layer 903 is formed on the interposer 100 , the opening of the first mask layer 903 corresponds to the position of the capacitor trench 900 to be formed, and the capacitor trench 900 is formed in the interposer 100 by etching.

The depth of the capacitor trench 900 is less than the depth of the conductive through hole 200, thereby ensuring that the distance between the bottom of the capacitor trench 900 and the bottom of the interposer 100 is greater than the distance between the bottom of the conductive through hole 200 and the bottom of the interposer 100. In this way, in the subsequent manufacturing process of the fourth conductive structure 700 and the fifth conductive structure 800, the bottom of the capacitor 300 can be prevented from being exposed, thereby ensuring the structural stability of the capacitor 300 in the entire semiconductor packaging structure manufacturing process.

In some embodiments, the capacitor trench 900 can be formed simultaneously with the trench of the conductive via 200, so that the manufacturing process can be effectively simplified. The specific steps of forming the conductive via 200 and the capacitor 300 include:

A first trench and a second trench 901 are formed in the interposer 100, and the depth of the second trench 901 is less than the depth of the first trench. A mask layer having two mask openings is selected, and the two mask openings correspond to the positions of the formed conductive via 200 and the capacitor 300, respectively. The interposer 100 is etched along the mask layer to form the first trench and the second trench 901.

Afterwards, a conductive material 904 is formed in the first trench, and the first trench containing the conductive material 904 forms a conductive via 200 ; and a capacitor 300 is formed in the second trench 901 .

In some embodiments, after forming the groove of the conductive via 200 and before depositing the conductive material 904 in the conductive via 200, the method further includes: depositing an insulating material in the groove of the conductive via 200, and the insulating material may be the same as the material of the dielectric layer 102, so that at least a portion of the dielectric layer 102 is distributed between the conductive via 200 and the interposer body layer 101. In this way, the electrical isolation between the conductive via 200 and the interposer body layer 101 can be ensured, and the semiconductor performance of the interposer body layer 101 is prevented from affecting the signal transmission of the conductive via 200.

In some embodiments, after forming the capacitor trench 900 and before forming the capacitor 300 in the capacitor trench 900, the method further includes: depositing an insulating material in the capacitor trench 900, the insulating material may be the same as the material of the dielectric layer 102, so that at least a portion of the dielectric layer 102 is distributed between the capacitor 300 and the intermediary body layer 101. In this way, the electrical isolation between the capacitor 300 and the intermediary body layer 101 can be ensured, and the semiconductor performance of the intermediary body layer 101 is prevented from affecting the signal storage of the capacitor 300.

Among them, the capacitor groove 900 and the conductive through hole 200 can have multiple grooves, so that the capacitor 300 and the conductive through hole 200 finally prepared can have multiple. Multiple capacitors 300 and multiple conductive through holes 200 are arranged at intervals in the interposer 100, and the direction of the interval arrangement can be perpendicular to the direction from the first surface 100a to the second surface 100b. In this way, the signal transmission function of the semiconductor packaging structure can be improved, and the noise in the circuit of the conductive through hole 200 in the semiconductor packaging structure can be suppressed, thereby optimizing the packaging effect.

S203: forming a capacitor in the capacitor trench. Specifically, forming a capacitor 300 in the capacitor trench includes:

S2031: forming a second electrode layer, wherein the second electrode layer is located in the capacitor trench, and a first trench is formed in the second electrode layer.

S2032: forming a capacitor dielectric layer, wherein the capacitor dielectric layer is located in the first trench, and a second trench is formed in the capacitor dielectric layer.

7 , the second electrode layer 303 and the capacitor dielectric layer 302 can be formed by deposition and have a certain thickness, but do not fill the capacitor trench 900. The materials of both have been described in the above embodiments and will not be repeated here.

S2033: forming a first electrode layer, the first electrode layer is located in the second groove, and the first electrode layer, the capacitor dielectric layer and the second electrode layer together form a capacitor. Referring to FIG8 , the first electrode layer 301 can be formed by deposition to fill the second groove 901 formed by the capacitor dielectric layer 302 .

Specifically, after forming the capacitor, the following steps are also included:

S204: Planarize the top of the conductive via, the top of the capacitor and the top of the intermediary layer to make the top surface of the conductive via, the top surface of the capacitor and the top surface of the intermediary layer flush, and the top surface of the intermediary layer forms the first surface. Referring to FIG. 9 , the planarization process can be completed by a CMP (Chemical Mechanical Polishing) process, and the capacitor 300 and the intermediary layer 100 that are higher than the top surface of the conductive via 200 are processed along the top of the conductive via 200, so that the top surface of the conductive via 200, the top surface of the capacitor 300 and the top surface of the intermediary layer 100 are flush. In this way, the loss of the conductive via 200 and the capacitor 300 in the process can also be reduced.

S205: forming a first conductive structure and a third conductive structure, wherein the first conductive structure is connected to the first electrode layer, and the third conductive structure is connected to the top of the conductive through hole, and the first conductive structure and the third conductive structure are in the same layer and material.

It should be noted that, since the top surface of the conductive through hole 200 is flush with the top surface of the capacitor 300, a first conductive structure 400 can be formed in the same process to electrically lead out the first conductive layer of the capacitor 300 close to the first surface 100a, and a third conductive structure 600 can be formed to electrically lead out the end of the conductive through hole 200 close to the first surface 100a, thereby simplifying the process of the semiconductor packaging structure.

As shown in FIG. 10 , after forming the first conductive structure 400 and the third conductive structure 600, a multi-layer dielectric layer 908 may be formed, and a blocking etching layer is formed between two adjacent dielectric layers 908, wherein one blocking etching layer is located on the first surface 100a (i.e., the top surface) of the interposer 100. One or more layers of the sixth conductive structure 905 are formed in the multi-layer dielectric layer 908 by etching and deposition, and the signals of the first conductive structure 400 and the third conductive structure 600 are transmitted to the components outside the semiconductor packaging structure through the sixth conductive structure 905. The above process may be a back-end BEOL (Back End of Line) process after forming the conductive via 200 and the capacitor 300.

Specifically, after forming the first conductive structure 400 and the third conductive structure 600, the method further includes:

S206: Process the bottom of the interposer to expose the bottom of the conductive via; the bottom surface of the processed interposer forms the second surface. Referring to FIG. 11 , this process is the backside via reveal process BVR (Backside Via Reveal), which can be completed by a CMP process. Since the depth of capacitor 300 is less than the depth of conductive via 200, the distance between capacitor 300 and the bottom surface of interposer 100 is greater than the distance between conductive via 200 and the bottom surface of interposer 100, this step can only expose the bottom of conductive via 200, but not the bottom of capacitor 300.

S207: forming a fourth trench, the fourth trench being located in the intermediary layer at the bottom of the capacitor and exposing the second electrode layer of the capacitor. Referring to FIG12 , the fourth trench may be formed by etching.

S208: Form a second conductive structure, which is located in the fourth groove and connected to the exposed second electrode layer. There may be multiple fourth grooves, and the multiple fourth grooves are arranged at intervals, and each fourth groove is provided with a second conductive structure 500. Multiple fourth grooves may correspond to a capacitor 300 and be connected to its second electrode layer 303, so as to improve the electrical extraction efficiency and stability of the capacitor 300. The interposer 100 at the bottom of the capacitor 300 can protect the second conductive layer and avoid electrical interference with the adjacent conductive through-hole 200. In some embodiments, the direction in which the multiple fourth grooves are arranged at intervals may be perpendicular to the direction from the first surface 100a to the second surface 100b.

S209: forming a fourth conductive structure, where the fourth conductive structure is located at the bottom of the interposer and is connected to the second conductive structure.

S210: forming a fifth conductive structure, the fifth conductive structure is located at the bottom of the interposer and connected to the bottom exposed by the conductive through hole. As shown in FIG. 1 and FIG. 12, the fourth conductive structure 700 and the fifth conductive structure 800 can be prepared by deposition, the fourth conductive structure 700 can be a redistribution layer, and the fifth conductive structure 800 can be a bump.

In a third aspect, the present disclosure provides a semiconductor device comprising a first element, a second element and the above-mentioned semiconductor package structure, wherein the first element and the second element are respectively located on opposite sides of an interposer 100 of the semiconductor package structure along a thickness direction and are interconnected through the semiconductor package structure.

The first element and the second element in the present disclosure may be a chip, a circuit or a storage structure, which may include but is not limited to a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM) or a magnetoresistive random access memory (MRAM). The non-storage device may be a logic device (such as a microprocessor, a digital signal processor or a microcontroller) or a device similar thereto.

In the description of the embodiments of the present disclosure, it should be understood that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances. The orientation or position relationship indicated by the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise precisely and specifically specified.

The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims (15)

1. A semiconductor packaging structure, characterized in that it includes an interposer, a conductive via and a capacitor; The intermediary layer comprises a first surface and a second surface opposite to each other in a thickness direction, and the conductive via and the capacitor are spaced apart and arranged in the intermediary layer; The opposite ends of the conductive through hole extend to the first surface and the second surface respectively; the capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer stacked in sequence; at least a portion of the first electrode layer is close to the first surface, and the intermediate layer is electrically led out through the first surface through a first conductive structure; at least a portion of the second electrode layer is close to the second surface, and the intermediate layer is electrically led out through the second surface through a second conductive structure. 2 . The semiconductor package structure according to claim 1 , wherein the capacitor comprises a plurality of capacitors, and the plurality of capacitors are arranged at intervals in the interposer. 3 . The semiconductor package structure according to claim 1 , wherein an end of the first electrode layer close to the first surface, an end of the conductive via close to the first surface, and the first surface are flush. 4. The semiconductor package structure according to any one of claims 1 to 3, further comprising a third conductive structure, wherein one end of the conductive through hole close to the first surface is connected to the third conductive structure, and the interposer is electrically led out through the third conductive structure; The first conductive structure and the third conductive structure are in the same layer and made of the same material. 5. The semiconductor packaging structure according to any one of claims 1-3 is characterized in that there is a distance between the second electrode layer close to the second surface and the second surface, the second conductive structure is embedded in the intermediate layer between the second surface and the second electrode layer, one end of the second conductive structure is connected to the second electrode layer, and the other end of the second conductive structure is led to the second surface. 6. The semiconductor package structure according to any one of claims 1 to 3, further comprising a fourth conductive structure, wherein the fourth conductive structure is located on the second surface, and the second conductive structure is connected to the fourth conductive structure; When there are multiple capacitors, the second electrode layers of the multiple capacitors are connected to the same fourth conductive structure through the second conductive structure; or, when there are multiple fourth conductive structures, the second electrode layers of the multiple capacitors are connected to different fourth conductive structures through the corresponding second conductive structures. 7. The semiconductor packaging structure according to any one of claims 1-3 is characterized in that it also includes a fifth conductive structure, wherein the fifth conductive structure is located on the second surface, and one end of the conductive through hole close to the second surface is flush with the second surface and connected to the fifth conductive structure, and the intermediate layer is electrically led out through the fifth conductive structure. 8. The semiconductor packaging structure according to any one of claims 1 to 3, characterized in that the interposer comprises an interposer body layer and a dielectric layer, the dielectric layer is distributed close to the first surface of the interposer, and the interposer body layer is distributed close to the second surface of the interposer; Furthermore, at least a portion of the dielectric layer is distributed between the conductive via and the interposer body layer; and/or at least a portion of the dielectric layer is distributed between the capacitor and the interposer body layer. 9. A method for preparing a semiconductor packaging structure, comprising: Providing an interposer, the interposer comprising a first surface and a second surface opposite to each other in a thickness direction; Conductive vias and capacitors are formed in the intermediate layer, the conductive vias and the capacitors are arranged at intervals, and the opposite ends of the conductive vias extend to the first surface and the second surface respectively, and the capacitor includes a first electrode layer, a capacitor dielectric layer, and a second electrode layer stacked in sequence; at least a portion of the first electrode layer is close to the first surface, and the intermediate layer is electrically led out through the first surface through a first conductive structure; at least a portion of the second electrode layer is close to the second surface, and the intermediate layer is electrically led out through the second surface through a second conductive structure. 10. The method for preparing a semiconductor package structure according to claim 9, wherein forming the conductive via and the capacitor comprises: forming the conductive via in the interposer; A capacitor groove is formed in the intermediary layer, wherein the bottom of the capacitor groove and the bottom of the conductive through hole are both spaced apart from the bottom of the intermediary layer, and the distance between the bottom of the capacitor groove and the bottom of the intermediary layer is greater than the distance between the bottom of the conductive through hole and the bottom of the intermediary layer; The capacitor is formed in the capacitor trench. 11. The method for preparing a semiconductor package structure according to claim 10, wherein forming the capacitor in the capacitor trench comprises: forming a second electrode layer, wherein the second electrode layer is located in the capacitor groove, and a first groove is formed in the second electrode layer; forming a capacitor dielectric layer, wherein the capacitor dielectric layer is located in the first groove, and a second groove is formed in the capacitor dielectric layer; A first electrode layer is formed, wherein the first electrode layer is located in the second groove, and the first electrode layer, the capacitor dielectric layer and the second electrode layer together form the capacitor. 12. The method for preparing a semiconductor package structure according to claim 11, characterized in that after forming the capacitor, the method further comprises: Planarizing the top of the conductive via, the top of the capacitor, and the top of the interposer so that the top surface of the conductive via, the top surface of the capacitor, and the top surface of the interposer are flush, and the top surface of the interposer forms the first surface; A first conductive structure and a third conductive structure are formed, wherein the first conductive structure is connected to the first electrode layer, the third conductive structure is connected to the top of the conductive through hole, and the first conductive structure and the third conductive structure are in the same layer and material. 13. The method for preparing a semiconductor package structure according to claim 12, characterized in that after forming the first conductive structure and the third conductive structure, the method further comprises: Processing the bottom of the interposer to expose the bottom of the conductive via; the processed bottom surface of the interposer forms the second surface; forming a fourth trench, wherein the fourth trench is located in the interposer layer at the bottom of the capacitor and exposes the second electrode layer of the capacitor; forming a second conductive structure, wherein the second conductive structure is located in the fourth trench and connected to the exposed second electrode layer; forming a fourth conductive structure, wherein the fourth conductive structure is located at the bottom of the interposer and connected to the second conductive structure; A fifth conductive structure is formed, where the fifth conductive structure is located at the bottom of the interposer and is connected to the exposed bottom of the conductive via. 14. The method for preparing a semiconductor packaging structure according to claim 13, wherein there are a plurality of capacitors, and the plurality of capacitors are spaced apart and arranged in the interposer; The second electrode layers of multiple capacitors are connected to the same fourth conductive structure through the second conductive structure; or, there are multiple fourth conductive structures, and the second electrode layers of multiple capacitors are connected to different fourth conductive structures through corresponding second conductive structures. 15. The method for preparing a semiconductor package structure according to any one of claims 9 to 14, wherein providing the interposer comprises: Forming an intermediary body layer; forming a dielectric layer, the dielectric layer being located on the intermediary body layer, the intermediary body layer and the dielectric layer jointly forming the intermediary layer, the dielectric layer being distributed close to the first surface of the intermediary layer, and the intermediary body layer being distributed close to the second surface of the intermediary layer; Furthermore, at least a portion of the dielectric layer is distributed between the conductive via and the interposer body layer; and/or at least a portion of the dielectric layer is distributed between the capacitor and the interposer body layer.