CN118034643B - Carry-free multiplication and calculation array based on SRAM - Google Patents

Abstract

The present invention provides a carry-free multiplication storage and calculation array based on SRAM, including m×m storage and calculation units based on SRAM structure and N×m XOR trees; the single-bit streams generated by the multipliers input by the storage and calculation units in the same row are the same, each row of storage and calculation units simultaneously inputs N single-bit streams generated by the multipliers, and each column of storage and calculation units outputs N×m calculation result values in one calculation cycle, and the N×m calculation result values are used as input data of N m-input XOR trees, and N single-bit calculation results are finally obtained through the calculation of the XOR trees, and the carry-free multiplication storage and calculation array finally obtains N×m single-bit data calculation results. The present invention greatly improves the efficiency of carry-free multiplication calculation by combining in-memory calculation technology; and uses NAND gates instead of AND gates to complete the AND operation required for carry-free multiplication, further reducing the number of transistors required, and reducing the power consumption and resource usage required for calculation.

Description

A carry-less multiplication storage array based on SRAM

Technical Field

The present invention belongs to the field of storage-computing integration and brain-like computing, and specifically relates to a carry-free multiplication storage-computing array based on SRAM (static random access memory).

Background Art

Today's society has higher and higher requirements for data, computing power, and chip performance, and it is urgent to improve computing power and data efficiency. The von Neumann system running on traditional computers includes two parts: storage units and computing units, that is, storage and computing separation architecture. Therefore, when traditional computers implement operations, they need to first store data in the main memory, and then take out instructions from the main memory in order to execute them in order. Data needs to be frequently migrated between the processor and the memory, and the energy consumed by reading and writing data in the memory once is hundreds of times more than the energy consumed by calculating data once. The high latency and high energy consumption caused by the traditional von Neumann architecture have become problems that need to be solved urgently, and the short board memory has become the main bottleneck restricting the improvement of data processing speed. Storage and computing integration is to embed computing power in the memory, and perform two-dimensional and three-dimensional matrix multiplication/addition operations with a new computing architecture, that is, to use the memory to calculate the data, thereby avoiding the "storage wall" and "power consumption wall" generated by data transfer, and improving data parallelism and efficiency. The existing technology for calculating carry-less multiplication mainly accelerates the carry-less multiplication operation by adding additional instructions to the processor or using FPGA to implement a customized multiplier. Adding additional instructions to the processor does not improve the efficiency of carry-less multiplication calculations much. For example, in the BIKE (bit flip key encapsulation technology) algorithm that uses carry-less multiplication, the BIKE team has made some optimizations for x86 machines, but the speed of completing carry-less multiplication is heavily dependent on the use of carry-less multiplication instructions (such as pclmulqdq), and it still takes tens of thousands of cycles to complete a single carry-less multiplication calculation. Although using FPGA to implement a custom multiplier reduces the number of calculation cycles, it also consumes a lot of resources.

Summary of the invention

The present invention provides a carry-less multiplication storage and calculation array based on SRAM, comprising m columns of storage and calculation unit groups constructed based on SRAM and m columns of XOR tree groups; the storage and calculation unit group is composed of m storage and calculation units, and the XOR tree group is composed of N XOR trees; m is an integer greater than or equal to 2, N=1, 2, 4, 8, ... 2 ^q , q is a natural number;

Each of the storage and calculation units is composed of an SRAM and N two-input NAND gates. The SRAM outputs one bit of information of the stored multiplicand. The output of the SRAM is used as the input of one of the input ends of the N two-input NAND gates. The other input ends of the N two-input NAND gates are respectively input with N single-bit streams generated by the multiplier. The N two-input NAND gates respectively output the result of the NAND of the two inputs, that is, output N single-bit binary numbers.

The N single-bit binary numbers output by each storage unit of the j-th column storage unit group are respectively input into each XOR tree of the j-th column XOR tree group, j=1, 2, ..., m, each XOR tree receives a total of m single-bit binary numbers, and outputs a single-bit binary number result of the XOR of the m single-bit binary numbers;

Each column of storage and computing units outputs N×m single-bit binary numbers in one calculation cycle. The N×m single-bit binary numbers are used as input data of N m-input XOR trees. N single-bit calculation results are finally obtained through the calculation of the XOR tree. The m columns of the storage and computing unit group obtain a total of N×m single-bit calculation results. In one calculation cycle, the carry-less multiplication storage and computing array finally obtains N×m single-bit data calculation results.

Furthermore, the multiplicand is stored in the SRAM of the storage and calculation array in the form of single-bit information, each SRAM outputs different one-bit information of the same multiplicand, a two-input NAND gate calculates the NAND result of a single bit of the single-bit stream generated by the multiplier and the one-bit information of the multiplicand, and completes the product operation between single bits in the carry-less multiplication; the XOR tree further performs an XOR operation on the product output by the two-input NAND gate, completes the carry-less operation in the carry-less multiplication, and finally outputs a partial product result.

Furthermore, the N single-bit streams generated by the multipliers input into the storage and computing units in the same row are the same, and each row of storage and computing units simultaneously inputs the N single-bit streams generated by the multipliers, and the N single-bit streams generated by the multipliers are respectively input into the N two-input NAND gates of each storage and computing unit in the row.

Furthermore, the binary representation of the multiplier is a _n-1 a _n-2 a _n-3 …a ₂ a ₁ a ₀ , and the kth row of the carry-less multiplication storage array cyclically shifts the binary representation of the multiplier left by m*(k-1) bits to obtain a new binary number, k=1,2,3,…,m; the high bits of the new binary number are padded with zeros to make it a binary number x _g*N-1 x _g*N-2 x _g*N-3 …x ₂ x ₁ x ₀ of length g*N, wherein g=ceil(n/N) and the ceil() function is a rounding function; the i-th two-input NAND gate of the k-th row storage unit of the carry-less multiplication storage array, i=1,2,3,…,N, has an input single-bit stream of x _i-1 ,xi _-1+N , _xi-1+2*N , _xi-1+3*N ,…,x _i-1+(g-1)*N .

Furthermore, all the SRAMs in each column respectively output different one-bit information of the same multiplicand stored therein, and each SRAM outputs the one-bit information of the stored multiplicand to the N two-input NAND gates in the storage unit where it is located, and the other input ends of the N two-input NAND gates respectively input N single-bit streams generated by the multiplier, and each column of storage units outputs N×m single-bit binary numbers to N m-input XOR trees in one calculation cycle, and the N XOR trees output N single-bit calculation results. After one calculation cycle, the SRAM-based carry-free multiplication storage array outputs N×m single-bit calculation results, and the N×m single-bit calculation results are represented by a matrix O of size N×m; in a column of storage units, the result of the calculation of the i-th two-input NAND gate of each storage unit will be output to the same XOR tree, i=1,2,…,N, and the column of storage units is the j-th column, j=1,2,…,m, then the single-bit calculation result output by the XOR tree at this time is the element O in the matrix O. The value corresponding to _ij .

The present invention also provides a carry-free multiplication operation method using the SRAM-based storage and calculation array to calculate the carry-free multiplication of A×B, the multiplicand B is stored in the SRAM of the storage and calculation array in the form of single-bit information, the SRAM outputs one-bit information of the multiplicand B, in each row of the storage and calculation array, N single-bit streams generated by the multiplier A and the output of the SRAM are input into the two-input NAND gate of the storage and calculation unit where the SRAM is located; in a calculation cycle, the result output by the two-input NAND gate is the product of the single-bit information of B stored in the SRAM and the single-bit data in the single-bit stream generated by the multiplier A input in the cycle, the results output by the two-input NAND gates of all the storage and calculation units are input into the corresponding XOR tree to perform mutual XOR operation, and the result finally output by the XOR tree is the partial product result of the carry-free multiplication calculation of A×B.

The advantages of the present invention are as follows:

The present invention greatly improves the efficiency of carry-less multiplication calculation by combining in-memory computing technology; uses NAND gates instead of AND gates to complete the AND operation required for carry-less multiplication, further reducing the number of transistors required, and reducing the power consumption and resource usage required for calculation; at the same time, a single memory computing unit is used to use N two-input NAND gates for parallel calculation, which can greatly reduce the number of cycles required for calculation; the configurable parameter array size m and the number of parallel calculations N also make its application scenarios more extensive.

(1) For carry-less multiplication operations, a carry-less multiplication storage and calculation array based on SRAM is proposed. The storage and calculation array uses NAND gates instead of AND gates to complete the AND operation required for carry-less multiplication. The gate circuits used use a smaller number of transistors, which effectively reduces the scale of the circuit, reduces the power consumption and area of the circuit, and improves the energy efficiency and computing density.

(2) By making a single storage and computing unit use N two-input NAND gates for parallel computing, the computational complexity of a single computing cycle is significantly improved, which can effectively reduce the complexity of the operation and the number of computing cycles.

(3) The parameter m in the size of the SRAM-based carry-less multiplication storage array and the parameter N of the parallel computing amount are configurable variables, and both can select corresponding values according to specific needs. Therefore, the array can be configured according to the calculation requirements of carry-less multiplication in different application scenarios, with higher flexibility and wider application range.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a schematic diagram of the structure of the XOR tree of 128 inputs;

Fig. 2 is a structural diagram of the jth column of the carry-less multiplication storage array;

Figure 3 is a diagram of the overall architecture of the carry-less multiplication storage and calculation array;

Figure 4 Schematic diagram of the architecture of polynomial multiplication calculation in the BIKE algorithm.

DETAILED DESCRIPTION

The present invention is further described and illustrated below in conjunction with specific embodiments. The embodiments are merely exemplary of the present disclosure and do not define the scope of limitation. The technical features of each embodiment of the present invention may be combined accordingly without conflicting with each other.

Among the methods for implementing in-memory computing, SRAM has a simple and clear storage logic and is easier to integrate with current digital processor technology. At the same time, SRAM is close to the CPU and has a greater read and write performance advantage. Carry-free multiplication, that is, multiplication without carry operation, is mathematically defined as multiplication of Galois Field GF(2 ⁿ ), and the polynomial is defined as where a _i ,b _i ∈{0,1}, c _i = Σ _{j + k = i} a _j b _k mod 2∈{0,1}. In the design of in-memory computing, each storage and computing unit not only stores data but also performs operations on data. The storage and computing array mainly completes the partial product operation of carry-less multiplication. The fully expanded storage and computing array can complete the partial product calculation of carry-less multiplication at one time and output the corresponding calculation results. The entire device array has the characteristics of fast speed, high parallelism and good energy efficiency. It is suitable for applications that require a large number of carry-less multiplication operations, such as post-quantum cryptography BIKE (bit flip key encapsulation technology), HQC (Hamming quasi-cyclic key encapsulation technology) and other algorithms.

The present invention provides a carry-less multiplication storage array based on SRAM, which is suitable for carry-less multiplication operations on Galois Field GF(2 ⁿ ). The carry-less multiplication storage array is composed of storage units and XOR trees constructed based on SRAM. The size of the carry-less multiplication storage array is m×m (m=16, 32, 64, 128, ...), that is, it is composed of m×m storage units and XOR trees. In particular, in order to store all multipliers in the storage units, m×m≥n is required. Taking the calculation of carry-less multiplication C=A×B as an example, where a _i ,b _i ∈{0,1}, c _i =Σ _{j+k = i} a _j b _k mod 2∈{0,1}. The input of the carry-less multiplication storage array is a single bit stream generated by the multiplier A, and the data stored in the storage unit is the multiplicand B. The specific array architecture design is introduced as follows:

A storage unit consists of an SRAM and N (N = 1, 2, 4, 8, ...) two-input NAND gates. An XOR tree is a tree structure built by two-input XOR gates. Its input is m single-bit binary numbers, and its output is the single-bit binary result of the XOR of these m single-bit binary numbers. An m-input XOR tree consists of multiple two-input XOR gates. Taking m = 128 as an example, its tree structure is shown in Figure 1. To calculate the result of mutual XOR of m single-bit binary numbers, ceil(log ₂ (m)) levels of XOR trees are required, and the ceil() function is a rounding-up function; the m single-bit binary numbers are input into the two-input XOR gates of the first level of the XOR tree, and two-by-two XOR calculations are performed, and the inputs of each level of two-input XOR gates starting from the second level depend on the outputs of the two-input XOR gates of the previous level, that is, the two inputs of a two-input XOR gate of the next level are the output results of the two two-input XOR gates of the previous level, and so on. The output result of the two-input XOR gate of the last level is the output result of the entire XOR tree, that is, the result of mutual XOR of the m single-bit binary number inputs.

The data output by the SRAM is input to one of the input ends of the N two-input NAND gates, and the data input to the other input end of the NAND gate is a single bit stream generated by the multiplier A. In particular, the single bit stream generated by the input multiplier A is the same for the storage units in the same row of the carry-free multiplication storage array, and each row of storage units simultaneously inputs a single bit stream generated by N multipliers A. The size of the carry-free multiplication storage array is m×m, that is, each column of storage units outputs N×m calculation result values in one calculation cycle. These N×m calculation result values will be used as input data for N m-input XOR trees, and N single-bit data calculation results will eventually be obtained through the calculation of the XOR tree. The jth (j＝1,2,…,m) column structure (i.e., single column structure) of the carry-free multiplication storage array is shown in Figure 2. In particular, in one calculation cycle, in a column of storage units, the result of the calculation of the i-th (i＝1,2,…,N) two-input NAND gate of each storage unit will be output to the same XOR tree. A carry-less multiplication storage array of size m×m has a total of m columns of storage units, so the carry-less multiplication storage array has a total of N×m m-input XOR trees. In one calculation cycle, the carry-less multiplication storage array finally obtains N×m single-bit data calculation results. The overall architecture of the carry-less multiplication storage array is shown in Figure 3, and its final output result can be represented by a matrix O of size N×m, wherein, in a column of storage units, since the result of the calculation of the i-th (i＝1,2,…,N) two-input NAND gate of each storage unit will be output to the same XOR tree, if the column of storage units is the j-th (j＝1,2,…,m) column, the single-bit data result output by the XOR tree at this time is the value corresponding to the element O _ij in the matrix O.

BIKE is a code-based key encapsulation mechanism based on QC-MDPC (quasi-cyclic medium-density parity check) codes. The quasi-cyclic code used in the BIKE algorithm allows all matrix operations to be considered as polynomial operations. According to the performance analysis results, polynomial multiplication is one of the most expensive computational operations in the BIKE algorithm. The polynomial multiplication in the BIKE algorithm is calculated on the cyclic polynomial ring F ₂ [x]/(x ^r -1), where F ₂ represents a binary finite field. Therefore, assuming A = a ₀ + a ₁ x + … + a _r-1 x ^r-1 , B = b ₀ + b ₁ x + … + b _r-1 x ^r-1 , where a _i , b _i ∈ {0,1}, the polynomial multiplication in the BIKE algorithm is C = (A×B)% (x ^r –1), where the A×B part is the carry-less multiplication operation, and C is the reduced modulus calculation result of the carry-less multiplication of A×B and the irreducible polynomial (x ^r –1). The reduction operation is to move the part of the terms with a degree greater than or equal to r in the result of the A×B carry-less multiplication operation to the part with a lower degree, and perform an XOR operation on the two parts. The output calculation result is the result value of the polynomial multiplication C=(A×B)%(x ^r –1) in the BIKE algorithm.

The above scheme is further explained by taking the carry-less multiplication operation in the BIKE algorithm as an example. Since the BIKE algorithm can be instantiated with three different parameter sets to meet the different security levels recommended by NIST (National Institute of Standards and Technology), this embodiment will calculate the carry-less multiplication used by the BIKE algorithm when the security level is 1, that is, the parameter r=12323. Therefore, it is assumed that A=a ₀ +a ₁ x+…+a ₁₂₃₂₂ x ¹²³²² , B=b ₀ +b ₁ x+…+b ₁₂₃₂₂ x ¹²³²² , where a _i ,b _i ∈{0,1}. The specific values of A, B and C are represented in the form of binary bits, that is, a ₁₂₃₂₂ a ₁₂₃₂₁ ... a ₁ a ₀ represents the multiplier A, b ₁₂₃₂₂ b ₁₂₃₂₁ ... b ₁ b ₀ represents the multiplicand B, and c ₁₂₃₂₂ c ₁₂₃₂₁ ... c ₁ c ₀ represents the multiplication result C. In this embodiment, the parameter m of the storage array size selected is 128, and the parameter N of the number of parallel calculations is 4. The SRAM-based carry-free multiplication storage array only needs g = ceil (r / N) = ceil (12323 / 4) = 3081 calculation cycles to complete a polynomial multiplication calculation. The ceil () function here is a rounding function, which returns an integer greater than or equal to the function parameter and closest to it. The overall architecture of calculating the polynomial multiplication C=(A×B)%(x ^r –1) in the BIKE algorithm using the SRAM-based carry-less multiplication storage array of the present invention is shown in FIG4 , and the calculation operation method is described as follows.

In this embodiment, a storage and calculation array is formed according to the value of the multiplicand B. The specific form of storing B in the storage and calculation array is: every 97 bits of B (if less than 97 bits, the high bits are filled with 0) are stored in the same row of the storage and calculation array, and the high bits are filled with 0, and the storage operation of a total of 128 rows is completed in sequence. For the kth (k＝1,2,3,…,126,127) row of storage and computing units of the storage and computing array, the 128 data stored are 0, 0, …, 0, 0, b _97*(k-1)+96 , b _97*(k-1)+95 , …, b _97*(k-1)+2 , b _97*(k-1)+1 , b _97*(k-1) ; for the last row (k＝128) of storage and computing units of the storage and computing array, the 128 data stored are 0, 0, …, 0, 0, b ₁₂₃₂₂ , …, b _97*127+1 , b _97*127 . That is, the data stored in the first row of 128 storage units of the storage array are 0, 0, …, 0, 0, b ₉₆ , b ₉₅ , …, b ₂ , b ₁ , b ₀ , the data stored in the second row of 128 storage units are 0, 0, …, 0, 0, b ₁₉₄ , b ₁₉₃ , …, b ₉₉ , b ₉₈ , b ₉₇ , and so on. The data stored in the last row of 128 storage units are 0, 0, …, 0, 0, b ₁₂₃₂₂ , b ₁₂₃₂₁ , b ₁₂₃₂₀ , b ₁₂₃₁₉ .

In this embodiment, the input of the storage and calculation array is formed according to the value of the multiplier A. For the storage and calculation unit of the kth row (k = 1, 2, 3, ..., 126, 127, 128) of the storage and calculation array, the input data is formed as follows. The binary number a ₁₂₃₂₂ a ₁₂₃₂₁ ... a ₁ a ₀ represents the multiplier A, and the binary number is cyclically shifted left by 97*(k-1) bits to obtain a new binary number

A _i =a _{12323-97*(k-1)-1} a _{12323-97*(k-1)-2} …a ₂ a ₁ a ₀ a ₁₂₃₂₂ a ₁₂₃₂₁ …a _{12323-97*(k-1)+2} a _{12323-97*(k-1)+ 1} a _{12323-97*(k-1)} . For the convenience of description, the binary number x ₁₂₃₂₂ x ₁₂₃₂₁ …x ₁ x ₀ is used to represent the new binary number obtained by cyclically shifting the binary number of the multiplier A to the left, and the high bits of the binary number are padded with zeros to make it a binary number A _i =x _g*N-1 x _g*N-2 …x ₁ x ₀ with a length of g*N. The number of parallel calculations is N, so a row of storage and calculation units has N inputs, and the composition of these N inputs is: for the i-th (i=1,2,3,…,N) input, its input bit stream is x _i-1 , x _i-1+N , x _i-1+2*N , x _i-1+3*N ,…, x _i-1+(g-1)*N , which is composed of g=3081 bits in total. In this embodiment, the parameter of the number of parallel calculations is N=4, and a row of storage and calculation units has N=4 inputs, so the bit stream of the i-th (i=1,2,3,4) input of the row of storage and calculation units is composed of x _i-1 , x _i+3 , x _i+7 ,…, x _i+12311 , x _i+12315 , x _i+12319 , and is input to the corresponding input end of the storage and calculation array.

In this embodiment, each storage unit of the storage unit array performs operations on the input, and the calculation results of the storage unit will be input into the XOR tree for XOR operation. Finally, after a calculation cycle, the SRAM-based carry-less multiplication storage unit array of the present invention will output 4×128 single-bit data calculation results, which can be represented by a matrix O of size 4×128.

In this embodiment, the row vectors of the matrix O are represented by binary numbers. Considering that only the last 97 columns of the storage and calculation array in this embodiment store data, in order to reduce the amount of calculation and facilitate calculation, the values of the four row vectors are represented as 100-bit binary numbers O ₁ , O ₂ , O ₃ and O ₄ , respectively, where the lower 97 bits are the last 97 bits of the values of each row of the matrix O, and the remaining upper 3 bits are filled with zeros, and these four binary numbers are input into the shift XOR module. In the shift XOR module, O ₂ is shifted left by 1 bit, O ₃ is shifted left by 2 bits, O ₄ is shifted left by 3 bits, and the lower bits are filled with zeros. The newly obtained three binary numbers are XORed together with O ₁ , and finally a 100-bit binary number result P is output.

In this embodiment, P is input into the register module, and the length of the register module is 100+4*C _n bits, where C _n means that a write operation is performed on the memory every C _n calculation cycles. The register module mainly implements the "calculation + storage" function, which first performs a logical right shift of N=4 bits on the output result R _last of the register module in the previous calculation cycle, and performs an XOR operation on the high 100 bits of the shifted R _last and the output result P of this calculation cycle, and finally obtains a new register output result R _now . The low bits of R _now are the data that have been calculated but not written into the memory, and the high bits are the data that have not been calculated yet.

In this embodiment, the memory read/write length is 4*Cn bits, and the lower 4*Cn bits of data stored in the register module are written into the memory after every _Cn calculation cycles. This embodiment will be described by taking parameter _Cn =32 as an example, that is, the memory read/write length is 128 bits, and the size of the data R _last stored in the register module is 100+4* _Cn =228 bits. Since the calculation of the lowest bit result of the polynomial multiplication in the BIKE algorithm is also related to the calculation result of the last shift XOR module, it is necessary to re-read the lowest bit 128 bits of the previously calculated result from the memory, perform a separate XOR calculation, and then write it back. The 128 bits of data re-read from the memory will be XORed with the middle 128 bits of the data R _last stored in the register module (i.e., the [162:35] part of R _last [227:0], a total of 128 bits), and the output result will be written back to the corresponding position where the original lowest bit 128 bits of the calculation result are stored in the memory. Finally, the result stored in the memory is the result value of the polynomial multiplication C=A×B in the BIKE algorithm.

In this embodiment, the present invention reduces the number of calculation cycles of polynomial multiplication in the BIKE algorithm to 3081 cycles, which greatly reduces the amount of calculation and improves the calculation efficiency compared to the millions of cycles required for the RISCV hardware processor to complete the calculation. At the same time, the storage and calculation array of the present invention is small in scale, the circuit has low power consumption and small area, and has higher energy efficiency and calculation density.

The above-mentioned embodiments only express several implementation methods of the present invention, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. For ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims (7)

1. The carry-free multiplication memory array based on the SRAM is characterized by comprising m columns of memory cell groups based on the SRAM structure and m columns of exclusive OR tree groups; the storage unit group consists of m storage units, and the exclusive-or tree group consists of N exclusive-or trees; m is an integer greater than or equal to 2, n=1, 2,4,8, …,2, ^q, q is a natural number;

Each storage unit consists of an SRAM and N two-input NAND gates, and the SRAM outputs one bit of the stored multiplicand information; the output of the SRAM is respectively used as the input of one input end of N two-input NAND gates, and the other input end of the N two-input NAND gates is respectively used for inputting N single bit streams generated by a multiplier; n two-input NAND gates respectively output two-input phase NAND results, namely N single-bit binary numbers;

N single-bit binary numbers output by each storage unit of the jth column of storage unit group are respectively input into each exclusive-or tree of the jth column of exclusive-or tree group, j=1, 2, …, m, each exclusive-or tree receives m single-bit binary numbers in total, and a single-bit binary number result which is formed by mutually exclusive-or of the m single-bit binary numbers is output;

Each column of storage and calculation units outputs N multiplied by m single-bit binary numbers in a calculation period, the N multiplied by m single-bit binary numbers are used as input data of N input exclusive-OR trees, N single-bit calculation results are finally obtained through calculation of the exclusive-OR trees, and N multiplied by m single-bit calculation results are obtained through m columns of storage and calculation unit groups; and in one calculation period, the carryless multiplication and calculation array finally obtains N multiplied by m single-bit data calculation results.

2. The SRAM-based carryless multiplication memory array of claim 1 wherein the multiplicand is stored in the SRAM of said memory array in the form of single bit information, each SRAM outputting the same multiplicand with different bit information, a two-input nand gate calculating the nand result of the single bit stream generated by the multiplier and the one bit information of the multiplicand, performing the operation of the product between the single bits in the carryless multiplication; the exclusive-or tree is used for further exclusive-or operation of the product output by the two-input NAND gate to finish the operation of no-carry operation in no-carry multiplication and finally output partial product result.

3. The SRAM-based carryless multiplication memory array of claim 1, wherein calculating the result of the exclusive or of m single bit binary numbers requires ceil (log ₂ (m)) level exclusive or trees, the ceil () function being a round-up function; the m single-bit binary numbers are input into two-input exclusive-OR gates of a first stage of an exclusive-OR tree to perform two-by-two exclusive-OR calculation, the input of each stage of two-input exclusive-OR gate started by a second stage depends on the output of the two-input exclusive-OR gate of the previous stage, namely, the two inputs of one two-input exclusive-OR gate of the subsequent stage are the output results of the two-input exclusive-OR gates of the previous stage, and so on, and the output result of the two-input exclusive-OR gate of the last stage is the output result of the whole exclusive-OR tree, namely, the result of the mutual exclusive-OR of the m single-bit binary number inputs.

4. The SRAM-based carryless multiplication memory array of claim 1 wherein the N single bit streams generated by the multipliers input by the memory cells in the same row are identical, each row of memory cells simultaneously inputting N single bit streams generated by the multipliers, said N single bit streams generated by the multipliers being input to N two-input nand gates of each memory cell within the row, respectively.

5. The SRAM-based carryless multiplication array of claim 1, wherein said binary representation of the multiplier is a _n-1a_n-2a _n-3…a₂a₁a₀, and wherein the k-th row of said carryless multiplication array is shifted left by m x (k-1) bits cyclically for the binary representation of the multiplier to obtain a new binary number, k = 1,2,3, …, m; the new binary number is subjected to high-order zero padding to be changed into a binary number x _g*N-1x_g*N-2x _g*N-3…x₂x₁x₀ with the length of g x N, wherein g=ceil (N/N), and the ceil () function is an upward rounding function; the ith two-input NAND gate of the kth row of the carryless multiplication and calculation array, i=1, 2,3, …, N, has the input single bit stream of x _i-1,x _i-1+N,x_i-1+2*N,x_i-1+3*N,…,x_i-1+(g-1)*N.

6. The SRAM-based carryless multiplication array of claim 1, wherein all of said SRAMs of each column respectively output stored identical multiplicand different bit information, each SRAM outputs stored multiplicand bit information to N two-input nand gates in a memory cell where it is located, another input terminal of said N two-input nand gates respectively inputs N single bit streams generated by multipliers, each column memory cell outputs N x m single bit binary numbers to N m input xor trees in one calculation cycle, N said xor trees output N single bit calculation results, after one calculation cycle is finished, said SRAM-based carryless multiplication array outputs N x m single bit calculation results, said N x m single bit calculation results are represented by matrix O of size N x m; in a column of memory units, the calculated result of the ith two-input nand gate of each memory unit is output to the same exclusive-or tree, i=1, 2, …, N, the column of memory units is the jth column, j=1, 2, …, m, and then the single-bit calculated result output by the exclusive-or tree is the value corresponding to the element O _ij in the matrix O.

7. A method of carryless multiplication using the SRAM-based storage array of claim 2, wherein the carryless multiplication of a x B is calculated, the multiplicand B is stored in the SRAM of the storage array in the form of single bit information, the SRAM outputs one bit of the multiplicand B, and in each row of the storage array, N single bit streams generated by the multiplier a are input together with the output of the SRAM into the two-input nand gate of the storage unit in which the SRAM is located; in a calculation period, the output result of the two-input NAND gate is the product of the single bit information of B stored in the SRAM and the single bit data in the single bit stream generated by the multiplier A input in the period, the output result of the two-input NAND gate of all the storage units is input into the corresponding exclusive-OR tree for mutual exclusive-OR operation, and the final output result of the exclusive-OR tree is the partial product result of the A multiplied by B without carry.