CN118033228A - Microcurrent detection device and microcurrent detection method - Google Patents

Abstract

The application discloses a micro-current detection device and a micro-current detection method, and belongs to the technical field of electronics. The device comprises: the device comprises a current integration module, a correlated double sampling module, a differential amplification module and an analog-to-digital converter; the current integration module comprises a plurality of current input interfaces and a plurality of operational amplifiers sharing the same input end; each current input interface is used for receiving a micro-current signal generated during nanopore sequencing and transmitting the micro-current signal to a corresponding operational amplifier for processing, each operational amplifier is used for carrying out integral amplification on the received micro-current signal and converting the micro-current signal into a voltage signal, and the related double sampling module is used for carrying out double sampling on the voltage signal. The device of the application realizes the efficient reading of the nanopore sequencing current by arranging a plurality of current detection channels, sharing half operational amplifier, carrying out correlated double sampling, differential amplification and other technical means, meets the requirement of high-flux sequencing, and has better technical effect.

Description

Micro-current detection device and micro-current detection method

Technical Field

The present application belongs to the field of electronic technology, and in particular relates to a micro-current detection device and a micro-current detection method.

Background technique

DNA sequencing technology (also known as gene sequencing technology) is a technology used to detect the DNA sequence of species. Compared with traditional DNA sequencing technology, the fourth-generation DNA sequencing technology based on nanopores has natural advantages in time, cost and operational complexity. Its principle is to detect the weak characteristic current signal generated when DNA passes through the nanopore to determine its base sequence. Therefore, accurately measuring this characteristic current is one of the key technologies to achieve high-accuracy gene sequencing.

At present, the research on nanopore DNA sequencing current detection devices mainly focuses on two technical routes: single channel and array. However, the single channel architecture faces the challenge of high power consumption and area consumption, while the array architecture is limited by circuit noise and cannot achieve accurate detection of pA (picoampere) level current.

Therefore, how to design a DNA sequencing device with low power consumption, small area and high accuracy has become a problem that needs to be solved urgently.

Summary of the invention

The purpose of the present application is to provide a microcurrent detection device and a microcurrent detection method, which can meet the needs of miniaturization, low cost and high accuracy of nanopore sequencing current detection devices.

In a first aspect, an embodiment of the present application provides a micro-current detection device, the device comprising: a current integration module, a correlated double sampling module, a differential amplification module and an analog-to-digital converter;

The current integration module includes multiple current input interfaces and multiple operational amplifiers sharing the same input terminal, each current input interface corresponds to an operational amplifier and is connected to the non-shared input terminal of the operational amplifier; each current input interface is used to receive a microcurrent signal generated during nanopore sequencing and transmit it to the corresponding operational amplifier for processing, and each operational amplifier is used to integrate and amplify the received microcurrent signal and convert it into a voltage signal;

The correlated double sampling module includes a plurality of correlated double sampling circuits, each of which corresponds to an operational amplifier and is connected to the output end of the operational amplifier, and is used to sample a first voltage signal output by the operational amplifier at the initial stage of current integration, and to sample a second voltage signal output by the operational amplifier at the end stage of current integration;

The differential amplifier module is used to determine a fully differential voltage signal corresponding to the micro-current signal according to the first voltage signal and the second voltage signal;

The analog-to-digital converter is used to generate and output characteristic data of micro-current according to the fully differential voltage signal.

In a possible implementation of the first aspect, the microcurrent detection device also includes an addressing module and a channel selector, one end of the channel selector is connected to a plurality of correlated double sampling circuits, and the other end of the channel selector is connected to a differential amplifier module; the addressing module is used to control the channel selector to traverse and select each correlated double sampling circuit in the plurality of correlated double sampling circuits, and transmit the first voltage signal and the second voltage signal stored in the selected correlated double sampling circuit to the differential amplifier module for processing.

In a possible implementation of the first aspect, the differential amplification module includes a fully differential switched capacitor amplifier, which is used to, in a sampling state, sample a first voltage signal and a second voltage signal stored in a selected correlated double sampling circuit, and, in an amplification state, amplify the first voltage signal and the second voltage signal into a fully differential voltage signal.

In a possible implementation of the first aspect, the fully differential voltage signal corresponding to the micro-current signal is obtained using the following formula:

,

in, is the fully differential voltage signal, /> is the gain of the fully differential switched capacitor amplifier, /> is the first voltage signal,/> is the second voltage signal.

In a possible implementation manner of the first aspect, the analog-to-digital converter includes at least one virtual capacitor, which is used to adjust the size of a bridge capacitor in the analog-to-digital converter and is located in a low-order portion of the analog-to-digital converter.

In a possible implementation manner of the first aspect, the analog-to-digital converter is a successive approximation analog-to-digital converter with N redundant bits; wherein N≥1 and is a positive integer.

In a possible implementation manner of the first aspect, the operational amplifier is a capacitive feedback transconductance amplifier.

In a possible implementation manner of the first aspect, each correlated double sampling circuit includes at least one analog buffer, and the at least one analog buffer is used to buffer the first voltage signal and the second voltage signal.

In a second aspect, an embodiment of the present application provides a microcurrent detection method, the method comprising:

The current integration module is used to collect the microcurrent signals generated by multiple nanopore sequencing, integrate and amplify the microcurrent, and convert it into a voltage signal;

Using a correlated double sampling module to sample a first voltage signal output by the current integration module at an initial stage of current integration, and a second voltage signal output by the current integration module at an end stage of current integration;

Determine a fully differential voltage signal corresponding to the micro-current signal according to the first voltage signal and the second voltage signal using a differential amplifier module;

An analog-to-digital converter is used to generate characteristic data of micro-current based on the fully differential voltage signal and output it.

In a third aspect, an embodiment of the present application provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the computer device implements any one of the implementation methods of the first and second aspects described above.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a computer device, it implements any implementation method of the first aspect and the second aspect mentioned above.

In a fifth aspect, an embodiment of the present application provides a computer program product, which, when executed on a computer device, enables the computer device to execute any one of the implementation methods described in the first aspect above.

Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

The device of the present application, through multiple current input interfaces and corresponding operational amplifiers, and the parallel design of the correlated double sampling circuit, can process microcurrent signals from multiple nanopore sequencing channels in parallel, effectively improving the current detection efficiency and real-time performance, so that it can meet the needs of high-throughput nanopore sequencing. On this basis, the design of the shared half-side operational amplifier effectively reduces the overall area and power consumption of the system. In addition, the design of the correlated double sampling and differential amplifier circuit helps to reduce the impact of noise on the results, thereby ensuring the accuracy and reliability of the data. In general, this scheme realizes efficient readout of nanopore sequencing current by setting multiple current detection channels, sharing half-side operational amplifiers, performing correlated double sampling and differential amplification and other technical means, meets the needs of high-throughput sequencing, and has good technical effects.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of an application scenario of a current detection device provided by an embodiment of the present application;

FIG2 is a schematic diagram of the structure of a current detection device provided in an embodiment of the present application;

FIG3 is a circuit diagram of an operational amplifier provided in an embodiment of the present application;

FIG4 is a circuit diagram of a current detection unit provided in another embodiment of the present application;

FIG5 is a schematic diagram of the working timing of a current detection device provided by another embodiment of the present application;

FIG6 is a schematic diagram of the structure of an analog-to-digital converter provided in another embodiment of the present application;

FIG7 is a system framework diagram of a current detection chip provided in an embodiment of the present application;

FIG8 is a schematic diagram of the structure of a shared half-side operational amplifier provided in an embodiment of the present application;

FIG9 is a schematic flow chart of a current detection method provided in another embodiment of the present application;

FIG. 10 is a schematic diagram of the structure of a computer device provided in an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

FIG1 shows a schematic diagram of an application scenario of a microcurrent detection device provided in an embodiment of the present application.

As can be seen from FIG. 1 , the microcurrent detection device provided in the present application can be used to detect and read out the microcurrent generated during the nanopore sequencing process.

Nanopore sequencing refers to the technology of using nanopores to detect DNA or RNA gene sequences. As shown in Figure 1, the principle is that when a nucleic acid molecule 1 is guided through a nanopore 2, different base sequences of the nucleic acid molecule 1 will generate a weak current signal (pA level), and the current detection device 3 measures and analyzes the weak current signal to determine the base sequence of the nucleic acid molecule.

It is understandable that the current detection device 3 may be a nanopore sequencing current detection chip integrated with a corresponding circuit.

Based on the number of channels and processing power, nanopore sequencing current detection devices can be divided into single-channel type and array type (multi-channel type). The difference is that the single-channel type has only one nanopore channel, so it can only read the sequence information of one nucleic acid molecule at a time and process it in sequence, with low power consumption, small area, low processing power and long processing time; while the array type contains multiple nanopore channels, which can read and process the sequence information of multiple nucleic acid molecules at the same time, with high power consumption, large area and stronger processing power.

In response to the problems existing in the above two types of nanopore sequencing current detection devices, the present application proposes a new current detection architecture, which aims to combine the advantages of single-channel and array types to achieve miniaturization, low cost and high accuracy of nanopore sequencing devices.

FIG2 shows a schematic structural diagram of a microcurrent detection device provided in an embodiment of the present application.

A structure of a micro-current detection device 200 is described below in conjunction with FIG. 2 .

The micro-current detection device 200 may include a current integration module 210 , a correlated double sampling module 220 , a differential amplification module 230 and an analog-to-digital converter 240 .

It can be seen from FIG. 2 that the current integration module 210 , the correlated double sampling module 220 , the differential amplification module 230 and the analog-to-digital converter 240 are connected in sequence.

The current integration module 210 is used to receive the microcurrent signal from the nanopore sequencing and perform integration operation to convert it into a corresponding voltage signal.

The correlated double sampling module 220 is used to sample the voltage signal generated by the current integration module 210 twice to obtain two voltage sampling results.

The differential amplifier module 230 is used to perform differential amplification processing on the two voltage sampling results generated by the correlated double sampling module 220 to obtain a fully differential voltage signal.

The analog-to-digital converter 240 is used to convert the fully differential voltage signal generated by the differential amplifier module 230 into characteristic data of micro-current and output it.

Exemplarily, the characteristic data corresponding to the microcurrent generated by the analog-to-digital converter 240 may be a 15-bit digital quantity.

The internal structure of the current integration module 210 is described below.

The current integration module 210 includes a plurality of current input interfaces 211 and a plurality of operational amplifiers 212 , and there is a one-to-one corresponding connection relationship between the plurality of current input interfaces 211 and the plurality of operational amplifiers 212 .

The current input interface 211 is used to receive the microcurrent signal generated by the nanopore sequencing and transmit it to the corresponding operational amplifier 212 for processing.

The operational amplifier 212 is used to integrate and amplify the micro-current signal received from the corresponding current input interface 211 and convert it into a voltage signal.

It should be noted that the multiple operational amplifiers 212 in the current integration module 210 adopt a shared half-side operational amplifier design. That is, all operational amplifiers 212 do not have completely independent circuits, but share the same circuit elements, that is, share the same input terminal.

It should be understood that the shared part may be an inverting input terminal or a non-inverting input terminal, and this application does not limit this.

It should also be understood that the current input interface 211 is connected to the remaining independent input terminals of the operational amplifier 212 .

The present application adopts a shared half-side operational amplifier design to share some circuit elements between multiple operational amplifiers. The advantages are: it can make the current detection circuit more compact as a whole, occupy less space, and reduce the number of devices and power consumption in the current detection circuit, thereby reducing the energy consumption and manufacturing cost of the system; in addition, the shared part can make the shared circuit elements more matched, reduce the impact of offset and noise, and improve the performance and stability of the entire current detection system.

Optionally, the operational amplifier 212 is a capacitive feedback transconductance amplifier (CTIA). Compared with other operational amplifiers, the capacitive feedback transconductance amplifier has the characteristics of high gain, wide bandwidth, low noise and good stability while ensuring the amplifier performance. It is suitable for amplifying the low current signal generated by nanopore sequencing and has high noise requirements.

FIG3 is a circuit diagram of a capacitive feedback transconductance amplifier based on a shared half-side op amp according to an embodiment of the present application. As can be seen from the figure, m capacitive feedback transconductance amplifiers share the same non-inverting input terminal. Each capacitive feedback transconductance amplifier includes a common non-inverting input terminal, an independent inverting input terminal and an output terminal. Among them, the capacitive feedback transconductance amplifier receives a micro-current signal sent from a corresponding current input interface through an inverting input terminal, performs integral amplification processing to obtain a voltage signal corresponding to the micro-current signal, and then outputs it through the output terminal.

The internal structure of the correlated double sampling module 220 is described below.

The correlated double sampling module 220 includes a plurality of identical correlated double sampling circuits 221 .

There is also a one-to-one connection relationship between each correlated double sampling circuit 221 and each operational amplifier in the current integration module 210 .

The correlated double sampling circuit 221 is used to sample the voltage signal from the corresponding operational amplifier twice to obtain two voltage sampling results, that is, to sample the voltage at the initial stage of integration and the final stage of integration respectively, and to obtain the first voltage signal and the second voltage signal accordingly.

Optionally, the correlated double sampling module 220 may further include one or more analog buffers, which are used to temporarily store the voltage sampling results for subsequent processing or conversion.

It should be noted that the current input interface 211, the amplifier 212 in the current integration module 210 and the correlated double sampling circuit 221 in the correlated double sampling module 220 are connected one by one. In simple terms, each current input interface 211, the amplifier 212 and the correlated double sampling circuit 221 are connected in pairs with each other. Each group of such connections (current input interface 211, amplifier 212 and correlated double sampling circuit 221) constitutes a current detection unit. Each current detection unit has a specific purpose, that is, it is used to detect the current of a nanopore sequencing microcurrent detection channel.

FIG4 is a circuit diagram of a current detection unit according to an embodiment of the present application. The circuit structure 1 on the left side of the figure is an example of a current input interface 211 and an amplifier 212, and the circuit structure 2 on the right side is an example of a correlated double sampling circuit 221. As can be seen from the figure, in this example, the first voltage signal is stored in a buffer and the second voltage signal is stored in another buffer for further analysis or digital processing.

FIG. 5 is a schematic diagram of an example of a working sequence of a current detection device according to an embodiment of the present application.

The working principle and sampling process of the correlated double sampling circuit are described below in conjunction with FIG. 4 and FIG. 5 .

At the initial stage of current integration, the correlated double sampling circuit samples the voltage signal output by the integration for the first time, that is, obtains the voltage value at the beginning of the integration, which is called the first voltage signal (denoted as or/> ).

At the end of the current integration, the correlated double sampling circuit samples the voltage signal output by the integration for the second time to obtain the voltage value at the end of the integration, which is called the second voltage signal (denoted as or/> ).

By sampling twice, the correlated double sampling circuit can obtain the voltage values at the start and end of the integration process, so that the change of the voltage signal, that is, the result of the integration, can be calculated.

The analog correlated double sampling method and circuit design adopted in this application have a good suppression effect on fixed offset voltage 1/f noise and low-frequency noise, and have a certain suppression effect on thermal noise and KT/C noise, thereby reducing and eliminating errors caused by factors such as circuit drift and noise, and improving the accuracy and reliability of integration.

The internal structure of the differential amplifier module 230 is described below.

The differential amplifier module 230 includes a fully differential switched capacitor amplifier.

Optionally, the fully differential switched capacitor amplifier has an offset voltage cancellation function.

The fully differential switched capacitor amplifier is used for voltage sampling and differential amplification. Specifically, in the sampling state, the fully differential switched capacitor amplifier samples the first voltage signal and the second voltage signal stored in the correlated double sampling module; and, in the amplification state, the fully differential switched capacitor amplifier amplifies the difference between the first voltage signal and the second voltage signal into a fully differential voltage signal.

It can be understood that the first voltage signal and the second voltage signal sampled by the correlated double sampling module 220 are pseudo differential signals converted from the same micro-current signal. In the differential amplifier module 230, one signal is subtracted from the other signal, and the difference is increased by an amplifier, thereby realizing the conversion of the two pseudo differential signals of the first voltage signal and the second voltage signal into a full differential signal. This method can obtain a larger dynamic range and gain, which helps to improve the measurability and reliability of the signal.

It should be understood that, unlike the operational amplifier 212 in the current integration module 210, the switched capacitor amplifier 232 in the differential amplifier module 230 is multiplexed, thereby greatly reducing the power consumption of a single detection channel, thereby completing the amplification of the pA-level nanopore weak current into an mV-level voltage signal under the constraints of low power consumption and low noise.

Based on the above description, it can be known that after the first voltage signal and the second voltage signal output by the correlated double sampling module 220 enter the pseudo differential to full differential module 231, they are differentially processed and then amplified by the switched capacitor amplifier 232 to obtain a full differential voltage signal. .

Fully differential voltage signal The calculation formula is as follows:

,

in, is the fully differential output voltage,/> is the positive output voltage of the fully differential switched capacitor amplifier, is the negative output voltage of the fully differential switched capacitor amplifier, /> is the gain of the two-stage fully differential switched capacitor amplifier.

It should be noted that the voltage sampled at the initial stage of current integration is Only circuit noise is included and the offset voltage of the op amp/> , and the voltage sampled at the end of the current integration phase/> Including circuit noise , offset voltage/> And the voltage signal obtained by integration/> It can be understood that the core part of the difference between the voltage signals obtained by the two samplings is the voltage signal obtained by integration, which contains the information of the nanopore sequencing current.

Considering the noise and offset, the more correlated the noise of the two samples is, the better the noise suppression effect will be after the correlated double sampling. The output voltage after the pseudo-differential to full differential module is The actual value is:

,

This processing method can offset the impact of circuit noise and offset on the final output to a certain extent, improving the accuracy and reliability of the signal. In addition, the fully differential signal has a good suppression ability for common mode noise such as power frequency interference and clock crosstalk, which can further improve the signal quality.

The device disclosed in this application, through multiple current input interfaces and corresponding operational amplifiers, and the parallel design of correlated double sampling circuits, can process microcurrent signals from multiple nanopore sequencing channels in parallel, effectively improving the efficiency and real-time performance of current detection, so that it can meet the needs of high-throughput nanopore sequencing. On this basis, the design of shared half-side operational amplifiers effectively reduces the overall area and power consumption of the system. In addition, the design of correlated double sampling and differential amplifier circuits helps to reduce the impact of noise on the results, thereby ensuring the accuracy and reliability of the data.

In summary, this scheme achieves efficient readout of nanopore sequencing current by setting up multiple current detection channels, sharing half-edge op amps, performing correlated double sampling and differential amplification, meeting the needs of high-throughput sequencing and having good technical effects.

In one embodiment, the microcurrent detection device 200 may further include a digital encoding module 250. The digital encoding module 250 is used to encode the digital quantity output by the analog-to-digital converter 240 and convert it into a specific digital format or encoding method to facilitate subsequent digital signal processing or transmission.

In one example, the analog-to-digital converter 240 quantizes the characteristic data corresponding to the microcurrent into a 15-bit digital quantity, and the digital encoding module 250 converts the 15-bit non-binary digital quantity into a 12-bit binary digital quantity and outputs it together with the gain code and the address code.

In one embodiment, the micro-current detection device 200 further includes an addressing module 260 and a channel selector.

One end of the channel selector is simultaneously connected to a plurality of correlated double sampling circuits, and the other end is connected to a differential amplifier module.

The addressing module 260 is used to control the channel selector to traverse and select each correlated double sampling circuit among the multiple correlated double sampling circuits, and transmit the first voltage signal and the second voltage signal stored in the selected correlated double sampling circuit to the differential amplification module 230 for processing.

In one embodiment, the micro-current detection device 200 may further include a clock generation module 270. The clock generation module 270 is used to synchronize the operation of each module in the micro-current detection device 200 to ensure that they operate according to a predetermined time sequence.

In the analog-to-digital converter 240, the bridge capacitance in the segmented capacitance is a fractional multiple of the unit capacitance, which is difficult to match in the actual manufacturing process. The device of the present application proposes to add a dummy capacitance at a low position to actively introduce a mismatch, so that the bridge capacitance is an integer multiple of the unit capacitance, thereby reducing the impact of the capacitance mismatch on the ADC performance.

That is, optionally, the analog-to-digital converter 240 may include at least one virtual capacitor. The virtual capacitor is used to adjust the size of the bridge capacitor in the analog-to-digital converter and is located at the lower part of the analog-to-digital converter 240.

Optionally, the analog-to-digital converter 240 may be a successive approximation register analog-to-digital converter (SAR ADC). The working principle of the SAR ADC is to determine the digital representation of the analog signal by stepwise approximation. Compared with other types of SAR converters, the SAR ADC has the advantages of high speed, low power consumption and applicability to a wide range of applications.

In order to correct comparator comparison errors caused by comparator noise or external interference in a successive approximation analog-to-digital converter (SAR ADC) during a conversion process, the present application introduces N (N≥1, a positive integer) bits of redundancy in the successive approximation analog-to-digital converter for self-error correction of the successive approximation analog-to-digital converter.

In the design of DAC, there is usually a series of capacitors used to represent different bits. By adjusting the value of these capacitors, the output of each bit can be controlled, including the redundant bits.

In an example shown in FIG6 , the present application proposes a novel CDAC with three-bit redundancy, which realizes three-bit redundancy by splitting and redistributing the capacitors of the high-order part and the low-order part. The design method is as follows:

First, the capacitance of the highest and second highest bits of the high-order part (MSB segment) is split into 24*Cu (Cu represents a unit capacitance, 24*Cu represents 24 times the unit capacitance) + 8*Cu and 12*Cu + 4*Cu respectively. The capacitance of the highest bit is 24*Cu, the capacitance of the second highest bit is 12*Cu, and the split 8*Cu and 4*Cu are placed in the lower bits to form 2-bit redundancy.

Similarly, the capacitance of the highest bit of the low-order part (LSB segment) is split into 12*Cu+4*Cu, 12*Cu is placed at the highest bit of the original LSB segment, and 4*Cu is placed at the lower bit to form a redundant bit.

Therefore, the two redundancy bits in the MSB segment plus the one redundancy bit in the LSB segment form a total of three redundancy bits. These redundant bits can improve the fault tolerance and accuracy of the system, thereby improving the performance of the analog-to-digital converter.

In another example, based on the above design, a dummy capacitor of 31*Cu can be introduced at the low position of CDAC, so that the bridge capacitance of the segmented capacitor CDAC is an integer multiple of the unit capacitance 2*Cu, which can greatly reduce the mismatch of the bridge capacitance and reduce the impact of process mismatch on the performance of SAR ADC.

The SAR ADC with 3-bit redundant CDAC in the above example is simulated, and the result is: at a sampling rate of 5MHz, when the input signal is 2.01MHz, its effective number of bits (ENOB) is 11.61bit, which verifies that this new segmented redundant CDAC can achieve good performance.

FIG. 7 shows a system framework diagram of a nanopore sequencing weak current detection chip provided in an embodiment of the present application.

It can be understood that the nanopore sequencing weak current detection chip in this embodiment is an example of the current detection device in FIG. 2 .

The chip includes 7 modules: a current integration module 710 (an example of the current integration module 210 in Figure 2), a correlated double sampling module 720 (an example of the correlated double sampling module 220 in Figure 2), a differential amplifier module 730 (an example of the differential amplifier module 230 in Figure 2), an analog-to-digital conversion module 740 (an example of the analog-to-digital converter 240 in Figure 2), a digital encoding module 750, an addressing module 760, and a clock generation module 770.

Each module uses the circuit structure shown in the figure to realize its function. It should be emphasized that the current integration module 710 uses a 32-channel current integration circuit based on a shared half-edge operational amplifier; the analog-to-digital conversion module 740 includes an analog-to-digital converter based on a new segmented 3-bit redundant.

Based on the above design, the chip can simultaneously detect the nanopore sequencing currents of 32 channels and quantify them into digital quantities for output.

As shown in the system framework diagram in Figure 7, the front end of the chip is 4 groups of capacitive feedback transconductance amplifiers (CTIA) based on 8 shared half-side op amps, which are used to integrate the nanopore current and convert it into a voltage signal to achieve a high transconductance gain of GΩ level. This new shared half-side op amp allows 8 CTIAs to share one half-side op amp, which can reduce the power consumption, offset and noise of a single detection unit by nearly half, achieving a balance between power consumption and noise.

The specific transistor-level implementation of sharing 8 half-side op amps is shown in Figure 8. The shared half-side circuit (i.e., the first stage) consists of M0, M1, M3, M5, M6, and M7. Eight independent half-side circuits are added to the common node VCOM of the first stage. The nth independent half-side circuit (i.e., the nth stage) includes M2_n, M4_n, M8_n, M9_n, and M10_n, where n ranges from 1 to 8, and the bias voltages VBP1, VBP2, Vcn, and Vbn1 are independently generated by the bias circuit. The shared half-side circuit contains a negative feedback loop that maintains the common node voltage VCOM at a level just above the in-phase input voltage Vip, so that transistor M0 can automatically adjust the sum of the currents flowing through a shared half-side circuit and the eight independent half-side circuits. The operation of a single amplifier is described by considering the first-stage shared half-side circuit and the independent nth-stage half-side circuit. If the voltage at the reverse input terminal of the nth stage Equal to the voltage at the same-direction input terminal of the shared stage/> , then the M2_n tube, which is the same as the M1 tube, will also flow through the current of Ib, and at this time all the tubes of the shared op amp are in the saturation region. If/> Slightly lower/> , then transistor M2_n will flow a current much larger than Ib, thereby reducing the current in M10_n, and Vout<n> increases until M8_n is in the linear region. Conversely, if/> Slightly above , then transistor M2_n will flow a current much smaller than Ib, thereby increasing the current in M10_n,/> Decrease until M10_n is in the linear region.

exist ≈/> Under the condition of , the incremental output voltage of the shared half operational amplifier is obtained by the following formula:

,

and

,

in, is the low frequency gain of the amplifier, /> is the transconductance of the transistor, /> is the output resistance of the transistor.

In addition, the offset of the shared op amp in the first-stage CTIA and the spatial noise of the nanopore itself are stored in the capacitor through analog correlated double sampling. At the same time, correlated double sampling (CDS) can also greatly reduce the low-frequency circuit flicker noise that greatly interferes with the nanopore current signal. The first-stage CTIA and CDS form a weak current detection unit. The main offset, noise and power consumption of a single detection unit all come from the operational amplifier in the first-stage CTIA. After testing, the noise frequency domain curve of the current integration output voltage without correlated double sampling corresponds to a noise floor of 62.5uV/√Hz, while the noise frequency domain curve of the current integration output voltage after correlated double sampling corresponds to a noise floor of 38.03uV/√Hz. It can be seen that after the shared half-side op amp and correlated double sampling, the noise of the output voltage is suppressed by more than 1/3.

Then, under the control of the addressing circuit, a single detection unit enters the second-stage 8×4 unit multiplexed switched capacitor amplifier through the selection of the analog channel selector, and further amplifies the amplified voltage signal to improve the signal-to-noise ratio. At the same time, the switched capacitor amplifier is multiplexed, so the power consumption of a single detection channel can be greatly reduced. In this way, the weak current of the nanopore at the pA level is amplified into a voltage signal at the mV level under the constraints of low power consumption and low noise.

In the multi-channel multiplexed digital-to-analog converter (ADC) part, the bridge capacitor in the segmented capacitor is a fractional multiple of the unit capacitor, which is difficult to match in the actual manufacturing process. This chip proposes to add a dummy capacitor at the low position to actively introduce mismatch, so that the bridge capacitor is an integer multiple of the unit capacitor, reducing the impact of the capacitor mismatch on the ADC performance. In addition, in order to correct the comparator comparison error caused by the noise of the comparator or external interference during a certain conversion process of the successive approximation analog-to-digital converter (SAR ADC), three-bit redundancy is introduced for ADC self-correction. The 12-bit SAR ADC based on the new segmented 3-bit redundant CDAC in this chip has an effective number of bits (ENOB) of 11.61 bits when the input signal is 2.01MHz at a sampling rate of 5MHz. It can be verified that this new segmented redundant CDAC can achieve good performance.

The chip working sequence is referenced to FIG2 . The working process of the chip is as follows: First, the weak current generated by 32 channels of DNA (an example of nucleic acid molecule 1 in FIG1 ) passing through the nanopore will pass through the 32-channel current integration module 710 respectively. The current integration module 710 integrates the nanopore current at a fixed frequency of 20kHz under the control of the clock and converts it into voltage. The integrated voltage is sampled once in the initial stage of the current integration and once in the final stage of the current integration, and is cached in the analog buffer. In the next current integration cycle, the addressing module controls the channel selector to time-select the initial integration voltage and the end integration voltage cached by the 32-channel current integration module 710 to the pseudo-differential to full differential module for subtraction and amplification again. After sampling, it is quantized into a 15-bit digital quantity through a multiplexed analog-to-digital converter. After passing through the digital encoding module 750, the 15-bit non-binary quantity is converted into a 12-bit binary digital quantity and then output together with the gain code and address code.

Table 1

The chip indicators are shown in Table 1 above.

The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

FIG. 9 is a flow chart of a circuit detection method provided in an embodiment of the present application.

As shown in FIG. 9 , the circuit detection method may include the following steps.

S1, using a current integration module to collect microcurrent signals generated by multiple nanopore sequencing, integrate and amplify the microcurrent, and convert it into a voltage signal;

S2, using a correlated double sampling module to sample a first voltage signal output by the current integration module at an initial stage of current integration, and a second voltage signal output by the current integration module at an end stage of current integration;

S3, using a differential amplifier module to determine a fully differential output voltage corresponding to the micro-current signal according to the first voltage signal and the second voltage signal;

S4. Generate characteristic data of the micro-current according to the fully differential output voltage using an analog-to-digital converter and output it.

It should be understood that, although the various steps in the flow chart involved in the above-mentioned embodiment are shown in sequence, these steps are not necessarily performed in sequence according to the order shown in the figure. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flow chart involved in each embodiment as described above may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of the steps or stages in other steps or other steps.

FIG10 is a schematic diagram of the structure of a computer device provided in an embodiment of the present application. As shown in FIG10 , the computer device 1000 includes: at least one processor 1003 (only one is shown in FIG10 ), a memory 1001, and a computer program 1002 stored in the memory 1001 and executable on the processor 1003. When the processor 1003 executes the computer program 1002, steps S1 to S4 in the method embodiment of FIG9 are implemented; or, when the processor 1003 executes the computer program 1002, the functions of modules 210 to 240 in the device embodiment of FIG2 are implemented.

The processor 1003 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

In some embodiments, the memory 1001 may be an internal storage unit of the computer device 1000, such as a hard disk or memory of the computer device 1000. In other embodiments, the memory 1001 may also be an external storage device of the computer device 1000, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the computer device 1000. Further, the memory 1001 may also include both an internal storage unit of the computer device 1000 and an external storage device. The memory 1001 is used to store an operating system, an application program, a boot loader, data, and other programs, such as the program code of the computer program. The memory 1001 may also be used to temporarily store data that has been output or is to be output.

An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by an electronic device, the steps in the above-mentioned method embodiments can be implemented.

The computer-readable medium may include at least: any entity or device capable of carrying computer program codes to a camera/electronic device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electric carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk, or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

The embodiment of the present application provides a computer program product, which includes a computer program, and when the computer program is executed by an electronic device, the steps in the above-mentioned various method embodiments can be implemented. The computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form.

In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

In the embodiments provided in the present application, it should be understood that the disclosed devices/network equipment and methods can be implemented in other ways. For example, the device/network equipment embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In the above description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and/or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and/or combinations thereof.

It should also be understood that the term “and/or” used in the specification and appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims (10)

1. The micro-current detection device is characterized by comprising a current integration module, a correlated double sampling module, a differential amplification module and an analog-to-digital converter;

The current integration module comprises a plurality of current input interfaces and a plurality of operational amplifiers sharing the same input end, and each current input interface corresponds to one operational amplifier and is connected with the non-shared input end of the operational amplifier; each current input interface is used for receiving a micro-current signal generated during nanopore sequencing and transmitting the micro-current signal to a corresponding operational amplifier for processing, and each operational amplifier is used for carrying out integral amplification on the received micro-current signal and converting the micro-current signal into a voltage signal;

The correlated double sampling module comprises a plurality of correlated double sampling circuits, each correlated double sampling circuit corresponds to one operational amplifier and is connected with the output end of the operational amplifier, and the correlated double sampling circuits are used for sampling a first voltage signal output by the operational amplifier in the initial stage of current integration and sampling a second voltage signal output by the operational amplifier in the end stage of current integration;

the differential amplification module is used for determining a fully differential voltage signal corresponding to the micro-current signal according to the first voltage signal and the second voltage signal;

The analog-to-digital converter is used for generating and outputting characteristic data of the micro-current according to the fully differential voltage signal.

2. The apparatus of claim 1, wherein the microcurrent detection apparatus further comprises an addressing module and a channel selector, one end of the channel selector being connected to the plurality of correlated double sampling circuits, the other end of the channel selector being connected to the differential amplification module; the addressing module is used for controlling the channel selector to traverse and select each relevant double sampling circuit in the relevant double sampling circuits, and transmitting the first voltage signal and the second voltage signal stored in the relevant double sampling circuits to the differential amplification module for processing.

3. The apparatus of claim 1, wherein the differential amplification module comprises a fully differential switched capacitor amplifier for sampling the first voltage signal and the second voltage signal stored in the correlated double sampling module, and for amplifying a difference between the sampled first voltage signal and the sampled second voltage signal into the fully differential voltage signal.

4. The apparatus of claim 3, wherein the fully differential voltage signal is derived using the formula:

，

Wherein, For the fully differential voltage signal,/>For the amplification factor of the fully differential switched-capacitor amplifier,/>For the first voltage signal,/>Is the second voltage signal.

5. The apparatus according to any one of claims 1 to 4, wherein the analog-to-digital converter comprises at least one virtual capacitor for adjusting the size of a bridge capacitor in the analog-to-digital converter and located in a low-order part of the analog-to-digital converter.

6. The apparatus according to any one of claims 1 to 4, wherein the analog-to-digital converter is a successive approximation type analog-to-digital converter with N redundancy bits; wherein N is more than or equal to 1 and is a positive integer.

7. The apparatus of any one of claims 1 to 4, wherein the operational amplifier is a capacitive feedback transconductance amplifier.

8. The apparatus of any of claims 1-4, wherein each of the correlated double sampling circuits comprises at least one analog buffer for buffering the first voltage signal and the second voltage signal.

9. A microcurrent detection method, comprising:

Respectively collecting micro-current signals generated during sequencing of a plurality of nanopores by using a current integration module, and performing integration amplification on the micro-current signals to convert the micro-current signals into voltage signals;

sampling a first voltage signal output by the current integration module in a current integration initial stage by using a correlated double sampling module, and sampling a second voltage signal output by the current integration module in a current integration ending stage;

Determining a fully differential voltage signal corresponding to the micro-current signal according to the first voltage signal and the second voltage signal by utilizing a differential amplification module;

And generating characteristic data of the micro-current according to the fully differential voltage signal by using an analog-to-digital converter and outputting the characteristic data.

10. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, when executing the computer program, causing the computer device to implement the method of claim 9.