CN118018052A - A multi-channel synchronous transceiver and synchronization method - Google Patents

Abstract

The present invention discloses a multi-channel synchronous transceiver and a synchronization method, which are mainly composed of N multi-channel signal acquisition and transmission boards and one frequency synthesis calculation board. The multi-channel signal acquisition and transmission board includes a clock module and an integrated system on chip. The frequency synthesis calculation board includes a power division unit, a clock generation unit, a combining unit, a 1:N buffer unit and a compensation calculation unit. The integrated system on chip involves a data compensation unit, data reception, data generation, a delay unit, a multi-block synchronization unit and M tile blocks. The present invention reduces the design complexity of the synchronization system and reduces the amount of resources occupied by the system-level multi-channel signal synchronization calibration by optimizing the design architecture of the multi-channel synchronous transceiver.

Description

A multi-channel synchronous transceiver and synchronization method

Technical Field

The present invention relates to the field of electronic information technology, and specifically to a multi-channel synchronous transceiver and a synchronization method, which can be applied to the design of a digital beamforming system.

Background technique

Multi-channel signal acquisition and transmission processors based on software-defined radio are often used in the design of beamforming systems, which have the advantages of improving the signal-to-noise ratio and enhancing the anti-interference ability of the system. However, this design often places high requirements on the synchronization of the acquisition and transmission channels, and as the number of array elements increases, the complexity of the synchronization calibration system also increases.

As a researcher in related fields, in addition to ensuring that the synchronization of the system's transceiver channels meets the requirements, the equipment cost required for the synchronization calibration of multi-channel transceivers, the difficulty of setting up the test environment, and the flexibility of use have always been important factors that need to be considered. Therefore, how to combine the development of integrated on-chip systems to simplify the design of traditional multi-channel synchronous transceiver systems and reduce the complexity of the system has always been a problem that needs to be solved.

Summary of the invention

The purpose of the present invention is to provide a multi-channel synchronous transceiver device and a synchronization method to address the problems existing in the background technology, which can reduce the amount of resources occupied by traditional synchronization calibration and reduce the complexity of system design.

To achieve the above objectives, according to the first aspect of the present invention, the present invention adopts the following technical solutions:

A multi-channel synchronous transceiver, characterized in that: the multi-channel synchronous transceiver is composed of N multi-channel signal acquisition and transmission boards and 1 frequency synthesis calculation board, wherein:

The multi-channel signal acquisition and transmission board includes a clock module and an integrated on-chip system, wherein the integrated on-chip system includes a data compensation unit, a data receiving unit, a data generating unit, a delay unit, a multi-block synchronization unit and M tile blocks, each tile block is composed of an ADC or a DAC;

The frequency synthesis calculation board comprises a power division unit, a clock generation unit, a combining unit, a 1:N buffer unit and a compensation calculation unit.

Preferably, the 1:N buffer unit model is ADI's HMC987LP5E.

Preferably, the clock module is TI's LMK0428X, and the SYNC signal and the reference clock from the 1:N buffer unit are connected to the sync pin and the reference clock pin of the clock module respectively. The SYNC signal determines the fixed phase relationship between the input reference clock and the output clock of the clock module, so as to realize the alignment of multiple output clocks.

The data compensation unit is used to receive the relative delay value sent by the compensation calculation unit, and compensate the relative delay value at the baseband data using a calibration compensation algorithm.

The data generating unit is used for generating waveform data, and the amplitude, frequency and phase of the output waveform are adjustable. The data receiving unit is used for receiving the cache of the waveform data.

The delay unit uses the logic reference clock output by the clock module to capture the logic timing reference for the delay of the timing trigger signal, thereby realizing the output alignment of the timing trigger signal between the multi-channel signal acquisition and sending cards.

After receiving the timing trigger signal, the multi-block synchronization unit triggers the reset operation to reset the frequency divider of the internal phase-locked loop and the digital frequency divider of the NCO, thereby realizing the phase alignment of the high-speed sampling clock inside the integrated on-chip system. The logic reference clock resets the counter of the dual clock FIFO in the Tile block by capturing the logic timing reference. The Tile block sends the analog timing reference to the logic end through the FIFO. When the logic reference clock detects the analog timing reference, the counter is stopped immediately, that is, the delay value between multiple channels can be represented by the value of the counter.

According to the second aspect of the present invention, the present invention adopts the following technical solution:

The synchronization method using the above multi-channel synchronous transceiver is characterized by:

The clock generating unit generates a SYNC signal and outputs N SYNC signals to the clock module via a 1:N buffer unit;

The clock generation unit generates a reference clock and outputs N reference clocks to the clock module via a 1:N buffer unit;

The clock module connects the SYNC signal and the reference clock from the 1:N buffer unit to the sync pin and the reference clock pin of the clock module respectively;

Each of the clock modules outputs four clocks, namely, analog timing reference clock, logic timing reference clock, analog reference clock, and logic reference clock, to four pins named analog_sysref, pl_sysref, pl_refclk, and analog_refclk in each integrated system-on-chip;

The delay unit uses the logic reference clock output by the clock module to capture the logic timing reference for the delay of the timing trigger signal, thereby realizing the output alignment of the timing trigger signals among multiple boards.

Furthermore, the delay residuals caused by the power splitter unit and the combiner unit can be calibrated and compensated in advance.

Furthermore, the multi-block synchronization unit completes the delay alignment between tiles and the deterministic delay compensation of the dual-clock FIFO according to the four clocks provided by the clock module, thereby realizing the synchronous operation of all tiles; the compensation calculation unit calculates the DAC channel delay between N multi-channel signal acquisition and transmission boards, and feeds back the delay value to the data compensation unit of each board, and the data compensation unit completes the relative delay compensation at the baseband data generation point; the compensation calculation unit calculates the ADC channel delay between N multi-channel signal acquisition and transmission boards, and feeds back the delay value to the data compensation unit of each board, and the data compensation unit completes the relative delay compensation at the baseband data reception point.

The specific process of the compensation calculation unit performing delay calculation and compensation of DAC channels between N multi-channel signal acquisition and transmission boards is as follows:

Step 1: The compensation calculation unit outputs a trigger pulse to the data compensation unit of the multi-channel signal acquisition and sending card.

Step 2 performs a delay operation in the data compensation unit, that is, the data generation time of the 2nd, 3rd...Nth blocks is delayed by 10*(N-1)ms respectively, and the data generation unit of each board only generates a 10ms data waveform, that is, the combining unit is time-division multiplexed.

Step 3: The compensation calculation unit restores the waveform of the channel according to the data collected within 10 ms, and calculates the relative delay of other channels with reference to the first channel at a certain time point thereafter.

Step 4 feeds back the relative delay value to the data compensation unit of each board, and the data compensation unit compensates for the relative delay at the baseband data generation location.

The specific process of the compensation calculation unit performing delay calculation and compensation of ADC channels between N multi-channel signal acquisition and transmission boards is as follows:

Step 1: The compensation calculation unit outputs a single-tone signal which is sent to the ADC through the power division unit output N channels to complete analog-to-digital conversion.

Step 2: The data compensation unit extracts the cached data and sends it to the compensation calculation unit.

Step 3: After the compensation calculation unit performs FFT conversion on the received data, it calculates the relative delays of other channels with the first channel as a reference.

Step 4 feeds back the delay value to the data compensation unit of each board, which compensates for the relative delay at the baseband data receiving point, thereby completing the synchronization calibration of signals between N multi-channel signal acquisition and transmission boards.

Preferably, the power splitter unit and the combining unit are of the ADP-2-20+ type of Min-Circuit, and the delay residuals caused by the power splitter unit and the combining unit can be calibrated and compensated in advance.

The present invention utilizes the above-mentioned multi-channel synchronous transceiver to solve the problem that the complexity of the synchronous calibration system increases with the increase in the number of array elements, that is, the system design of the multi-channel synchronous transceiver is optimized, the amount of resources occupied by the synchronous calibration of multi-channel signals between multiple boards is reduced, and the design complexity of the system is reduced. At the same time, during the synchronous operation process, the relative delay value between multiple channels can be calibrated and iterated multiple times until the synchronization accuracy meets the actual design requirements.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a multi-channel synchronous transceiver device and a synchronization method according to the present invention.

FIG. 2 is a schematic diagram of an embodiment of a multi-channel synchronous transceiver device and a synchronization method according to the present invention.

FIG. 3 is a schematic diagram of a flow chart of DAC channel signal delay calculation and calibration in an embodiment of the present invention.

FIG. 4 is a schematic diagram of a flow chart of ADC channel signal delay calculation and calibration in an embodiment of the present invention.

Detailed ways

In order to enable people to intuitively and vividly understand each technical feature and the overall technical solution of the present invention, the technical solution of the present invention will be clearly and completely explained below in conjunction with a schematic diagram of an embodiment of the present invention.

FIG1 is a schematic diagram of a multi-channel synchronous transceiver device and a synchronization method of the present invention, which includes N multi-channel signal acquisition and transmission boards and one frequency synthesis calculation board.

The multi-channel signal acquisition and transmission board in Figure 1 includes a clock module and an integrated on-chip system. The integrated on-chip system includes a data compensation unit, a data receiving unit, a data generation unit, a delay unit, a multi-block synchronization unit and M tile blocks, each of which is composed of an ADC or a DAC.

The frequency synthesis calculation board comprises a power division unit, a clock generation unit, a combining unit, a 1:N buffer unit and a compensation calculation unit.

As shown in Figure 1, first, each multi-channel signal acquisition and transmission board uses multiple synchronization units to realize synchronization calibration between tile blocks. Secondly, each multi-channel signal acquisition and transmission board provides one ADC signal and one DAC signal to the frequency synthesis calculation board respectively. The delay value of each signal acquisition board relative to the first multi-channel signal acquisition board is obtained through the compensation calculation unit and the delay value is fed back. Finally, the delay value compensation operation is performed inside each board to realize signal synchronization between N multi-channel signal acquisition and transmission boards.

Specifically, in one embodiment of the present invention, the multi-channel synchronous transceiver device shown in FIG. 2 includes two multi-channel signal acquisition and transmission boards and one frequency synthesis calculation board.

In the embodiment described, the frequency synthesis calculation board includes a power division unit, a clock generation unit, a combining unit, a 1:N buffer unit and a compensation calculation unit.

The multi-channel signal acquisition and transmission board includes a clock module and an integrated system on chip.

The model of the integrated system-on-chip in the described embodiment is Xilinx's RFSOC-XCZU47DR. The RFSOC includes a data compensation unit, data reception, data generation, a delay unit, a multi-block synchronization unit and 8 tile blocks, 4 of which are each composed of 2 ADCs, and the other 4 Tile blocks are each composed of 2 DACs. Each multi-channel signal acquisition and transmission board is an 8-receive and 8-transmit signal path.

To simplify the synchronization system design of multi-channel synchronous transceiver, the synchronization between tiles on the board must be ensured first. Therefore, the following four conditions must be met:

1) Ensure that the reference clock phases between boards are consistent.

2) Ensure that the clock module outputs the same phase.

3) Ensure that the high-speed sampling clock output phase is consistent.

4) Ensure that the high-speed sampling clock can stably capture the timing reference clock.

To meet the above conditions, the present invention achieves synchronization between tiles through software and hardware collaboration. The following is a specific software and hardware design method:

In the embodiment described, the clock generation unit generates a SYNC signal and a base reference signal and sends them to the 1:N buffer unit, ensuring that all SYNC and base reference clocks have the same source.

Preferably, the 1:N buffer model in the embodiment is ADI's HMC987LP5E.

Preferably, the clock module in the embodiment is LMK0428X from TI.

In the embodiment described, the sync pin and reference clock pin of the clock module are respectively connected to the SYNC signal and the reference clock output by the 1:N buffer unit, and combined with the zero delay mode of the clock module, a fixed deterministic phase relationship is established between the input clocks from all CLKINx pins and all output clocks, generating a reference clock and timing reference output with consistent phases to the RFSOC. It should be noted that in order to ensure that the SYNC signal and the reference clock can reach the two multi-channel signal acquisition and transmission boards at the same time, the wiring from the 1:N buffer unit to different boards must be of equal length.

After ensuring that the output clock frequency of the clock module is locked, the delay unit uses the logic reference clock to capture the logic timing reference for the delay of the timing trigger signal, thereby achieving output alignment of the timing trigger signals in the two multi-channel signal acquisition and transmission boards.

In the described embodiment, after receiving the timing trigger signal, the multi-block synchronization unit triggers the reset operation to reset the internal phase-locked loop divider and the NCO digital divider, thereby realizing the phase alignment of the high-speed sampling clock inside the RFSOC. The logic reference clock resets the counter of the dual clock FIFO in the Tile block by capturing the logic timing reference. The analog timing reference is sent to the logic end through the FIFO in the Tile block. When the logic reference clock detects the analog timing reference, the counter is stopped immediately, that is, the delay value between multiple channels can be represented by the value of the counter. It should be noted that the analog timing reference and the logic timing reference must have the same frequency, and any reference clock that interacts with them must be an integer multiple thereof. This design can satisfy the requirement that the timing reference is stably captured. At this point, the synchronization conditions have been met, and the synchronization between tiles within the board can be completed by calling the API function to start the IP core.

As shown in FIG3 , the specific process of delay calculation and compensation of multiple DAC channels between boards in the embodiment is as follows:

Step 1: The compensation calculation unit outputs a trigger pulse to the data compensation units of the first and second multi-channel signal acquisition and transmission cards.

Step 2 performs a delay operation in the data compensation unit, that is, the data generation time of the second multi-channel signal acquisition and transmission card is delayed by 10ms, and the data generation unit of each board only generates a 10ms data waveform, that is, the combining unit is time-division multiplexed.

Step 3: The compensation calculation unit restores the waveform of the channel according to the data collected within 10ms, extracts the phase characteristic information of the two channels at a certain time node thereafter, and then calculates the relative delay of the DAC channel of the second multi-channel signal acquisition and sending card with reference to the DAC channel of the first multi-channel signal acquisition and sending card.

Step 4 feeds back the relative delay value to the data compensation unit of each board, and the data compensation unit compensates for the relative delay at the baseband data generation location.

As shown in FIG. 4 , the specific process of delay calculation and compensation of multiple ADC channels between boards in the embodiment is as follows:

Step 1: The compensation calculation unit outputs a single-tone signal, which is output in two ways through the power division unit and sent to the ADCs of the first and second multi-channel signal acquisition and transmission cards to complete analog-to-digital conversion.

Step 2: The data compensation unit extracts the cached data and sends it to the compensation calculation unit.

Step 3: After the compensation calculation unit performs FFT transformation on the received data, it extracts the phase characteristic information of the two channels, and calculates the relative delay of the ADC channel of the second multi-channel signal acquisition card with the ADC channel of the first multi-channel signal acquisition card as a reference.

Step 4 feeds back the delay value to the data compensation unit of each board, and the data compensation unit compensates for the relative delay at the baseband data receiving point to achieve the synchronization calibration of the signals between multiple boards.

In one embodiment of the present invention, the synchronization operation between multiple tiles inside the multi-channel signal acquisition and transmission board is first completed, that is, the remaining channels of RFSOC have a fixed delay relative to the first channel. Secondly, each signal acquisition and transmission board only needs to output one ADC and DAC channel, and calculate the relative delay of the second multi-channel signal acquisition card relative to the first multi-channel signal acquisition card channel. At this point, all channels have a known relative delay relationship with the first channel of the first multi-channel signal acquisition card. Finally, compensation can be performed at the baseband data according to the delay value fed back by the compensation calculation unit.

It should be understood that the above embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Therefore, the present invention is not limited to the specific embodiments disclosed above, and any obvious modifications within the purpose of the present invention should also be protected by the present invention.

Claims (7)

1. A multi-channel synchronous transceiver, characterized in that: the multi-channel synchronous transceiver is composed of N multi-channel signal acquisition and transmission boards and a frequency synthesis calculation board. The multi-channel signal acquisition and transmission board includes a clock module and an integrated on-chip system, wherein the integrated on-chip system includes a data compensation unit, a data receiving unit, a data generating unit, a delay unit, a multi-block synchronization unit and M tile blocks, each tile block is composed of an ADC or a DAC; The frequency synthesis calculation board comprises a power division unit, a clock generation unit, a combining unit, a 1:N buffer unit and a compensation calculation unit. 2. A multi-channel synchronous transceiver according to claim 1, characterized in that: The data compensation unit is used to receive the relative delay value sent by the compensation calculation unit, and compensate the relative delay value at the baseband data using a calibration compensation algorithm; The data generating unit is used to generate waveform data, and the amplitude, frequency and phase of the output waveform are adjustable. The data receiving unit is used to receive the cache of the waveform data. The delay unit uses the logic reference clock output by the clock module to capture the logic timing reference for the delay of the timing trigger signal, so as to achieve the output alignment of the timing trigger signal between the multi-channel signal acquisition and sending cards; After receiving the timing trigger signal, the multi-block synchronization unit triggers the reset operation to reset the internal phase-locked loop divider and the NCO digital divider, thereby realizing the phase alignment of the high-speed sampling clock inside the integrated on-chip system; the logic reference clock resets the counter of the dual clock FIFO in the Tile block by capturing the logic timing reference, and the Tile block sends the analog timing reference to the logic end through the FIFO. When the logic reference clock detects the analog timing reference, the counter is stopped immediately, that is, the delay value between multiple channels can be represented by the value of the counter. 3. A synchronization method for a multi-channel synchronous transceiver according to claim 1, characterized in that: The clock generating unit generates a SYNC signal and outputs N SYNC signals to the clock module via a 1:N buffer unit; The clock generation unit generates a reference clock and outputs N reference clocks to the clock module via a 1:N buffer unit; The clock module connects the SYNC signal and the reference clock from the 1:N buffer unit to the sync pin and the reference clock pin of the clock module respectively; Each of the clock modules outputs four clocks, namely, analog timing reference clock, logic timing reference clock, analog reference clock, and logic reference clock, to four pins named analog_sysref, pl_sysref, pl_refclk, and analog_refclk in each integrated system-on-chip; The delay unit uses the logic reference clock output by the clock module to capture the logic timing reference, which is used for delaying the timing trigger signal, so that the output of the timing trigger signal between the N multi-channel signal acquisition and transmission boards is aligned. 4. The synchronization method according to claim 3, characterized in that: The multi-block synchronization unit completes the delay alignment between tiles and the deterministic delay compensation of the dual-clock FIFO according to the four clocks provided by the clock module, thereby realizing the synchronous operation of all tiles; The compensation calculation unit calculates the DAC channel delay between N multi-channel signal acquisition and transmission boards, and feeds back the delay value to the data compensation unit of each board, and the data compensation unit completes the relative delay compensation at the baseband data generation unit; The compensation calculation unit calculates the ADC channel delay between N multi-channel signal acquisition and transmission boards, and feeds the delay value back to the data compensation unit of each board, which completes the relative delay compensation at the baseband data receiving unit. 5. The synchronization method according to claim 3 is characterized in that the delay residual caused by the power division unit and the combining unit can be calibrated and compensated in advance. 6. The synchronization method according to claim 3 is characterized in that: the specific process of the compensation calculation unit performing the delay calculation and compensation of the DAC channels between the N multi-channel signal acquisition and transmission boards is as follows: Step 1: The compensation calculation unit outputs a trigger pulse to the data compensation unit of the multi-channel signal acquisition and sending card. Step 2 performs a delay operation in the data compensation unit, that is, the data generation time of the 2nd, 3rd...Nth blocks is delayed by 10*(N-1)ms respectively, and the data generation unit of each board only generates a 10ms data waveform, that is, the combining unit is time-division multiplexed. Step 3: The compensation calculation unit restores the waveform of the channel according to the data collected within 10 ms, and calculates the relative delay of other channels with reference to the first channel at a certain time point thereafter. Step 4 feeds back the relative delay value to the data compensation unit of each board, and the data compensation unit compensates for the relative delay at the baseband data generation location. 7. The synchronization method according to claim 3 is characterized in that: the specific process of the compensation calculation unit performing the delay calculation and compensation of the ADC channels between the N multi-channel signal acquisition and transmission boards is as follows: Step 1: The compensation calculation unit outputs a single-tone signal which is sent to the ADC through the power division unit output N channels to complete analog-to-digital conversion. Step 2: The data compensation unit extracts the cached data and sends it to the compensation calculation unit. Step 3: After the compensation calculation unit performs FFT conversion on the received data, it calculates the relative delays of other channels with the first channel as a reference. Step 4 feeds back the delay value to the data compensation unit of each board, which compensates for the relative delay at the baseband data receiving point, thereby completing the synchronization calibration of signals between N multi-channel signal acquisition and transmission boards.