CN117995131B - Display panel and driving method of display panel - Google Patents
Display panel and driving method of display panel Download PDFInfo
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- CN117995131B CN117995131B CN202410194877.2A CN202410194877A CN117995131B CN 117995131 B CN117995131 B CN 117995131B CN 202410194877 A CN202410194877 A CN 202410194877A CN 117995131 B CN117995131 B CN 117995131B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The application provides a display panel and a driving method of the display panel. According to the application, the switching circuit is arranged, so that a single cascade control signal output by each shift register unit is output as a driving cascade signal to drive the pixel units to display normal pictures, or the single cascade control signal is output as a black inserting cascade signal to drive the pixel units to display black pictures to realize black inserting display, and each shift register unit can realize normal display or black inserting display of the display panel.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a display panel and a driving method of the display panel.
Background
In order to solve the problem of smear phenomenon when the display panel switches dynamic pictures, black insertion (AFI technology for short, auto Frame Insertion) is generally performed in the display gap of a frame of picture to complete initialization before the display of the next frame of picture, reduce or eliminate the visual residue of human eyes on the display picture of the previous frame, thereby achieving the purposes of eliminating smear, improving dynamic definition, improving dynamic response and the like, and improving the dynamic display quality of LCD (Liquid CRYSTAL DISPLAY).
Currently, in a display device with high resolution and narrow frame, a GOA (Gate on Array) technology is generally adopted to realize in-plane line scanning driving. In the non-AFI technology, generally, left and right GOA units are adopted to drive in plane simultaneously, namely, the same row is provided with left and right GOA units to complete driving, and the driving modes are left and right complementarily, so that the driving capability is strong and the picture display is uniform. When the AFI technology is adopted, the left GOA is generally adopted as display driving, and the right GOA is adopted as black inserting driving, so that the AFI technology is generally single-drive and slightly worse than the non-AFI technology in driving capability.
Disclosure of Invention
The application mainly solves the technical problem of providing a display panel and a driving method of the display panel, and solves the problem of how to realize double driving of an AFI technology on the basis of a narrow frame in the prior art.
In order to solve the technical problems, a first technical scheme provided by the application is that a display panel is provided, wherein the display panel comprises:
The display device comprises a plurality of pixel units arranged in an array manner, wherein each pixel unit comprises a display switch and a black insertion switch;
two gate driving circuits, each gate driving circuit including a plurality of cascaded shift register units;
The switching circuit is used for outputting a single cascade control signal output by the corresponding shift register unit as a driving cascade signal or a black inserting cascade signal;
The black inserting cascade signal is used for controlling the black inserting switch in the pixel units of the corresponding row to be opened so as to drive the pixel units to display a black picture.
The display panel further comprises a plurality of gate line groups which are arranged at intervals, each gate line group is arranged corresponding to one row of pixel units and is electrically connected with the corresponding pixel units, each gate line group comprises a display gate line and a black inserting gate line which are arranged at intervals, the display gate line is electrically connected with the control end of a display switch in the corresponding row of pixel units to control the opening of the display switch, and the black inserting gate line is electrically connected with the control end of a black inserting switch in the corresponding row of pixel units to control the opening of the black inserting switch.
The switching circuit is used for transmitting a single cascade control signal output by the corresponding shift register unit to the display gate lines in the corresponding gate line group as a driving cascade signal, or is used for transmitting a single cascade control signal output by the corresponding shift register unit to the black inserting gate lines in the corresponding gate line group as a black inserting cascade signal.
Each grid driving circuit further comprises a first signal line and a second signal line, the switching circuit comprises a first switch and a second switch, the input end of the first switch is electrically connected with the output end of the corresponding shift register unit, the output end of the first switch is electrically connected with the corresponding display grid line, the control end of the first switch is electrically connected with the first signal line, the input end of the second switch is connected with the same output end of the corresponding shift register unit, the output end of the second switch is electrically connected with the corresponding black inserted grid line, and the control end of the second switch is electrically connected with the second signal line.
Each grid driving circuit further comprises a ground power supply signal line, the display panel further comprises reset switches, the reset switches are arranged in one-to-one correspondence with the shift register units, the input ends of the reset switches are electrically connected with the black inserted grid lines corresponding to the corresponding shift register units, the output ends of the reset switches are electrically connected with the ground power supply signal lines, the control ends of the reset switches are connected with the output ends of the m-stage shift register units after the corresponding shift register units, and m is a natural number greater than or equal to 1.
The cascade control signals output by the output ends of the same post-m-stage shift register units are used as reset signals of the current-stage shift register units and are used as control signals received by reset switches corresponding to the current-stage shift register units.
The display panel further comprises a plurality of data lines, the pixel unit further comprises a pixel capacitor, a pixel electrode and a public electrode, the input end of the display switch is electrically connected with the data lines, the output end of the display switch is electrically connected with one end of the pixel capacitor through the pixel electrode, the other end of the pixel capacitor is electrically connected with the public electrode, the input end of the black inserting switch is electrically connected with the pixel electrode, and the output end of the black inserting switch is connected with the public electrode.
The display panel comprises a normal display mode and a black insertion display mode;
When the display panel is in a normal display mode, at least one gate driving circuit works, and all switching circuits corresponding to the shift register units in the gate driving circuit output cascade control signals as driving cascade signals;
When the display panel is in the black insertion display mode, the two gate driving circuits work, the switch circuits corresponding to all the shift register units in one gate driving circuit output cascade control signals as driving cascade signals, and the switch circuits corresponding to all the shift register units in the other gate driving circuit output cascade control signals as black insertion cascade signals, wherein the driving time sequences of the two gate driving circuits are different by at least half a frame in one frame of picture.
In order to solve the technical problems, a second technical scheme provided by the application is to provide a driving method of a display panel, which is used for driving the display panel, wherein the driving method comprises the following steps:
controlling the shift register unit to output a cascade control signal;
the switching circuit corresponding to the shift register unit is controlled to output the cascade control signal as a driving cascade signal or a black insertion cascade signal.
The display panel comprises a normal display mode and a black insertion display mode;
The switching circuit for controlling the shift register unit to output the cascade control signal as a driving cascade signal or a black insertion cascade signal includes:
when the display panel is in the black insertion display mode, the switch circuits corresponding to all the shift register units in one gate driving circuit are controlled to output cascade control signals as driving cascade signals, and the switch circuits corresponding to all the shift register units in the other gate driving circuit are controlled to output cascade control signals as black insertion cascade signals;
When the display panel is in a normal display mode, at least one gate driving circuit works, and the control switch circuit outputs cascade control signals as driving cascade signals.
The application has the beneficial effects that the display panel and the driving method of the display panel are different from the prior art, and the display panel comprises a plurality of pixel units, two grid driving circuits and a switch circuit which are arranged in an array. Each pixel unit includes a display switch and a black insertion switch. The gate driving circuit includes a plurality of cascaded shift register units. The switch circuits are arranged in one-to-one correspondence with the shift register units, and are arranged in correspondence with and electrically connected with at least one row of pixel units. The switch circuit is used for outputting a single cascade control signal output by the corresponding shift register unit as a driving cascade signal or a black inserting cascade signal. The driving cascade signal is used for controlling the display switch in the pixel unit in the corresponding row to be turned on so as to drive the pixel unit to display a normal picture. The black inserting cascade signal is used for controlling the black inserting switch in the pixel unit of the corresponding row to be turned on so as to drive the pixel unit to display a black picture. According to the application, the switching circuit is arranged, so that a single cascade control signal output by each shift register unit is output as a driving cascade signal to drive the pixel units to display normal pictures, or the single cascade control signal is output as a black inserting cascade signal to drive the pixel units to display black pictures to realize black inserting display, and each shift register unit can realize normal display or black inserting display of the display panel.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without any inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a pixel unit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an equivalent circuit structure of an embodiment of a pixel unit according to the present application;
FIG. 4 is a timing difference diagram of two embodiments of the gate driving circuits according to the present application;
FIG. 5 is a timing difference diagram of another embodiment of two gate driving circuits according to the present application;
FIG. 6 is a schematic diagram showing a mode switching of a display panel according to the present application;
fig. 7 is a flowchart illustrating an embodiment of a driving method of a display panel according to the present application.
Reference numerals illustrate:
10. Pixel unit, 11, display switch, 12, black insertion switch, 13, pixel electrode, 14, common electrode, C, pixel capacitor, 20, gate driving circuit, 21/SW1/SW3, first signal line, 22/SW2/SW4, second signal line, VSS, ground power signal line, STV1/STV2, frame start signal, CK, clock signal line, 20A, first Gate driving circuit, 20B, second Gate driving circuit, GOA/Gn/Gn+1/Gn+m/Gn+1+m, shift register unit, 30, gate line group, gate1, display Gate line, gate2, black insertion Gate line, 40, switching circuit, 41/T1/T4, first switch, 42/T2/T5, second switch, 50/T3/T6, reset switch, data line, 101, display area, 102, frame area, T1, display phase, T2, black insertion phase.
Detailed Description
The following describes embodiments of the present application in detail with reference to the drawings.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the present application.
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms "first," "second," "third," and the like in this disclosure are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. All directional indications (such as up, down, left, right, front, rear) in embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular pose (as shown in the drawings), and if the particular pose changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1 to 3, fig. 1 is a schematic structural diagram of an embodiment of a display panel provided by the present application, fig. 2 is a schematic structural diagram of an embodiment of a pixel unit provided by the present application, and fig. 3 is a schematic structural diagram of an equivalent circuit of an embodiment of a pixel unit provided by the present application.
The application provides a display panel, which comprises a plurality of pixel units 10, two grid driving circuits 20 and a switch circuit 40 which are arranged in an array mode. Each pixel unit 10 includes a display switch 11 and a black insertion switch 12. The gate driving circuit 20 includes a plurality of cascaded shift register units GOA. The switch circuits 40 are disposed in one-to-one correspondence with the shift register units GOA, and are disposed in correspondence with and electrically connected to at least one row of the pixel units 10. The switching circuit 40 is configured to output a single cascade control signal corresponding to the output of the shift register unit GOA as a driving cascade signal or a black insertion cascade signal. The driving cascade signal is used for controlling the display switch 11 in the pixel unit 10 in the corresponding row to be turned on so as to drive the pixel unit 10 to display a normal picture. The black inserting cascade signal is used for controlling the black inserting switch 12 in the pixel unit 10 of the corresponding row to be turned on so as to drive the pixel unit 10 to display a black picture.
In the application, a single cascade control signal output by each shift register unit GOA is output as a driving cascade signal to drive the pixel units 10 to display normal pictures, or is output as a black inserting cascade signal to drive the pixel units 10 to display black pictures to realize black inserting display, so that each shift register unit GOA can realize normal display or black inserting display of a display panel, and in addition, two grid driving circuits 20 are arranged, so that the display panel can realize black inserting display besides double-side driving or single-side driving of each row of pixel units 10, thereby realizing diversification of display modes of the display panel.
The display panel has a display area 101 and a bezel area 102 located at a side of the display area 101. In the application, the display panel is a liquid crystal panel.
The display panel further includes a plurality of Data lines Data. The pixel unit 10 further includes a pixel capacitor C, a pixel electrode 13, and a common electrode 14, wherein an input end of the display switch 11 is electrically connected to the Data line Data, an output end of the display switch 11 is electrically connected to one end of the pixel capacitor C through the pixel electrode 13, and the other end of the pixel capacitor C is electrically connected to the common electrode 14. The input terminal of the black insertion switch 12 is electrically connected to the pixel electrode 13, and the output terminal of the black insertion switch 12 is electrically connected to the common electrode 14. The input terminal of the black insertion switch 12 is electrically connected between the pixel capacitor C and the pixel electrode 13.
Liquid crystal molecules are disposed between each pixel electrode 13 and each common electrode 14, and when a potential difference exists between the pixel electrode 13 and the corresponding common electrode 14, an electric field is generated, and the electric field drives the corresponding liquid crystal molecules to deflect, so that the pixel unit 10 displays a normal picture. When the potential between the pixel electrode 13 and the corresponding common electrode 14 is the same, the corresponding liquid crystal molecules are not deflected, and the pixel unit 10 displays a black picture.
Specifically, when the display switch 11 is turned on and the black insertion switch 12 is turned off, there is a potential difference between the common electrode 14 and the pixel electrode 13 to drive the pixel unit 10 to display a normal picture. When the display switch 11 is turned off and the black insertion switch 12 is turned on, the potential between the common electrode 14 and the pixel electrode 13 is the same to drive the pixel unit 10 to display a black picture.
It should be noted that, the display switch 11 and the black insertion switch 12 in each pixel unit 10 cannot be turned on at the same time, so as to avoid affecting the normal display of the pixel unit 10.
The two gate driving circuits 20 are respectively disposed in the frame region 102 and disposed on opposite sides of the display region 101. Each gate driving circuit 20 includes a plurality of cascaded shift register units GOA. The specific structure of the shift register unit GOA is not limited here, and is selected according to actual requirements. Each shift register unit GOA is disposed and coupled to at least one row of pixel units 10 to drive the pixel units 10 of the corresponding row to display. That is, each shift register unit GOA may drive one row of pixel units 10, or may drive multiple rows of pixel units 10, which is not limited herein, and may be selected according to practical requirements.
In the present embodiment, the structures of the two gate driving circuits 20 are the same. Each shift register unit GOA drives a row of pixel cells 10.
In other embodiments, the structures of the two gate driving circuits 20 may be different.
The display panel further includes a plurality of gate line groups 30 disposed at intervals. Each gate line group 30 is disposed corresponding to and electrically connected to a row of pixel cells 10. The Gate line group 30 includes one display Gate line Gate1 and one black inserted Gate line Gate2 arranged at intervals. The display Gate line Gate1 is electrically connected to the control terminal of the display switch 11 in the pixel unit 10 of the corresponding row to control the turn-on of the display switch 11, and the black insertion Gate line Gate2 is electrically connected to the control terminal of the black insertion switch 12 in the pixel unit 10 of the corresponding row to control the turn-on of the black insertion switch 12.
Specifically, the extending direction of the display Gate line Gate1 is the row direction of the pixel unit 10. The display Gate lines Gate1 and the black inserted Gate lines Gate2 in the Gate line group 30 are insulated and arranged at intervals, so as to avoid the short circuit connection of the display Gate lines Gate1 and the black inserted Gate lines Gate2, which affects the display of the pixel unit 10.
In the present embodiment, the black inserted Gate line Gate2 and the display Gate line Gate1 in the Gate line group 30 are disposed in parallel, and the black inserted Gate line Gate2 and the display Gate line Gate1 are respectively located at two opposite sides of the pixel units 10 in the corresponding row. That is, the extending direction of the Gate line group 30 is parallel to the extending direction of the display Gate line Gate 1.
It should be understood that in other embodiments, the black inserted Gate line Gate2 and the display Gate line Gate1 in the Gate line group 30 may be located on the same side of the pixel units 10 in the corresponding row.
The two Gate driving circuits 20 are respectively located at opposite sides of the Gate line group 30 along the extending direction of the display Gate line Gate 1. One of the two gate driving circuits 20 is coupled to one end of the gate line group 30 and the other is coupled to the other end of the gate line group 30, so that the two gate driving circuits 20 can simultaneously drive one row of the pixel units 10.
The switch circuit 40 is electrically connected between the corresponding shift register unit GOA and the corresponding gate line group 30. That is, one end of the switching circuit 40 is connected to the shift register unit GOA, and the other end is electrically connected to the gate line group 30 to transmit the cascade control signal outputted from the shift register unit GOA to the gate line group 30, thereby driving the pixel units 10 in the corresponding row to display.
Further, the switching circuit 40 is used to transmit the single cascade control signal output by the corresponding shift register unit GOA as a driving cascade signal to the display Gate line Gate1 in the corresponding Gate line group 30, or the switching circuit 40 is used to transmit the single cascade control signal output by the corresponding shift register unit GOA as a black inserting cascade signal to the black inserting Gate line Gate2 in the corresponding Gate line group 30.
It may be understood that the switch circuit 40 may conduct between the output terminal of the shift register unit GOA and the corresponding display Gate line Gate1, so that the single cascade control signal outputted by the shift register unit GOA is transmitted to the display Gate line Gate1 as a driving cascade signal to drive the pixel unit 10 connected to the display Gate line Gate1 to display a normal picture, or the switch circuit 40 may conduct between the output terminal of the shift register unit GOA and the corresponding black insertion Gate line Gate2, so that the single cascade control signal outputted by the shift register unit GOA is transmitted to the black insertion Gate line Gate2 as a black insertion cascade signal to drive the pixel unit 10 connected to the black insertion Gate line Gate2 to display a black picture. That is, the cascade control signal output by the shift register unit GOA in the present application is a driving cascade signal or a black insertion cascade signal. One switching circuit 40 cannot output the driving cascade signal and the black insertion cascade signal at the same time, and can selectively output only a single cascade control signal output from a single shift register unit GOA as the driving cascade signal or the black insertion cascade signal.
In the present application, the types of signals output from the switch circuits 40 corresponding to the shift register units GOA in the same gate driving circuit 20 are the same. Specifically, the switch circuits 40 corresponding to the shift register units GOA in the same gate driving circuit 20 all output driving cascade signals or all output black insertion cascade signals.
Each gate driving circuit 20 further includes a first signal line 21 and a second signal line 22. The switching circuit 40 includes a first switch 41 and a second switch 42, an input terminal of the first switch 41 is electrically connected to an output terminal of the corresponding shift register unit GOA, an output terminal of the first switch 41 is electrically connected to the corresponding display Gate line Gate1, and a control terminal of the first switch 41 is electrically connected to the first signal line 21. The input terminal of the second switch 42 is connected to the same output terminal of the corresponding shift register unit GOA as the input terminal of the first switch 41, the output terminal of the second switch 42 is electrically connected to the corresponding black inserted Gate line Gate2, and the control terminal of the second switch 42 is electrically connected to the second signal line 22. That is, the first signal line 21 is used for controlling the on and off of the first switch 41, and the second signal line 22 is used for controlling the on and off of the second switch 42. The first switch 41 is used for switching on and off between the output terminal of the shift register unit GOA and the display Gate line Gate 1. The second switch 42 is used for switching on and off between the output terminal of the shift register unit GOA and the black inserted Gate line Gate 2.
In this embodiment, the first switch 41 and the second switch 42 are both transistors, and the transistors of the first switch 41 and the second switch 42 are the same type and are both N-type transistors.
In other embodiments, the first switch 41 and the second switch 42 may be other types of transistors.
The first signal line 21 and the second signal line 22 are independently controlled. The driving timing of the first signal line 21 and the driving timing of the second signal line 22 do not overlap, so as to avoid the influence on the normal display of the pixel unit 10 when the display switch 11 and the black insertion switch 12 are turned on simultaneously.
Each gate driving circuit 20 further includes at least one clock signal line CK, the number of which is not limited here, and is selected according to the actual structure of the gate driving circuit 20.
The display panel includes a normal display mode and a black insertion display mode. When the display panel is in the normal display mode, at least one gate driving circuit 20 is operated, and the switching circuits 40 corresponding to all the shift register units GOA in the gate driving circuit 20 output the cascade control signals as driving cascade signals. That is, when the display panel is in the normal display mode, one gate driving circuit 20 operates to drive each row of the pixel units 10 on one side, and when two gate driving circuits 20 operate simultaneously, each row of the pixel units 10 is driven on both sides. Compared with the single-side driving, the driving capability of the pixel unit 10 can be improved, and the picture display is more uniform. Meanwhile, when the gate driving circuit 20 on one side is abnormal, the gate driving circuit 20 on the other side can be adopted to work so as to improve the fault tolerance of the gate driving circuit 20 and the yield and the service life of the display panel.
When the display panel is in the black insertion display mode, the two gate driving circuits 20 are operated, the switch circuits 40 corresponding to all the shift register units GOA in one gate driving circuit 20 output the cascade control signals as driving cascade signals, and the switch circuits 40 corresponding to all the shift register units GOA in the other gate driving circuit 20 output the cascade control signals as black insertion cascade signals, wherein the driving timings of the two gate driving circuits 20 differ by at least half a frame within one frame. That is, one gate driving circuit 20 is used to drive each row of the pixel units 10 to display a normal picture, and the other gate driving circuit 20 is used as a black inserting circuit to drive each row of the pixel units 10 to display a black picture. In one frame, the driving timings of the frame start signals of the two gate driving circuits 20 are different by at least half a frame.
Compared with the prior art, the display panel provided by the application has multiple display modes by the matching use of the switch circuit 40 and the gate driving circuit 20, so that not only can single-drive and double-drive be realized, but also black insertion display can be realized, and the mode switching can be performed according to the requirements of customers or the display requirements, thereby improving the use feeling of customers. Secondly, the application is suitable for the black insertion mode of the display panel with high resolution without increasing the number of the grid driving circuits 20 under the condition of being compatible with the normal display mode and the black insertion display mode.
Further, each Gate driving circuit 20 further includes a ground power supply signal line VSS, the display panel further includes a reset switch 50, the reset switch 50 is disposed in one-to-one correspondence with the shift register units GOA, an input end of the reset switch 50 is electrically connected to the black inserted Gate line Gate2 corresponding to the corresponding shift register unit GOA, an output end of the reset switch 50 is electrically connected to the ground power supply signal line VSS, and a control end of the reset switch 50 is connected to an output end of the shift register unit GOA of the next m stages of the corresponding shift register unit GOA. Wherein m is a natural number greater than or equal to 1.
The reset switch 50 is used for pulling the potential of the black inserted Gate line Gate2 to a low potential after the black inserted display is finished in the black inserted display mode, so as to turn off the black inserted switch 12 connected with the black inserted Gate line Gate2, thereby avoiding the incomplete influence on the normal display of the pixel unit 10 due to the turn-off of the black inserted switch 12. Meanwhile, in the normal display mode, the situation that the electric potential of the corresponding black inserted Gate line Gate2 is pulled up due to the leakage of the second switch 42 in the switch circuit 40, which causes the black inserted switch 12 to be turned on and affects the display of the pixel unit 10 to display a normal picture can be avoided.
In the present application, in the black insertion display mode, the driving timings of the frame start signals of the two gate driving circuits 20 are set to be different by at least half a frame in a frame, so that the reset switches 50 and the black insertion switches 12 corresponding to the pixel units 10 in the same row are not turned on at the same time, thereby affecting the display of the black image by the pixel units 10. Specifically, when the black inserting switch 12 in the pixel unit 10 is turned on, the reset switch 50 corresponding to the row of pixel units 10 is turned on at the same time, the potential of the black inserting Gate line Gate2 corresponding to the row of pixel units 10 is pulled down, so that the potential of the black inserting Gate line Gate2 is lower than the Gate threshold voltage of the black inserting switch 12, and the potential of the black inserting Gate line Gate2 is insufficient to turn on the black inserting switch 12, which results in that the pixel unit 10 cannot normally display a black picture and affects the black inserting display of the display panel.
It should be noted that, in a frame of picture, the driving timing of the reset signal of the current stage shift register unit GOA and the driving timing of the current stage shift register unit GOA are both located in the first half frame of the current detection picture. The driving timings of the frame start signals of the two gate driving circuits 20 are set to differ by at least half a frame in the black insertion display mode, so that the driving timings of the gate driving circuits 20 used as the black insertion circuits are located in the second half of the current frame, that is, when the black insertion switch 12 in the pixel unit 10 is turned on, the reset switch 50 corresponding to the row of pixel units 10 is not turned on at the same time.
The control terminal of the reset switch 50 is connected to the output terminal of the m-th stage shift register unit GOA of the corresponding shift register unit GOA, and it can be understood that the control terminal of the reset switch 50 corresponding to the n-th stage shift register unit GOA is connected to the output terminal of the n+m-th stage shift register unit GOA. Wherein n is a natural number greater than or equal to 1.
The cascade control signal output by the h-th stage shift register unit GOA serves as a reset signal of the current stage shift register unit GOA, and specifically, the cascade control signal output by the n+h-th stage shift register unit GOA serves as a reset signal of the n-th stage shift register unit GOA. Wherein h is a natural number greater than or equal to 1. The relation between h and m is not limited, and is selected according to actual requirements.
In this embodiment, the cascade control signal output from the output terminal of the same last m stage shift register unit GOA is used as the reset signal of the current stage shift register unit GOA and as the control signal received by the reset switch 50 corresponding to the current stage shift register unit GOA.
It can be understood that the cascade control signal output from the output terminal of the n+m stage shift register unit GOA serves as a reset signal of the n stage shift register unit GOA and as a control signal received by the reset switch 50 corresponding to the n stage shift register unit GOA. I.e. h is equal to m.
In this embodiment, the reset signal of a certain stage of the shift register unit GOA is multiplexed into the control signal of the reset switch 50 corresponding to the stage of the shift register unit GOA, so that the wiring of the gate driving circuit 20 can be reduced, which is beneficial to the design of a narrow frame.
It should be noted that, the reset signal of the shift register unit GOA at the last stage of the present application is a frame start signal.
In one embodiment, the two gate driving circuits 20 are respectively defined as a first gate driving circuit 20A and a second gate driving circuit 20B, wherein the first gate driving circuit 20A is disposed in the frame area 102 on the left side of the display area 101, and the second gate driving circuit 20B is disposed in the frame area 102 on the right side of the display area 101. The first switch 41 and the second switch 42 corresponding to the shift register unit GOA in the first gate driving circuit 20A are denoted as T1 and T2, respectively, and the reset switch 50 corresponding to the shift register unit GOA in the first gate driving circuit 20A is denoted as T3. The first switch 41 and the second switch 42 corresponding to the shift register unit GOA in the second gate driving circuit 20B are denoted as T4 and T5, respectively, and the reset switch 50 corresponding to the shift register unit GOA in the second gate driving circuit 20B is denoted as T6.
The first signal line 21 and the second signal line 22 in the first gate driving circuit 20A are denoted as SW1 and SW2, respectively, and the first signal line 21 and the second signal line 22 in the second gate driving circuit 20B are denoted as SW3 and SW4, respectively. The frame start signal in the first gate driving circuit 20A is denoted as STV1, and the frame start signal in the second gate driving circuit 20B is denoted as STV2.
The n-th stage shift register unit GOA is denoted Gn, the n+1-th stage shift register unit GOA is denoted gn+1, the n+m-th stage shift register unit GOA is denoted gn+m, and the n+1+m-th stage shift register unit GOA is denoted gn+1+m.
Referring to fig. 1 to 6, fig. 4 is a timing difference schematic diagram of one embodiment of two gate driving circuits according to the present application, fig. 5 is a timing difference schematic diagram of another embodiment of two gate driving circuits according to the present application, and fig. 6 is a mode switching schematic diagram of a display panel according to the present application.
The normal display mode includes a dual-drive mode, a left single-drive mode, and a right single-drive mode.
When the display panel is in the dual driving mode, the first gate driving circuit 20A and the second gate driving circuit 20B operate simultaneously, i.e., the driving timings of the frame start signal STV1 of the first gate driving circuit 20A and the frame start signal STV2 of the second gate driving circuit 20B are the same. All the switch circuits 40 output driving cascade signals according to the driving timing of the gate driving circuit 20 to control the display switch 11 to be turned on. Specifically, the current stage shift register unit GOA outputs the cascade control signal, SW1 and SW3 both provide high potential, SW2 and SW4 both provide low potential, T1 and T4 are on, T2 and T5 are off, and the current stage shift register unit GOA in the first gate driving circuit 20A and the current stage shift register unit GOA in the second gate driving circuit 20B simultaneously drive the corresponding row of pixel units 10 to display a normal picture. In this mode, the display panel has good driving capability and display uniformity.
When the display panel is in the left single-drive mode, the first gate driving circuit 20A is operated, and the second gate driving circuit 20B is not operated. The switching circuits 40 corresponding to the shift register units GOA in the first gate driving circuit 20A each output a driving cascade signal to control the display switch 11 to be turned on. All the black insertion switches 12 are turned off. Specifically, the shift register unit GOA of the current stage in the first gate driving circuit 20A outputs the cascade control signal, SW1 provides a high potential, SW2, SW3 and SW4 each provide a low potential, T1 is turned on, T2, T4 and T5 are turned off, and the shift register unit GOA of the current stage in the first gate driving circuit 20A drives the corresponding row of pixel units 10 to display a normal picture.
When the display panel is in the right single-drive mode, the first gate driving circuit 20A does not operate, and the second gate driving circuit 20B operates. The switching circuits 40 corresponding to the shift register units GOA in the second gate driving circuit 20B each output a driving cascade signal to control the display switch 11 to be turned on. All the black insertion switches 12 are turned off. Specifically, the shift register unit GOA of the current stage in the second gate driving circuit 20B outputs the cascade control signal, SW3 provides a high potential, SW1, SW2 and SW4 each provide a low potential, T4 is on, T1, T2 and T5 are off, and the shift register unit GOA of the current stage in the second gate driving circuit 20B drives the corresponding row of pixel units 10 to display a normal picture.
The black insertion display mode includes a first black insertion mode and a second black insertion mode. The display stage t1 and the black insertion stage t2 are sequentially included in one frame of picture.
When the display panel is in the first black insertion mode, the first gate driving circuit 20A and the second gate driving circuit 20B operate. The switch circuits 40 corresponding to the shift register units GOA in the first gate driving circuit 20A each output a driving cascade signal to control the display switch 11 to be turned on, and the switch circuits 40 corresponding to the shift register units GOA in the second gate driving circuit 20B each output a black insertion cascade signal to control the black insertion switch 12 to be turned on. That is, the first gate driving circuit 20A is used to drive the pixel cells 10 of the corresponding row to display a normal screen, and the second gate driving circuit 20B is used as a black insertion circuit to drive the pixel cells 10 of the corresponding row to display a black screen. Specifically, in the display stage T1 within one frame, the shift register unit GOA of the current stage in the first gate driving circuit 20A outputs the cascade control signal, SW1 provides a high potential, SW2, SW3 and SW4 each provide a low potential, T1 is turned on, T2, T4 and T5 are turned off, and the shift register unit GOA of the current stage in the first gate driving circuit 20A drives the pixel unit 10 of the corresponding row to display a normal picture. In the black insertion stage T2 in the detection frame, the current stage shift register unit GOA in the second gate driving circuit 20B outputs a cascade control signal, SW4 provides a high voltage, SW1, SW2 and SW3 provide low voltages, T5 is turned on, T1, T2 and T4 are turned off, and the current stage shift register unit GOA in the second gate driving circuit 20B drives the corresponding row of pixel units 10 to display a black frame. In one frame, the driving timing of the second gate driving circuit 20B is delayed by at least half a frame compared to the timing of the first gate driving circuit 20A, that is, as shown in fig. 4, the driving timing of the frame start signal STV2 of the second gate driving circuit 20B is delayed by at least half a frame compared to the driving timing of the frame start signal STV1 of the first gate driving circuit 20A, so that the reset switches 50 corresponding to the pixel units 10 in the same row are not turned on simultaneously with the black insertion switch 12, thereby affecting the pixel units 10 to display black images.
When the display panel is in the second black insertion mode, the first gate driving circuit 20A and the second gate driving circuit 20B operate. The switch circuits 40 corresponding to the shift register units GOA in the first gate driving circuit 20A each output a black insertion cascade signal to control the black insertion switch 12 to be turned on, and the switch circuits 40 corresponding to the shift register units GOA in the second gate driving circuit 20B each output a driving cascade signal to control the display switch 11 to be turned on. That is, the first gate driving circuit 20A is used as a black insertion circuit for driving the pixel units 10 of the corresponding row to display a black screen. The second gate driving circuit 20B is used to drive the pixel units 10 of the corresponding row to display a normal picture. Specifically, in the display stage T1 within one frame, the shift register unit GOA of the current stage in the second gate driving circuit 20B outputs the cascade control signal, SW3 provides a high potential, SW1, SW2 and SW4 each provide a low potential, T4 is on, T1, T2 and T5 are off, and the shift register unit GOA of the current stage in the second gate driving circuit 20B drives the pixel unit 10 of the corresponding row to display a normal picture. In the black insertion stage T2 in the detection frame, the shift register unit GOA of the current stage in the first gate driving circuit 20A outputs a cascade control signal, SW2 provides a high voltage, SW1, SW3 and SW4 provide low voltages, T2 is turned on, T1, T4 and T5 are turned off, and the shift register unit GOA of the current stage in the first gate driving circuit 20A drives the pixel units 10 of the corresponding row to display a black frame. In one frame, the driving timing of the first gate driving circuit 20A is delayed by at least half a frame compared to the timing of the second gate driving circuit 20B, that is, as shown in fig. 5, the driving timing of the frame start signal STV1 of the first gate driving circuit 20A is delayed by at least half a frame compared to the driving timing of the frame start signal STV2 of the second gate driving circuit 20B, so that the reset switches 50 corresponding to the pixel units 10 in the same row are not turned on simultaneously with the black insertion switch 12, thereby affecting the pixel units 10 to display black images.
Referring to fig. 7, fig. 7 is a flowchart illustrating an embodiment of a driving method of a display panel according to the present application.
The application provides a driving method of a display panel. The driving method of the display panel is used for driving the display panel. The driving method of the display panel specifically comprises the following steps:
And S10, controlling the shift register unit to output a cascade control signal.
Specifically, the shift register unit is controlled to output a cascade control signal according to the driving timing of the gate driving circuit.
In one embodiment, the step of controlling the shift register unit to output the cascade control signal specifically includes:
and controlling one gate driving circuit in the two gate driving circuits to work, and controlling the corresponding shift register unit to output a cascade control signal according to the driving time sequence of the gate driving circuit.
In another embodiment, the step of controlling the shift register unit to output the cascade control signal specifically includes:
and controlling the two gate driving circuits to work simultaneously, and controlling the shift register unit to output cascade control signals according to the driving time sequence of the gate driving circuits.
And S20, controlling a switching circuit corresponding to the shift register unit to output the cascade control signal as a driving cascade signal or a black insertion cascade signal.
Specifically, the switching circuit corresponding to the shift register unit is controlled to output the cascade control signal as a driving cascade signal or a black insertion cascade signal according to the driving order of the shift register unit and the mode of the display panel.
The display panel includes a normal display mode and a black insertion display mode.
Step S20, controlling a switch circuit corresponding to the shift register unit to output a cascade control signal as a driving cascade signal or a black insertion cascade signal, comprising the following steps:
when the display panel is in the black insertion display mode, the switch circuits corresponding to all the shift register units in one gate driving circuit are controlled to output cascade control signals as driving cascade signals, and the switch circuits corresponding to all the shift register units in the other gate driving circuit are controlled to output cascade control signals as black insertion cascade signals;
When the display panel is in a normal display mode, at least one gate driving circuit works, and the control switch circuit outputs cascade control signals as driving cascade signals.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The foregoing is only the embodiments of the present application, and therefore, the patent protection scope of the present application is not limited thereto, and all equivalent structures or equivalent flow changes made by the content of the present specification and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the patent protection scope of the present application.
Claims (7)
1. A display panel, comprising:
The display device comprises a plurality of pixel units arranged in an array manner, wherein each pixel unit comprises a display switch and a black insertion switch;
two gate driving circuits, each of which includes a plurality of cascaded shift register units;
the switching circuit is used for outputting a single cascade control signal output by the corresponding shift register unit as a driving cascade signal or a black inserting cascade signal;
The black inserting cascade signal is used for controlling the black inserting switch in the pixel units of the corresponding row to be turned on so as to drive the pixel units to display a black picture;
The display panel further comprises a plurality of gate line groups which are arranged at intervals, wherein each gate line group is correspondingly arranged with one row of pixel units and is electrically connected with the corresponding pixel units, each gate line group comprises a display gate line and a black inserting gate line which are arranged at intervals, each display gate line is electrically connected with a control end of a display switch in the corresponding row of pixel units so as to control the opening of the display switch, and each black inserting gate line is electrically connected with a control end of a black inserting switch in the corresponding row of pixel units so as to control the opening of the black inserting switch;
The switching circuit is used for transmitting the single cascading control signal output by the corresponding shift register unit to the display gate line corresponding to the gate line group as the driving cascading signal, or transmitting the single cascading control signal output by the corresponding shift register unit to the black inserting gate line corresponding to the gate line group as the black inserting cascading signal;
Each grid driving circuit further comprises a first signal line and a second signal line, the switch circuit comprises a first switch and a second switch, the input end of the first switch is electrically connected with the output end of the corresponding shift register unit, the output end of the first switch is electrically connected with the corresponding display grid line, the control end of the first switch is electrically connected with the first signal line, the input end of the second switch is connected with the same output end of the corresponding shift register unit, the output end of the second switch is electrically connected with the corresponding black inserting grid line, and the control end of the second switch is electrically connected with the second signal line.
2. The display panel according to claim 1, wherein each of the gate driving circuits further includes a ground power supply signal line, the display panel further includes a reset switch provided in one-to-one correspondence with the shift register unit, an input terminal of the reset switch is electrically connected to the black inserted gate line corresponding to the shift register unit, an output terminal of the reset switch is electrically connected to the ground power supply signal line, and a control terminal of the reset switch is connected to an output terminal of the shift register unit of a latter m stages of the corresponding shift register unit, wherein m is a natural number greater than or equal to 1.
3. The display panel of claim 2, wherein the display panel comprises,
And the cascade control signals output by the output ends of the shift register units of the same post m stages are used as reset signals of the shift register units of the current stage and are used as control signals received by reset switches corresponding to the shift register units of the current stage.
4. The display panel according to claim 1, wherein the display panel further comprises a plurality of data lines, the pixel unit further comprises a pixel capacitor, a pixel electrode and a common electrode, the input end of the display switch is electrically connected with the data lines, the output end of the display switch is electrically connected with one end of the pixel capacitor through the pixel electrode, the other end of the pixel capacitor is electrically connected with the common electrode, the input end of the black insertion switch is electrically connected with the pixel electrode, and the output end of the black insertion switch is connected with the common electrode.
5. The display panel according to claim 1, wherein the two gate driving circuits have the same structure, and wherein the display panel includes a normal display mode and a black insertion display mode;
When the display panel is in the normal display mode, at least one gate driving circuit works, and all the switching circuits corresponding to the shift register units in the gate driving circuit output the cascade control signals as the driving cascade signals;
When the display panel is in a black insertion display mode, the two gate driving circuits work, the switch circuits corresponding to all the shift register units in one gate driving circuit output the cascade control signals as driving cascade signals, and the switch circuits corresponding to all the shift register units in the other gate driving circuit output the cascade control signals as the black insertion cascade signals, wherein the driving time sequences of the two gate driving circuits are different by at least half a frame in one frame picture.
6. A driving method of a display panel for driving the display panel according to any one of claims 1 to 5, comprising:
controlling the shift register unit to output a cascade control signal;
and controlling a switching circuit corresponding to the shift register unit to output the cascade control signal as a driving cascade signal or a black insertion cascade signal.
7. The driving method of a display panel according to claim 6, wherein the display panel includes a normal display mode and a black insertion display mode;
the controlling the switching circuit corresponding to the shift register unit to output the cascade control signal as a driving cascade signal or a black insertion cascade signal includes:
When the display panel is in the black insertion display mode, controlling the switch circuits corresponding to all the shift register units in one grid driving circuit to output the cascade control signals as driving cascade signals, and controlling the switch circuits corresponding to all the shift register units in the other grid driving circuit to output the cascade control signals as black insertion cascade signals;
When the display panel is in the normal display mode, at least one gate driving circuit works to control the switching circuit to output the cascade control signals as driving cascade signals.
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| CN108172182A (en) * | 2017-12-25 | 2018-06-15 | 昆山龙腾光电有限公司 | Black picture is inserted into circuit, display device and electronic equipment |
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| CN111210758B (en) * | 2020-02-28 | 2023-01-31 | 合肥鑫晟光电科技有限公司 | Grid driving circuit and display device |
| WO2021189492A1 (en) * | 2020-03-27 | 2021-09-30 | 京东方科技集团股份有限公司 | Gate drive circuit, driving method therefor, and display panel |
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