CN117977943B

CN117977943B - Fault-tolerant control method, system, device, equipment and medium for inverter

Info

Publication number: CN117977943B
Application number: CN202410393272.6A
Authority: CN
Inventors: 杨清; 陈东恩; 杨帆
Original assignee: Gree Electric Appliances Inc of Zhuhai
Current assignee: Gree Electric Appliances Inc of Zhuhai
Priority date: 2024-04-02
Filing date: 2024-04-02
Publication date: 2024-07-05
Anticipated expiration: 2044-04-02
Also published as: CN117977943A

Abstract

The application relates to a fault-tolerant control method, a system, a device, equipment and a medium of an inverter, wherein the fault-tolerant control method of the inverter comprises the following steps: switching on a boost circuit of the inverter based on a bridge arm fault signal of the inverter; the direct-current bus voltage of the inverter is improved through the booster circuit; performing topology reconstruction on the inverter according to the bridge arm fault signals, and acquiring initial compensation quantity after the topology reconstruction; determining voltage equalizing control compensation quantity corresponding to neutral point potential deviation of the inverter; calculating based on the initial compensation quantity and in combination with the equalizing control compensation quantity to obtain a target compensation quantity; the fault-tolerant control is carried out on the inverter according to the target compensation quantity, the driving signal of the inverter is obtained, and the neutral point potential offset suppression of the inverter after the fault is realized, so that the driving capability of the inverter after the fault can be effectively ensured, and the technical problem that the driving capability of the inverter cannot be ensured after the NPC three-level inverter fails in the prior art is solved.

Description

Fault-tolerant control method, system, device, equipment and medium for inverter

Technical Field

The present application relates to the technical field of inverters, and in particular, to a fault-tolerant control method, system, device, equipment and medium for an inverter.

Background

Along with the rapid development of power electronics technology, multi-level inverters are widely used, and three-level inverters have become the mainstream of multi-level inverters due to the advantages of stable performance, more flexible balance control over loss and the like.

For example, in the aspect of variable frequency drive control under the medium-high voltage level, the neutral point clamped (Neutral Point Clamped, NPC) type three-level inverter has certain advantages in the aspects of volume, manufacturing and maintenance cost, control difficulty and the like compared with a flying type and cascading type three-level inverter, and compared with a two-level inverter, the output is closer to a sine wave, the subsequent filtering difficulty is reduced, and the neutral point clamped (Neutral Point Clamped, NPC) type three-level inverter is also more suitable for application occasions of medium-high voltage.

However, the probability of the NPC type three-level inverter failure is also increased due to the increase of the switching power devices. How to ensure that the NPC three-level inverter can continuously and stably run after a certain phase bridge arm of the inverter has short circuit or open circuit fault is a technical problem to be solved at present.

Disclosure of Invention

The application provides a fault-tolerant control method, a fault-tolerant control system, a fault-tolerant control device, fault-tolerant control equipment and fault-tolerant control media for an inverter, and aims to solve the technical problem that the driving capability of the inverter cannot be guaranteed after an NPC three-level inverter fails in the prior art.

In a first aspect, the present application provides a fault-tolerant control method for an inverter, including: switching on a boost circuit of an inverter based on a bridge arm fault signal of the inverter; the direct-current bus voltage of the inverter is improved through the booster circuit; performing topology reconstruction on the inverter according to the bridge arm fault signals, and acquiring initial compensation quantity after the topology reconstruction; determining voltage equalizing control compensation quantity corresponding to the neutral point potential deviation of the inverter; calculating based on the initial compensation quantity and combining the voltage equalizing control compensation quantity to obtain a target compensation quantity; and performing fault-tolerant control on the inverter according to the target compensation quantity to obtain a driving signal of the inverter.

Optionally, the performing topology reconstruction on the inverter according to the bridge arm fault signal includes: determining a single-phase bridge arm corresponding to the bridge arm fault signal as a fault bridge arm; and cutting out the fault bridge arm from the topological structure of the inverter, and conducting a bidirectional thyristor correspondingly connected with the fault bridge arm, wherein one end of the bidirectional thyristor is electrically connected with the output end of the fault bridge arm and the bridge arm midpoint of the fault bridge arm, and the other end of the bidirectional thyristor is electrically connected with the direct-current side capacitor midpoint of the inverter.

Optionally, the midpoint potential deviation is a midpoint potential deviation of a dc bus of the inverter, and the obtaining the initial compensation amount after topology reconstruction includes: after the bidirectional thyristor is conducted, a first capacitor voltage and a second capacitor voltage are obtained, wherein the first capacitor voltage is the voltage of a first capacitor on the direct current side of the inverter, the second capacitor voltage is the voltage of a second capacitor on the direct current side of the inverter, the first end of the first capacitor is electrically connected with the first end of the fault bridge arm, the second end of the first capacitor is electrically connected with the first end of the second capacitor and the midpoint of the capacitor on the direct current side, and the second end of the second capacitor is electrically connected with the second end of the fault bridge arm; and calculating by adopting the first capacitance voltage and the second capacitance voltage to obtain the initial compensation quantity.

Optionally, determining the equalizing control compensation amount corresponding to the midpoint potential deviation of the inverter includes: obtaining the DC bus voltage of the inverter; combining the midpoint potential deviation according to the direct current bus voltage to synthesize a reference voltage vector so as to obtain a reference voltage vector; and determining the equalizing control compensation quantity by adopting the absolute value of the midpoint potential deviation based on the vector region where the reference voltage vector is located.

Optionally, calculating, based on the initial compensation amount and in combination with the equalizing control compensation amount, a target compensation amount includes: filtering the initial compensation quantity to obtain a direct current component in the initial compensation quantity; subtracting the direct current component from the initial compensation quantity to obtain a fault-tolerant compensation quantity; and adding the voltage equalizing control compensation quantity by using the fault-tolerant compensation quantity to obtain the target compensation quantity.

Optionally, the fault-tolerant control of the inverter according to the target compensation amount includes: based on the target compensation quantity, calculating by adopting a space vector pulse width modulation algorithm to obtain a pulse driving signal; and carrying out balance control on the midpoint voltage of the direct current bus of the inverter based on the pulse driving signal.

Optionally, after obtaining the bridge arm fault signal of the inverter, the fault-tolerant control method of the inverter further includes: switching on a boost circuit of the inverter; and the voltage boosting circuit is used for boosting the DC bus voltage of the inverter.

In a second aspect, the present application provides a fault tolerant control system for an inverter, comprising:

The fault signal module is used for conducting a boost circuit of the inverter based on a bridge arm fault signal of the inverter;

the direct-current boosting module is used for improving the direct-current bus voltage of the inverter through the boosting circuit;

The topology reconstruction acquisition module is used for carrying out topology reconstruction on the inverter according to the bridge arm fault signals and acquiring initial compensation quantity after the topology reconstruction;

The voltage-sharing compensation determining module is used for determining voltage-sharing control compensation quantity corresponding to the midpoint potential deviation of the inverter;

the target compensation calculation module is used for calculating based on the initial compensation quantity and combining the voltage equalizing control compensation quantity to obtain a target compensation quantity;

and the fault-tolerant control module is used for carrying out fault-tolerant control on the inverter according to the target compensation quantity to obtain a driving signal of the inverter.

In a third aspect, the present application provides a fault tolerant control apparatus for an inverter, including: fault tolerant control system and inverter;

the inverter comprises at least three level bridge arms and bidirectional thyristors which are connected with the single-phase bridge arms in a one-to-one correspondence manner; the inverter is used for disconnecting a fault bridge arm after the single-phase bridge arm fails and conducting the bidirectional thyristors correspondingly connected with the fault bridge arm;

The control system is used for conducting a boost circuit of the inverter based on a bridge arm fault signal of the inverter; the direct-current bus voltage of the inverter is improved through the booster circuit, and initial compensation quantity after topology reconstruction is obtained; determining voltage equalizing control compensation quantity corresponding to the neutral point potential deviation of the inverter; calculating based on the initial compensation quantity and combining the voltage equalizing control compensation quantity to obtain a target compensation quantity; and performing fault-tolerant control on the inverter according to the target compensation amount to obtain a driving signal of the inverter.

Optionally, the fault tolerant control system includes: and the output end of the boost circuit is electrically connected with the direct current bus of the inverter, and the boost circuit is used for improving the direct current bus voltage of the inverter.

Optionally, the output end of the boost circuit includes a first output end and a second output end, and the inverter further includes: the pressure equalizing control module; the first end of the voltage equalizing control module is electrically connected with the first output end of the boost circuit and the first end of each phase bridge arm of the inverter, the second end of the voltage equalizing control module is electrically connected with the first end of the bidirectional thyristor and the midpoint of each phase bridge arm of the inverter, and the third end of the voltage equalizing control module is electrically connected with the second output end of the boost circuit and the second end of each phase bridge arm of the inverter; the output end of each phase bridge arm is electrically connected with the second end of the bidirectional thyristor correspondingly connected with the bridge arm.

Optionally, the voltage equalizing control module includes: the first capacitor, the second capacitor, the first resistor and the second resistor; the first end of the first capacitor is electrically connected with the first output end of the boost circuit, the first end of the first resistor and the first end of each phase bridge arm of the inverter, and the second end of the first capacitor is electrically connected with the second end of the first resistor, the first end of the second capacitor, the first end of the second resistor, the first end of the triac and the midpoint of each phase bridge arm of the inverter;

The second end of the second capacitor is electrically connected with the second end of the second resistor, the second output end of the boost circuit and the second end of each phase bridge arm of the inverter.

Optionally, the boost circuit comprises a filter capacitor, a voltage stabilizing capacitor, a boost inductor, a diode and a power switch device; the first end of the filter capacitor is electrically connected with the first end of the power switch device and the anode of the diode through the boost inductor, the cathode of the diode is electrically connected with the first end of the voltage stabilizing capacitor and the first end of the voltage equalizing control module, and the second end of the filter capacitor is electrically connected with the second end of the power switch device, the second end of the voltage stabilizing capacitor and the third end of the voltage equalizing control module.

In a fourth aspect, the present application further provides a fault-tolerant control apparatus for an inverter, including: a memory for storing a computer program; a processor for executing a computer program stored in the memory, and when the computer program is executed, implementing the steps of the fault-tolerant control method of an inverter as described in any one of the first aspects.

In a fifth aspect, the present application also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the fault-tolerant control method of an inverter according to any of the first aspects.

Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages: according to the embodiment of the application, the boost circuit of the inverter is conducted based on the bridge arm fault signal of the inverter, so that the direct current bus voltage of the inverter is improved through the boost circuit, the inverter is subjected to topology reconstruction according to the bridge arm fault signal, the inverter topology reconstruction is realized, the initial compensation quantity after the topology reconstruction is obtained, the voltage-sharing control compensation quantity corresponding to the neutral point potential deviation of the inverter is determined, the calculation is performed based on the initial compensation quantity and the voltage-sharing control compensation quantity, and the target compensation quantity is obtained, so that the fault-tolerant control can be performed on the inverter according to the target compensation quantity, the neutral point potential deviation suppression of the inverter after the fault is realized, the driving capability of the inverter after the fault is ensured, and the continuous operation of the inverter after the fault is ensured, so that the technical problem caused by the fact that the driving capability of the inverter cannot be ensured after the NPC type three-level inverter fails in the prior art is solved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.

Fig. 1 is a schematic flow chart of steps of a fault-tolerant control method of an inverter according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a fault tolerant topology of an inverter according to an example of the present application;

Fig. 3 is a topology diagram of an inverter a-phase bridge arm after failure according to an example of the present application;

FIG. 4 is a schematic diagram of a fault tolerant topology space vector before A-phase failure according to an example of the present application;

FIG. 5 is a schematic diagram of a fault tolerant topology space vector after A-phase failure according to an example of the present application;

FIG. 6 is a schematic diagram showing the distribution of space voltage vectors as a function of voltage at the midpoint of a DC bus according to an example of the present application;

fig. 7 is a schematic diagram of a fault-tolerant control method of an inverter according to an example of the present application;

fig. 8 is a block diagram of a fault-tolerant control device for an inverter according to an embodiment of the present application;

Fig. 9 is a schematic circuit diagram of a fault-tolerant control device for an inverter according to an embodiment of the present application;

Fig. 10 is a flowchart illustrating steps of a fault-tolerant control method of an inverter according to an embodiment of the present application;

Fig. 11 is a block diagram of a fault-tolerant control system of an inverter according to an embodiment of the present application;

Fig. 12 is a schematic structural diagram of a fault-tolerant control device for an inverter according to an embodiment of the present application.

Wherein, C ₁ is the first capacitor, C ₂ is the second capacitor, C ₃ is the filter capacitor of the direct current input side, L is the boost inductor, S ₁ is the power switch device IGBT, D ₇ is the diode, and C ₄ is the voltage stabilizing capacitor. R ₁ is a first resistor, R ₂ is a second resistor, FU is a fast fuse, D ₁、D₂、D₃、D₄、D₅、D₆ is a clamping diode of an inverter, S _x,1、S_x,2、S_x,3、S_x,4 (x=a, b, c) is a power switching device, T ₁、T₂、T₃ is a bidirectional thyristor, V _dc is an inverter direct current side voltage, V _in is a direct current input side voltage, i _la, ilb, ilc are inverter output three-phase currents, up is a first capacitor voltage, un is a second capacitor voltage, and G (S) is a Bass Wo Lvbo device.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The following disclosure provides many different embodiments, or examples, for implementing different structures of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In order to ensure that the inverter can still continuously run after a short circuit or open circuit fault occurs in a certain phase bridge arm of the inverter and has certain driving output capacity, the application provides a fault-tolerant control method, a system, a device, equipment and a medium of the inverter.

It should be noted that, the inverter in the embodiment of the present application refers to a multi-level inverter, which has at least three level bridge arms, for example, may be an NPC type three-level inverter. The NPC type three-level inverter is a commonly used power conversion device that can convert direct current into three-phase alternating current.

Fig. 1 is a schematic flow chart of steps of a fault-tolerant control method of an inverter according to an embodiment of the present application. As shown in fig. 1, the fault-tolerant control method of an inverter provided by the embodiment of the application specifically includes the following steps:

step 110, switching on a boost circuit of an inverter based on a bridge arm fault signal of the inverter;

The bridge arm fault signal may refer to a signal generated by the inverter after a bridge arm of a certain phase fails. For example, taking an NPC-type three-level inverter as an example, when a single-phase bridge arm fault occurs in the NPC-type three-level inverter, a fault signal corresponding to the fault bridge arm can be obtained through fault detection, so as to be used as a bridge arm fault signal. After the bridge arm fault signal of the inverter is obtained, the boost circuit of the inverter may be turned on based on the bridge arm fault signal, so as to increase the dc bus voltage of the inverter through the boost circuit, that is, step 120 is performed.

Step 120, raising the dc bus voltage of the inverter by the boost circuit;

In order to ensure the driving capability of the inverter after the fault, in the step, a front-stage BOOST circuit of the inverter can be used as an upgrade circuit of the inverter, so that when a bridge arm fault signal of the inverter is obtained, the front-stage BOOST circuit of the inverter is conducted, and the amplitude of the residual alternative voltage vector of the inverter after the single-phase bridge arm fault is improved through the front-stage BOOST circuit of the inverter, so that the continuous and stable operation of the inverter after the fault is ensured.

130, Performing topology reconstruction on the inverter according to the bridge arm fault signals, and obtaining initial compensation quantity after the topology reconstruction;

In the step, a fault bridge arm of the inverter can be cut out, and a bidirectional thyristor correspondingly connected with the fault bridge arm can be conducted according to a bridge arm fault signal, so that fault phase output is directly connected with a direct current bus midpoint of the inverter, fault-tolerant topology reconstruction after fault is completed, then an initial compensation quantity can be obtained through sampling, for example, the direct current bus midpoint potential of the inverter can be sampled to obtain the initial compensation quantity, and the initial compensation quantity can be brought into reference voltage vector synthesis to realize space vector pulse width modulation.

Step 140, determining a voltage equalizing control compensation amount corresponding to the midpoint potential deviation of the inverter;

In the step, under ideal conditions, the midpoint potential is not offset any more in steady state, but the influence of the midpoint potential fluctuation of the direct current bus on the space vector voltage is considered, and the embodiment can determine the compensation quantity corresponding to the midpoint potential offset according to the midpoint offset condition of the direct current bus of the inverter to serve as the voltage equalizing control compensation quantity corresponding to the midpoint potential offset so as to compensate the midpoint potential offset by using the voltage equalizing control compensation quantity later, thereby realizing the midpoint potential offset suppression of the inverter after failure and improving engineering practicability.

Step 150, calculating based on the initial compensation quantity and combining the equalizing control compensation quantity to obtain a target compensation quantity;

In this step, the embodiment may use the initial compensation amount to subtract the dc component in the initial compensation amount to obtain a compensation amount without the dc component, and then use the compensation amount without the dc component to add the equalizing control compensation amount to obtain the target compensation amount, so as to bring the target compensation amount into the reference voltage vector synthesis, thereby implementing the midpoint potential offset suppression and pulse width modulation of the inverter after the fault.

And 160, performing fault-tolerant control on the inverter according to the target compensation quantity to obtain a driving signal of the inverter, and implementing the neutral point voltage balance control of the direct current bus and the driving of the inverter by a space vector pulse width modulation algorithm.

In the step, space vector pulse width modulation of the inverter can be performed according to the target compensation quantity, for example, a space vector pulse width modulation algorithm of the inverter can be adjusted according to the target compensation quantity so as to bring the target compensation quantity into reference voltage vector synthesis, thereby obtaining the acting time of each space voltage vector after final compensation of the space vector modulation, further obtaining a driving signal, and realizing neutral point voltage balance control of a direct current bus and driving of the inverter.

In summary, the embodiment of the application realizes the topology reconstruction of the inverter by acquiring the bridge arm fault signal of the inverter to reconstruct the inverter according to the bridge arm fault signal, acquires the initial compensation quantity after the topology reconstruction and determines the voltage-sharing control compensation quantity corresponding to the neutral point potential deviation of the inverter, and calculates the target compensation quantity by combining the voltage-sharing control compensation quantity based on the initial compensation quantity, thereby carrying out fault-tolerant control on the inverter according to the target compensation quantity, realizing the neutral point potential deviation inhibition of the inverter after the fault, ensuring the driving capability of the inverter after the fault, further ensuring the continuous operation of the inverter after the fault, and solving the technical problem that the driving capability of the inverter cannot be ensured after the NPC three-level inverter fails in the prior art.

In an alternative embodiment of the application, the space vector pulse width modulation algorithm of the inverter is adjusted according to the target compensation quantity, and meanwhile, a front-stage BOOST circuit of the inverter can be conducted, so that the amplitude of the residual alternative voltage vector of the inverter after the single-phase bridge arm faults is improved, the driving capability of the inverter after the faults is ensured, the fault-tolerant control of the inverter is further realized, and the continuous and stable operation of the inverter after the faults are ensured.

Therefore, the embodiment of the application realizes the topology reconstruction of the inverter by acquiring the bridge arm fault signal of the inverter to reconstruct the inverter according to the bridge arm fault signal, acquires the initial compensation quantity after the topology reconstruction and determines the voltage-sharing control compensation quantity corresponding to the neutral point potential deviation of the inverter, and calculates the target compensation quantity by combining the voltage-sharing control compensation quantity based on the initial compensation quantity, thereby carrying out fault-tolerant control according to the target compensation quantity, realizing the neutral point potential deviation suppression of the inverter after the fault, and simultaneously switching on the boost circuit of the inverter to improve the direct current bus voltage of the inverter after the fault through the boost circuit so as to further ensure the driving capability of the inverter after the fault.

In one embodiment of the application, the inverter comprises at least three level legs and bi-directional thyristors connected in one-to-one correspondence with the single phase legs. Specifically, the output end of each level bridge arm of the inverter is connected with the midpoint of the corresponding bridge arm, and is also connected with the midpoint of the direct-current side capacitor through the correspondingly connected bidirectional thyristor. For example, each phase output of the NPC three-level inverter is not only connected with the midpoint of the corresponding bridge arm, but also connected with the midpoint of the direct-current side capacitor through a bidirectional thyristor; after the single-phase bridge arm fails, the inverter topology reconstruction can be realized by disconnecting the failed bridge arm and conducting the bidirectional thyristors correspondingly connected with the failed bridge arm.

Optionally, the topology reconstruction of the inverter according to the bridge arm fault signal in the embodiment of the present application may specifically include: determining a single-phase bridge arm corresponding to the bridge arm fault signal as a fault bridge arm; and cutting the fault bridge arm from the topological structure of the inverter, and conducting the bidirectional thyristors correspondingly connected with the fault bridge arm. One end of the bidirectional thyristor is electrically connected with the output end of the fault bridge arm and the bridge arm midpoint of the fault bridge arm, and the other end of the bidirectional thyristor is electrically connected with the direct-current side capacitor midpoint of the inverter.

As an example of the present application, as shown in fig. 2, each phase leg of the NPC type three-level inverter has two fast fuses FU and four power switching devices (S _x,1、S_x,2、S_x,3、S_x,4, x=a, b, c), and each phase output is connected not only to the corresponding leg midpoint, but also to the dc side capacitor midpoint O through a triac (T ₁、T₂、T₃). Before the inverter fails, the bidirectional thyristor T ₁、T₂、T₃ is not conducted; when a single-phase bridge arm fault occurs, the fast fuse FU of the fault phase bridge arm is disconnected, the fault bridge arm is cut off, a fault signal generated after the fast fuse FU is disconnected can be used as a bridge arm fault signal, a bidirectional thyristor trigger signal on the fault phase is given based on the bridge arm fault signal, the fault phase bidirectional thyristor is conducted, the inverter fault phase output is directly connected with the midpoint of the direct current bus, and fault-tolerant topology reconstruction after the fault is completed. Because of the three-phase symmetry, taking the a-phase fault as an example, when the fast fuse FU on the a-phase is opened, the bidirectional thyristor T ₁ receives the driving signal of the driving circuit and is turned on, and the reconstruction topology after the fault is shown in fig. 3. The driving signal of the driving circuit is used as a trigger signal of the bidirectional thyristor to trigger the bidirectional thyristor to conduct, so that the voltage of the direct current bus can be adjusted according to the neutral point potential deviation later, and the output capacity of the inverter after the fault is improved.

In an embodiment of the present application, the midpoint potential deviation is a midpoint potential deviation of a dc bus of the inverter, and the obtaining an initial compensation amount after topology reconstruction specifically may include: after the bidirectional thyristor is conducted, a first capacitor voltage and a second capacitor voltage are obtained, wherein the first capacitor voltage is the voltage of a first capacitor on the direct current side of the inverter, the second capacitor voltage is the voltage of a second capacitor on the direct current side of the inverter, the first end of the first capacitor is electrically connected with the first end of the fault bridge arm, the second end of the first capacitor is electrically connected with the first end of the second capacitor and the midpoint of the capacitor on the direct current side, and the second end of the second capacitor is electrically connected with the second end of the fault bridge arm; and calculating by adopting the first capacitance voltage and the second capacitance voltage to obtain the initial compensation quantity.

Specifically, as shown in fig. 2, the first capacitor C ₁ and the second capacitor C ₂ are used as up-and-down voltage dividing capacitors on the dc side of the inverter, and in this embodiment, the first capacitor voltage up may be obtained by collecting the voltage on the first capacitor C ₁, and the second capacitor voltage un may be obtained by collecting the voltage on the second capacitor C ₂, so as to determine the midpoint potential deviation of the dc bus by using the first capacitor voltage up and the second capacitor voltage un, to realize sampling of the midpoint potential deviation of the dc bus, and may use the first capacitor voltage up and the second capacitor voltage un to calculate to obtain an initial compensation amount, so that the target compensation amount may be determined subsequently based on the initial compensation amount in combination with the voltage equalizing control compensation amount corresponding to the midpoint potential deviation.

In an embodiment of the present application, the dc component of the initial compensation amount may be determined by a filtering manner, for example, the initial compensation amount may be filtered by using a bus Wo Lvbo device to obtain the dc component in the initial compensation amount, and then the dc component may be subtracted from the initial compensation amount to obtain the compensation amount without the dc component, so that the midpoint current satisfies half-wave symmetry, and then the compensation amount without the dc component may be reused to add the equalizing control compensation amount to obtain the target compensation amount.

Optionally, the embodiment of the present application calculates, based on the initial compensation amount and in combination with the equalizing control compensation amount, a target compensation amount, which may specifically include: filtering the initial compensation quantity to obtain a direct current component in the initial compensation quantity; subtracting the direct current component from the initial compensation quantity to obtain a fault-tolerant compensation quantity; and adding the voltage equalizing control compensation quantity by using the fault-tolerant compensation quantity to obtain the target compensation quantity. The fault-tolerant compensation amount refers to compensation amount without direct current component, and can be particularly used for fault-tolerant control of an inverter, so that the neutral point current meets half-wave symmetry.

In an optional embodiment of the present application, determining the equalizing control compensation amount corresponding to the midpoint potential deviation of the inverter may specifically include: obtaining the DC bus voltage of the inverter; combining the midpoint potential deviation according to the direct current bus voltage to synthesize a reference voltage vector so as to obtain a reference voltage vector; and determining the equalizing control compensation quantity by adopting the absolute value of the midpoint potential deviation based on the vector region where the reference voltage vector is located.

As an example of the present application, the switching function of the inverter may be predefined as:

According to the switching function of the inverter, the three-phase three-level NPC inverter before the bridge arm fault can output 27 switching states, and the three-phase three-level NPC inverter corresponds to 27 space voltage vectors, and as shown in FIG. 4, the three-phase three-level NPC inverter can be divided into 3 zero vectors (PPP, OOO, NNN), 12 small vectors (POO, ONN, PPO, OON, OPO, NON, OPP, NOO, OOP, NNO, POP, ONO), 6 middle vectors (PON, OPN, NPO, NOP, ONP, PNO) and 6 large vectors (PNN, PPN, NPN, NPP, NNP, PNP) according to the magnitude of vector amplitude; the 27 space voltage vectors are distributed over 6 sectors.

The eight-switch three-phase inverter (EIGHT SWITCH THREE PHASE INVERTERS, ESTPI) topology after single-phase failure has 9 switch states, and the ESTPI topology A phase after A phase failure can only output O level. As can be known from the ESTPI topological space vector after the A-phase bridge arm fault is observed, as shown in FIG. 5, 6 sectors are arranged in the ESTPI topological space vector diagram after the A-phase bridge arm fault, the sectors II and V contain middle vectors, and the sectors II and V can be divided into subareas 1 and 2; the space vector can be divided into 6 sectors, and the overall space vector distribution meets the reference voltage vector synthesis condition. But the reference voltage synthesis rule needs to be reselected due to the partial absence of the space voltage vector.

When designing the reference voltage synthesis rule, the common-mode voltage corresponding to the residual vector can be considered first, and the common-mode leakage current is generated by the distributed capacitance due to the change of the common-mode voltage, so that electromagnetic interference is brought and the system efficiency is reduced.

Specifically, because the common mode voltage may be defined as u _cm=1/3(u_ao+u_bo+u_co), where u _ao is the voltage between the output of the a-phase bridge arm and the midpoint of the dc bus, u _bo is the voltage between the output of the B-phase bridge arm and the midpoint of the dc bus, u _co is the voltage between the output of the C-phase bridge arm and the midpoint of the dc bus, and as a result, the common mode voltage corresponding to each voltage vector is obtained, for example, the common mode voltage corresponding to the zero voltage vector OOO is 0V, the common mode voltage corresponding to the small voltage vector OPP, ONN, OPO, OOP, OON, ONO is V _dc/3V、-V_dc/3V、V_dc/6V、V_dc/6V、-V_dc/6V、-V_dc/6V, and the common mode voltage corresponding to the medium voltage vector is 0V. In order to reduce common mode voltage, when synthesizing a reference voltage vector, a middle vector is introduced, and the reference voltage vector is synthesized through zero vectors, small vectors and middle vectors, so that the reference voltage vector is obtained.

For example, in the case of setting the reference voltage vector synthesis order as shown in table 1, in combination with the above example, the small sector at the time of a-phase failure is defined only in the ii, v-th sectors; after the ESTPI topological reference voltage synthesis sequence after the A phase fault is determined, according to the volt-second balance principle, according to the ESTPI topological reference voltage synthesis sequence after the A phase fault, reference voltage vector synthesis is carried out through zero vectors, small vectors and medium vectors, and a reference voltage vector is obtained.

TABLE 1

Wherein N is a large sector in the basic voltage vector diagram; n is the sub-region within the sector.

In a specific implementation, the neutral point potential fluctuation of the direct current bus is an inherent phenomenon, and no redundant vector is available for neutral point potential control under the single-phase fault state of the NPC three-level inverter, so that the output imbalance of the inverter exists naturally. Considering the influence of midpoint potential fluctuation on reference voltage vector synthesis, the embodiment of the application can determine the equalizing control compensation quantity by adopting the absolute value of midpoint potential deviation based on the vector area where the reference voltage vector is positioned according to the volt-second balance principle so as to compensate the reference voltage vector synthesis when the midpoint potential fluctuates according to the volt-second balance principle.

For example, by analyzing ESTPI operation modes after the a-phase bridge arm fault, the inverter output voltage can be obtained as follows:

Wherein u _ao、u_bo、u_co is three-phase output of the inverter A, B, C, and Deltau is neutral point potential deviation of the direct current bus. According to the space voltage vector calculation formula, u _ao、u_bo、u_co can be used for determining a space voltage vector u _s, so that the distribution situation of the space voltage vector along with the voltage change of the midpoint of the direct current bus in the stationary two-phase alpha beta coordinate system is obtained, as shown in fig. 6. It should be noted that, the calculation formula of the space voltage vector u _s is:

Along with the aggravation of the fluctuation of the midpoint of the direct current bus, the output unbalance degree of the inverter is further increased, the linear modulation area is gradually reduced, and the midpoint potential deviates from the balance point, so that the reference voltage vector does not satisfy the volt-second balance principle after exceeding the linear modulation area, and the output current of the inverter is severely distorted. Therefore, the neutral point potential fluctuation of the direct current bus leads to deviation of basic voltage vector distribution, and if the influence of the neutral point potential fluctuation is ignored, the basic voltage vector containing the deviation is used for synthesizing the reference voltage vector, so that the grid-connected power quality is inevitably influenced. Therefore, considering the influence of the midpoint potential fluctuation on the reference voltage vector synthesis, the reference voltage vector synthesis during the midpoint potential fluctuation is compensated based on the volt-second balance principle, taking the first sector as an example (n=1), and the volt-second balance equation is as follows:

Can be expressed in the αβ coordinate system as:

（1）

the calculation method of the action time of each space vector of the rest sectors is the same, and the reference voltage vector synthesis rule which does not consider the midpoint potential fluctuation can be obtained, wherein the reference voltage vector synthesis rule is shown in table 2.

TABLE 2

Since the above formula (1) does not consider the influence of the fluctuation of the neutral point potential of the bus on the space vector voltage, T ₀、T₁、T₂ in table 4 obtained by using the formula (1) necessarily contains an error. Considering the influence of the neutral potential fluctuation of the bus on the space vector voltage, the space vector after the neutral potential fluctuation is compensated, and the following formula (2) can be rewritten as formula (1):

（2）

The calculation method of the space vector acting time of the rest sectors of T₁=2mT_ssin(π/3-θ)/(1-2△u/V_dc),T₂=2mT_ssin(θ)/(1-2△u/V_dc),T₀=T_S-T₁-T₂, is the same, so that vector synthesis can be compensated, and a reference voltage vector synthesis rule which is shown in table 3 and takes the midpoint potential fluctuation into account is designed.

TABLE 3 Table 3

Wherein Ts is a sampling control period, m is a modulation depth, and the maximum linear modulation region is defined to correspond to m=1, soV _ref is a reference voltage vector output by the grid-connected controller, and V _dc is a direct-current bus voltage; t ₁、T₂ is the acting time of the vector V ₁、V₂, i _o1、i_o2 is the current corresponding to the midpoint of the outgoing DC bus when the vector V ₁、V₂ acts, and the direction of the midpoint of the outgoing bus is regulated to be positive; thus, throughout the space vector diagram, the reference voltage vector V _ref can be synthesized according to table 2 using the zero vector and vector V ₁、V₂, where the zero vector is applied for a time T ₀ and T ₀=T_S-T₁-T₂,T_S is a control period.

Based on table 3, the current flowing into and out of the midpoint of the dc bus in one fundamental wave period can be analyzed according to the synthesis rule of the reference voltage vector V _ref in the whole space voltage vector diagram. Assuming three-phase equilibrium, there are:

Wherein I _m is the phase current amplitude, phi is the phase included angle of the stator voltage and the stator current of the motor defined by the grid-connected power factor angle when the motor is driven; because one sampling control period is very short, the current in one sampling control period can be assumed to be unchanged, and because the zero vector does not influence the midpoint potential, the midpoint current in each modulation period can be represented by the midpoint current of the V ₁、V₂ vector, and the area equivalent principle is utilized to combine the volt-second balance principle formula And Table 3, the current flowing out of the midpoint of the DC bus in one fundamental wave period can be obtained, and the following formula is shown:

In order to restrain the shift of the neutral point potential of the bus, the average value of the neutral point current flowing in and out is zero in one fundamental wave period, the neutral point current meets half-wave symmetry, namely Can be according to the formulaThe dc component in the dc bus midpoint deviation in table 2 is filtered, and as shown in fig. 7, butterworth low pass filtering may be used to obtain dc component K ₁. When the reference voltage vector V _ref is in the sectors I, III, IV and VI, the initial compensation quantity Deltau can be adjusted by a table look-up mode to control the fluctuation of the neutral point potential of the direct current bus.

For example, in the case of designing the table look-up table as table 4, the midpoint potential deviation of the dc bus may be obtained by sampling on the software level, that is, midpoint potential deviation sampling is performed, as shown in fig. 7, to obtain an initial compensation amount Δu corresponding to the midpoint potential deviation of the dc bus, then a dc component K ₁ in the initial compensation amount Δu is obtained by a bas Wo Lvbo(s), and then, by combining the midpoint deviation condition of the dc bus and the sector where the reference vector is located, a compensation amount K2 is obtained by table 4 as a voltage-equalizing control compensation amount corresponding to the midpoint potential deviation, and then, the collected Δu may be subtracted by the dc component K ₁ and added with the compensation amount K ₂ to obtain a target compensation amount Δu', that is: the method comprises the steps of performing delta u '= delta u-K ₁+K₂, then using a target compensation quantity delta u' to replace an original initial compensation quantity delta u to send to a fault-tolerant control SVPWM algorithm of an inverter, obtaining the acting time T ₀、T₁、T₂ of each vector after final compensation, obtaining the acting time of each space vector in a control period T _s, and obtaining the on-off time of each switching power tube by combining a preset defined switching function of the inverter and a table 1, so as to realize the driving control of the NPC type inverter after faults, and further realize the neutral point potential offset suppression and pulse width modulation of the NPC type three-level inverter after faults.

TABLE 4 Table 4

In an embodiment of the present application, fault-tolerant control is performed on the inverter according to the target compensation amount to obtain a driving signal of the inverter, which may specifically include: based on the target compensation quantity, calculating by adopting a space vector pulse width modulation algorithm to obtain a pulse driving signal; and carrying out balance control on the midpoint voltage of the direct current bus of the inverter based on the pulse driving signal. For example, when the single-phase bridge arm of the inverter fails, the fast fuse FU of the failed phase bridge arm can be disconnected, the failed bridge arm is cut out, and the failed phase bidirectional thyristor T _x is turned on, so that the failed phase output of the inverter is directly connected with the midpoint of the direct current bus, fault-tolerant topology reconstruction after the failure is completed, meanwhile, the initial compensation quantity corresponding to the midpoint potential deviation can be adjusted through table lookup, so that the space vector pulse width modulation algorithm of the inverter can be adjusted according to the adjusted target compensation quantity, the balanced control of the midpoint voltage of the direct current bus is realized, the BOOST circuit of the front stage of the inverter is started, the direct current bus voltage is improved, and the output capability of the inverter after the failure can be effectively improved.

In an embodiment of the present application, there is provided a fault-tolerant control apparatus for an inverter, as shown in fig. 8, including: fault tolerant control system 810 and inverter 820; wherein the inverter 820 comprises at least three level bridge arms and bidirectional thyristors connected with the single-phase bridge arms in a one-to-one correspondence manner; the inverter 820 is configured to disconnect a fault bridge arm after a single-phase bridge arm fails, and turn on the bidirectional thyristors correspondingly connected to the fault bridge arm, thereby implementing fault-tolerant topology reconstruction. The fault-tolerant control system 810 is configured to conduct a boost circuit of the inverter 820 based on a bridge arm fault signal of the inverter 820; the direct-current bus voltage of the inverter 820 is improved through the booster circuit, and initial compensation quantity after topology reconstruction is obtained; determining voltage equalizing control compensation quantity corresponding to the neutral point potential deviation of the inverter; calculating based on the initial compensation quantity and combining the voltage equalizing control compensation quantity to obtain a target compensation quantity; and performing fault-tolerant control on the inverter 820 according to the target compensation amount to obtain a driving signal of the inverter 820.

Specifically, after the single-phase bridge arm fails, the inverter 820 realizes topology reconstruction by disconnecting the failed bridge arm and turning on the bidirectional thyristors correspondingly connected to the failed bridge arm. After obtaining the initial compensation amount generated after the topology reconstruction of the inverter 820, the fault-tolerant control system 810 may calculate, based on the initial compensation amount, by combining with the voltage-equalizing control compensation amount corresponding to the midpoint potential deviation of the inverter 820, to obtain the target compensation amount, so as to perform fault-tolerant control on the inverter 820 according to the target compensation amount, and obtain the driving signal of the inverter. For example, the control system may adjust the space vector pulse width modulation algorithm of the inverter according to the target compensation amount, so as to bring the target compensation amount into the reference voltage vector synthesis, thereby obtaining the acting time of each space voltage vector after final compensation of space vector modulation, further obtaining a driving signal, and simultaneously conducting the front-stage boost circuit of the inverter, so as to improve the amplitude of the remaining alternative voltage vector of the inverter after the single-phase bridge arm fault, and ensure the driving capability of the inverter after the fault.

In an alternative embodiment of the present application, the fault tolerant control system 810 includes a boost circuit, an output of the boost circuit is electrically connected to the dc bus of the inverter 820, and the boost circuit is configured to boost the dc bus voltage of the inverter. Therefore, the output end of the boost circuit in the embodiment of the application is electrically connected with the direct current bus of the inverter, so that the amplitude of the residual alternative voltage vector of the inverter after the single-phase bridge arm faults can be improved through the direct current bus voltage of the boost circuit inverter 820, and the driving capability of the inverter after the faults is further ensured.

Optionally, the output end of the boost circuit includes a first output end and a second output end, and the inverter further includes: the pressure equalizing control module; the first end of the voltage equalizing control module is electrically connected with the first output end of the boost circuit and the first end of each phase leg of the inverter, the second end of the voltage equalizing control module is electrically connected with the first end of the bidirectional thyristor and the midpoint of each phase leg of the inverter, and the third end of the voltage equalizing control module is electrically connected with the second output end of the boost circuit and the second end of each phase leg of the inverter 820; the output end of each phase bridge arm is electrically connected with the second end of the bidirectional thyristor correspondingly connected with the bridge arm.

Optionally, the voltage equalizing control module includes: the first capacitor, the second capacitor, the first resistor and the second resistor. As shown in fig. 9, a first end of the first capacitor C ₁ is electrically connected to the first output end of the boost circuit, a first end of the first resistor R ₁, and a first end of each phase leg of the inverter, and a second end of the first capacitor C1 is electrically connected to a second end of the first resistor R ₁, a first end of the second capacitor C ₂, a first end of the second resistor R ₂, a first end of the triac, and a leg midpoint of each phase leg of the inverter; the second end of the second capacitor C ₂ is electrically connected to the second end of the second resistor R ₂, the second output end of the boost circuit, and the second end of each phase leg of the inverter. The output end of each phase bridge arm is electrically connected with the second end of the corresponding connected bidirectional thyristor, so that the inverter can realize topology reconstruction through the corresponding connected bidirectional thyristor with the conduction fault.

The first resistor R ₁ and the second resistor R ₂ are used as voltage equalizing resistors R ₁、R₂ connected in parallel on the dc bus capacitor C ₁、C₂, and can be used for eliminating the dc bus midpoint potential deviation caused by different capacitance values of the devices of the capacitor process reason C ₁、C₂, so as to inhibit the bus midpoint potential deviation on the hardware level.

In an alternative embodiment of the application, the boost circuit comprises a filter capacitor C ₃, a voltage stabilizing capacitor C ₄, a boost inductor L, a diode D ₇ and a power switch device S ₁; the first end of the filter capacitor C ₃ is electrically connected to the first end of the power switch device S ₁ and the positive electrode of the diode D ₇ through the boost inductor L, the cathode of the diode D ₇ is electrically connected to the first end of the voltage stabilizing capacitor C ₄ and the first end of the voltage equalizing control module, and the second end of the filter capacitor C ₃ is electrically connected to the second end of the power switch device S ₁, the second end of the voltage stabilizing capacitor C ₄ and the third end of the voltage equalizing control module.

For example, taking an NPC type level inverter as an example, in a normal operation mode of the NPC type level inverter, as shown in fig. 10, by judging whether a fault exists on a single-phase bridge arm, when the fault exists on the single-phase bridge arm, the inverter topology is reconstructed by cutting off a fault-phase bridge arm and conducting a bidirectional thyristor corresponding to the fault, and then the voltage on the direct current side of the inverter can be raised by a boost circuit, so that fault-tolerant control of the NPC type three-level inverter is realized, and further, the output capability of the inverter after the fault can be effectively improved.

In summary, when a short circuit or open circuit fault occurs in a single-phase bridge arm of the inverter, the embodiment of the application can realize inverter reconstruction through the fast fuse and the bidirectional thyristor at the output end of a fault phase, and then the voltage of a direct-current bus of the inverter after the fault is improved through the boost circuit, so that the continuous operation of the NPC three-level inverter after the fault is ensured by combining a fault-tolerant control SVPWM algorithm.

It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments.

As shown in fig. 11, the embodiment of the application further provides a fault-tolerant control system of an inverter, which includes the following modules:

a fault signal module 1110, configured to conduct a boost circuit of an inverter based on a bridge arm fault signal of the inverter;

the dc boost module 1120 is configured to boost, by using the boost circuit, a dc bus voltage of the inverter;

the topology reconfiguration obtaining module 1130 is configured to perform topology reconfiguration on the inverter according to the bridge arm fault signal, and obtain an initial compensation amount after the topology reconfiguration;

The voltage equalizing compensation determining module 1140 is configured to determine a voltage equalizing control compensation amount corresponding to the midpoint potential deviation of the inverter;

The target compensation calculation module 1150 is configured to calculate, based on the initial compensation amount, in combination with the voltage equalizing control compensation amount, to obtain a target compensation amount;

and the fault-tolerant control module 1160 is used for performing fault-tolerant control on the inverter according to the target compensation amount to obtain a driving signal of the inverter.

Optionally, the topology reconfiguration obtaining module includes: the fault bridge arm determining submodule is used for determining a single-phase bridge arm corresponding to the bridge arm fault signal as a fault bridge arm; the topology reconstruction sub-module is used for cutting out the fault bridge arm from the topological structure of the inverter and conducting a bidirectional thyristor correspondingly connected with the fault bridge arm, one end of the bidirectional thyristor is electrically connected with the output end of the fault bridge arm and the bridge arm midpoint of the fault bridge arm, and the other end of the bidirectional thyristor is electrically connected with the direct-current side capacitor midpoint of the inverter.

Optionally, the midpoint potential deviation is a midpoint potential deviation of a dc bus of the inverter, and the topology reconstruction obtaining module further includes: the voltage acquisition sub-module and the calculation sub-module. The voltage acquisition submodule is used for: after the bidirectional thyristor is conducted, a first capacitor voltage and a second capacitor voltage are obtained, wherein the first capacitor voltage is the voltage of a first capacitor on the direct current side of the inverter, the second capacitor voltage is the voltage of a second capacitor on the direct current side of the inverter, the first end of the first capacitor is electrically connected with the first end of the fault bridge arm, the second end of the first capacitor is electrically connected with the first end of the second capacitor and the midpoint of the capacitor on the direct current side, and the second end of the second capacitor is electrically connected with the fault; the calculating submodule is used for: and calculating by adopting the first capacitance voltage and the second capacitance voltage to obtain the initial compensation quantity.

Optionally, the voltage equalizing compensation determining module includes: the DC bus voltage acquisition sub-module is used for acquiring the DC bus voltage of the inverter; the vector synthesis submodule is used for carrying out reference voltage vector synthesis according to the direct current bus voltage and combining the midpoint potential deviation to obtain a reference voltage vector; and the voltage-sharing control compensation quantum module is used for determining the voltage-sharing control compensation quantity by adopting the absolute value of the midpoint potential deviation based on the vector region where the reference voltage vector is located.

Optionally, the target compensation calculating module includes: the filtering sub-module is used for filtering the initial compensation quantity to obtain a direct current component in the initial compensation quantity; the direct current component removing submodule is used for subtracting the direct current component from the initial compensation quantity to obtain a fault-tolerant compensation quantity; and the target compensation quantum module is used for adding the voltage equalizing control compensation quantity to the fault-tolerant compensation quantity to obtain the target compensation quantity.

Optionally, the fault-tolerant control module includes: the pulse width modulation calculation sub-module is used for calculating by adopting a space vector pulse width modulation algorithm based on the target compensation quantity to obtain a pulse driving signal; and the equalization control sub-module is used for performing equalization control on the midpoint voltage of the direct current bus of the inverter based on the pulse driving signal.

In a specific implementation, the fault-tolerant control system can be applied to terminal equipment, so that the terminal equipment is used as fault-tolerant control equipment of an inverter, the inverter is topologically reconstructed according to bridge arm fault signals by acquiring the bridge arm fault signals, the topology reconstruction of the inverter is realized, initial compensation quantity after the topology reconstruction and voltage-sharing control compensation quantity corresponding to the neutral point potential deviation of the inverter are acquired, the voltage-sharing control compensation quantity is combined with the initial compensation quantity to calculate, and the target compensation quantity is obtained, so that the fault-tolerant control of the inverter can be carried out according to the target compensation quantity, for example, a space vector pulse width modulation algorithm of the inverter is adjusted according to the target compensation quantity, the neutral point potential deviation inhibition of the inverter after the fault is realized, the driving capability of the inverter after the fault is ensured, and further the continuous operation of the inverter after the fault is ensured, and the technical problem that the driving capability of the inverter cannot be ensured after the NPC three-level inverter is in the prior art is faulted is solved. It should be noted that the fault-tolerant control device may be formed by two or more physical entities, or may be formed by one physical entity, for example, the fault-tolerant control device may be a personal computer (Personal Computer, PC), a computer, a server, an inverter device, or the like, which is not limited in particular by the embodiment of the present application.

In an embodiment of the present application, there is also provided a fault-tolerant control apparatus for an inverter, including: a memory and a processor; wherein the memory is used for storing a computer program; and the processor is used for executing the computer program stored in the memory, and when the computer program is executed, the steps of the fault-tolerant control method of the inverter provided by any one of the method embodiments are realized. For example, as shown in fig. 12, an embodiment of the present application provides a fault-tolerant control device for an inverter, including a processor 111, a communication interface 112, a memory 113 and a communication bus 114, where the processor 111, the communication interface 112, and the memory 113 perform communication with each other through the communication bus 114, and the memory 113 is used for storing a computer program; the processor 111 is configured to implement the fault-tolerant control method of the inverter provided in any one of the foregoing method embodiments when executing the program stored in the memory 113.

The embodiment of the application also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the fault-tolerant control method of an inverter provided in any one of the method embodiments described above.

The present application also provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of the image conversion method provided by any of the method embodiments described above.

The apparatus, system, and device embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the method described in the respective embodiments or some parts of the embodiments.

It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," and "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an order of performance is explicitly stated. It should also be appreciated that additional or alternative steps may be used.

The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A fault-tolerant control method of an inverter, comprising:

switching on a boost circuit of an inverter based on a bridge arm fault signal of the inverter;

The direct-current bus voltage of the inverter is improved through the booster circuit;

performing topology reconstruction on the inverter according to the bridge arm fault signals, and acquiring initial compensation quantity after the topology reconstruction;

determining voltage equalizing control compensation quantity corresponding to the neutral point potential deviation of the inverter;

Calculating based on the initial compensation quantity and combining the voltage equalizing control compensation quantity to obtain a target compensation quantity;

performing fault-tolerant control on the inverter according to the target compensation quantity to obtain a driving signal of the inverter;

The determining the equalizing control compensation quantity corresponding to the midpoint potential deviation of the inverter comprises the following steps: obtaining the DC bus voltage of the inverter; combining the midpoint potential deviation according to the direct current bus voltage to synthesize a reference voltage vector so as to obtain a reference voltage vector; and determining the equalizing control compensation quantity by adopting the absolute value of the midpoint potential deviation based on the vector region where the reference voltage vector is located.

2. The fault tolerant control method of claim 1, wherein the performing topology reconstruction on the inverter according to the bridge arm fault signal comprises:

determining a single-phase bridge arm corresponding to the bridge arm fault signal as a fault bridge arm;

And cutting out the fault bridge arm from the topological structure of the inverter, and conducting a bidirectional thyristor correspondingly connected with the fault bridge arm, wherein one end of the bidirectional thyristor is electrically connected with the output end of the fault bridge arm and the bridge arm midpoint of the fault bridge arm, and the other end of the bidirectional thyristor is electrically connected with the direct-current side capacitor midpoint of the inverter.

3. The fault-tolerant control method according to claim 2, wherein the midpoint potential deviation is a dc bus midpoint potential deviation, and the obtaining the initial compensation amount after topology reconstruction includes:

After the bidirectional thyristor is conducted, a first capacitor voltage and a second capacitor voltage are obtained, wherein the first capacitor voltage is the voltage of a first capacitor on the direct current side of the inverter, the second capacitor voltage is the voltage of a second capacitor on the direct current side of the inverter, the first end of the first capacitor is electrically connected with the first end of the fault bridge arm, the second end of the first capacitor is electrically connected with the first end of the second capacitor and the midpoint of the capacitor on the direct current side, and the second end of the second capacitor is electrically connected with the second end of the fault bridge arm;

and calculating by adopting the first capacitance voltage and the second capacitance voltage to obtain the initial compensation quantity.

4. The fault-tolerant control method according to claim 1, wherein calculating a target compensation amount based on the initial compensation amount in combination with the voltage-equalizing control compensation amount includes:

Filtering the initial compensation quantity to obtain a direct current component in the initial compensation quantity;

subtracting the direct current component from the initial compensation quantity to obtain a fault-tolerant compensation quantity;

And adding the voltage equalizing control compensation quantity by using the fault-tolerant compensation quantity to obtain the target compensation quantity.

5. The fault-tolerant control method according to claim 1, wherein the fault-tolerant control of the inverter in accordance with the target compensation amount includes:

Based on the target compensation quantity, calculating by adopting a space vector pulse width modulation algorithm to obtain a pulse driving signal;

And carrying out balance control on the midpoint voltage of the direct current bus of the inverter based on the pulse driving signal.

6. A fault tolerant control system for an inverter, comprising:

the fault-tolerant control module is used for carrying out fault-tolerant control on the inverter according to the target compensation quantity to obtain a driving signal of the inverter;

Wherein, the voltage equalizing compensation determining module comprises: the direct-current bus voltage acquisition sub-module, the vector synthesis sub-module and the voltage equalizing control compensation sub-module;

The DC bus voltage acquisition submodule is used for acquiring the DC bus voltage of the inverter;

The vector synthesis submodule is used for carrying out reference voltage vector synthesis according to the direct current bus voltage and combining the midpoint potential deviation to obtain a reference voltage vector;

And the voltage-sharing control compensation quantum module is used for determining the voltage-sharing control compensation quantity by adopting the absolute value of the midpoint potential deviation based on the vector region where the reference voltage vector is located.

7. A fault tolerant control for an inverter, comprising: fault tolerant control system and inverter;

The fault-tolerant control system is used for conducting a boost circuit of the inverter based on a bridge arm fault signal of the inverter; the direct-current bus voltage of the inverter is improved through the booster circuit, and initial compensation quantity after topology reconstruction is obtained; determining voltage equalizing control compensation quantity corresponding to the neutral point potential deviation of the inverter; calculating based on the initial compensation quantity and combining the voltage equalizing control compensation quantity to obtain a target compensation quantity; performing fault-tolerant control on the inverter according to the target compensation quantity to obtain a driving signal of the inverter;

8. The apparatus of claim 7, wherein the fault tolerant control system comprises: and the output end of the boost circuit is electrically connected with the direct current bus of the inverter.

9. The apparatus of claim 8, wherein the output of the boost circuit comprises a first output and a second output, the inverter further comprising: the pressure equalizing control module;

the first end of the voltage equalizing control module is electrically connected with the first output end of the boost circuit and the first end of each phase bridge arm of the inverter, the second end of the voltage equalizing control module is electrically connected with the first end of the bidirectional thyristor and the midpoint of each phase bridge arm of the inverter, and the third end of the voltage equalizing control module is electrically connected with the second output end of the boost circuit and the second end of each phase bridge arm of the inverter;

the output end of each phase bridge arm is electrically connected with the second end of the bidirectional thyristor correspondingly connected with the bridge arm.

10. The apparatus of claim 9, wherein the pressure equalizing control module comprises: the first capacitor, the second capacitor, the first resistor and the second resistor;

The first end of the first capacitor is electrically connected with the first output end of the boost circuit, the first end of the first resistor and the first end of each phase bridge arm of the inverter, and the second end of the first capacitor is electrically connected with the second end of the first resistor, the first end of the second capacitor, the first end of the second resistor, the first end of the triac and the midpoint of each phase bridge arm of the inverter;

11. The apparatus of any one of claims 8 to 10, wherein the boost circuit comprises a filter capacitor, a voltage stabilizing capacitor, a boost inductor, a diode, and a power switching device;

The first end of the filter capacitor is electrically connected with the first end of the power switch device and the anode of the diode through the boost inductor, the cathode of the diode is electrically connected with the first end of the voltage stabilizing capacitor and the first end of the voltage equalizing control module, and the second end of the filter capacitor is electrically connected with the second end of the power switch device, the second end of the voltage stabilizing capacitor and the third end of the voltage equalizing control module.

12. A fault tolerant control apparatus for an inverter, comprising:

A memory for storing a computer program;

A processor for executing a computer program stored in said memory, and which, when executed, implements the steps of the fault-tolerant control method of an inverter as claimed in any one of claims 1-5.

13. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the fault-tolerant control method of an inverter according to any one of claims 1-5.