CN117971756A

CN117971756A - Clock phase determining method and device, electronic equipment and storage medium

Info

Publication number: CN117971756A
Application number: CN202410136446.0A
Authority: CN
Inventors: 王江伟; 赵江; 王镇山
Original assignee: Lingsi Microelectronics Hangzhou Co ltd
Current assignee: Lingsi Microelectronics Hangzhou Co ltd
Priority date: 2024-01-31
Filing date: 2024-01-31
Publication date: 2024-05-03

Abstract

The application provides a method, a device, electronic equipment and a storage medium for determining clock phase, and relates to the technical field of communication, wherein the method comprises the following steps: after receiving a first clock signal of a target frequency, inputting the first clock signal into a delay line, and selecting M optional selection bits from N selection bits of the line to determine a first high-level signal; determining a target phase and a target delay value; acquiring a delayed second sampling clock signal, and reading data at different phases in a target half period by adjusting the bit numbers of the selected M selected bits to determine a first adjustment bit number and a second adjustment bit number; and determining the target clock phase according to the first adjusting bit number and the second adjusting bit number and the target delay value. The technical problem that the stability of the data read by the sampling clock cannot be maintained under the condition that the influence of environmental factors is large in the related art is solved, and the technical effect of maintaining the stability of the data read by the sampling clock under the condition that the influence of the environmental factors is large is achieved.

Description

Clock phase determining method and device, electronic equipment and storage medium

Technical Field

The present application relates to the field of communications technologies, and in particular, to a method and apparatus for determining a clock phase, an electronic device, and a storage medium.

Background

With the rapid development of digital communication technology, sampling clock signals play a critical role in ensuring signal synchronization and data integrity. In high-speed digital systems, the sampling clock signal not only needs to maintain a stable frequency, but must also ensure that data is collected or transmitted at the correct point in time. Thus, clock signals are one of the core technologies to ensure data integrity.

In the related art, during the process of reading and writing data, a main control interface inside a main chip generates a corresponding serial peripheral interface (SERIAL PERIPHERAL INTERFACE, which may be abbreviated as SPI) clock through even frequency division, and the rising edge of the serial peripheral interface clock needs to be kept in a stable area of each beat of data, so as to ensure the stability of reading and writing data. However, in the low-voltage high-temperature or high-voltage low-temperature application scenario, the main control interface may use the serial peripheral interface clock as the sampling clock to capture external data, and the environmental factors (for example, low-voltage high-temperature or high-voltage low-temperature) have an influence on the delay of the sampling clock and related elements (for example, the main chip, the data line, the receiving chip, etc.), so that the delay configuration value is determined in the main chip according to the environmental factors and the delay of the related elements, and then the sampling clock phase is adjusted by the delay configuration value, so that the rising edge of the sampling clock is kept in the stable area of each beat of data, so as to ensure the stability of the read data.

However, in the above manner, when the environmental factor has a larger influence on the delay of the sampling clock and the related element, a larger delay configuration value is determined according to the delay of the environmental factor and the related element, and a larger phase granularity (i.e., a phase adjustment amount) is generated by adjusting the phase of the sampling clock through the larger delay configuration value, so that the rising edge of the sampling clock is caused to jump out of the stable area of the read data, and further, the stability of the read data of the sampling clock cannot be maintained under the condition that the influence of the environmental factor is larger in the related art.

Disclosure of Invention

The application provides a clock phase determining method, a clock phase determining device, electronic equipment and a storage medium, which are used for keeping the stability of reading data by a sampling clock under the condition of great influence of environmental factors.

In a first aspect, the present application provides a method for determining a clock phase, the method comprising: after a first sampling clock signal of a target frequency input by clock control equipment is received, inputting the first sampling clock signal into a delay line, and selecting M selection bits from N selection bits in the delay line to determine that the M selection bits are first high-level signals provided by corresponding M-level delay units, wherein the N selection bits correspond to N+1-level delay units, and the delay line comprises the N selection bits and the N+1-level delay units, and M is more than or equal to 2 and less than or equal to N; determining a target phase of each delay target half period of the first sampling clock signal in the delay line and a target delay value of each stage of delay unit according to the first sampling clock signal, the first high-level signal and the M stages of delay units; acquiring a second sampling clock signal output by the delay line, wherein the second sampling clock signal is obtained by delaying the first sampling clock signal by the delay line; optionally selecting the M selection bits from the N selection bits in the target half period corresponding to the target phase in the second sampling clock signal, and adjusting the number of bits of the M selection bits in turn so as to execute a data reading operation in different phases of the target half period after adjusting the number of bits of the M selection bits each time, wherein the target phase comprises a plurality of phases, and the target half period is the difference value between any two adjacent phases in the plurality of phases; after the correct data is read from the first phase of the first half period, the bit number of the M selected bits corresponding to the first phase is recorded as a first adjustment bit number, wherein the data read before the first phase is error data, the data read after the first phase and before the first target phase is correct data, the first target phase is delayed to the first phase on the second sampling clock signal, the target phase comprises the first target phase, and the target half period comprises the first half period; after error data is read from a second phase of a second half period, and the number of bits of the M selected bits corresponding to the second phase is recorded as a second adjustment bit number, wherein the data read after the second phase and before a second target phase are error data, and the data read before the second phase and after the first phase are correct data, the second phase is delayed by the first target phase and the second target phase is delayed by the second phase on the second sampling clock signal, the target phase comprises the second target phase, the target half period comprises a second half period, and the second half period is delayed by the first half period on the second sampling clock signal; and determining a target clock phase according to the target delay value, the first adjustment bit number and the second adjustment bit number.

By adopting the technical scheme, the received first sampling clock signal is input into the delay line, and M selection bits are selected from N selection bits in the delay line to determine that the M selection bits are the first high-level signal provided by the corresponding M-stage delay unit, so that the flexibility and the adaptability of delay configuration of the clock signal are ensured. And determining the target phase of each delay target half period of the first sampling clock signal in the delay line and the target delay value of each stage of delay unit according to the first sampling clock signal, the first high-level signal and the M stages of delay units. And obtaining a second sampling clock signal which is output by the delay line and is obtained by delaying the first sampling clock signal, wherein in the second sampling clock signal, data reading operation can be performed at different phases by adjusting the bit numbers of the selected M selected bits in a target half period corresponding to the target phase. So that after correctly reading data at the first phase of the first half cycle, the bit at this time can be set to the first adjustment bit number, and when erroneous data is read at the second phase of the second half cycle, the bit at this time can be set to the second adjustment bit number. And determining the target clock phase according to the target delay value, the first adjustment bit number and the second adjustment bit number. And the data can be read according to the target clock phase, so that the purpose that the stability of the data read by the sampling clock is not affected by temperature is realized. The technical problem that the stability of the data read by the sampling clock cannot be maintained under the condition that the influence of environmental factors is large in the related art is solved, and the technical effect of maintaining the stability of the data read by the sampling clock under the condition that the influence of the environmental factors is large is achieved.

Optionally, the determining, according to the first sampling clock signal, the first high level signal and the M-stage number of the M-stage delay unit, a target phase of each delay target half cycle of the first sampling clock signal in the delay line and a target delay value of each stage delay unit specifically includes: acquiring a third sampling clock signal obtained by delaying the first sampling clock signal by the M-stage delay unit according to the first high-level signal; inputting the first sampling clock signal and the third sampling clock signal into a trigger device to acquire a trigger signal output by the trigger device; under the condition that the trigger signal is obtained and the trigger signal is determined to comprise a first low-level signal and a second low-level signal, continuously increasing the bit number of the M selection bits according to a preset increment until the trigger signal comprises a target high-level signal and a target low-level signal; when the trigger signal comprises the target high level signal and the target low level signal, the current bit number of the M selection bits is recorded as a target bit number, and the target level number of the delay unit corresponding to the target bit number is determined; the target phase of the first sampling clock signal in each delay of the target half period in the delay line is determined according to the target level number, and a target delay value of each delay unit is determined according to the target level number and the target frequency.

By adopting the technical scheme, the third sampling clock signal obtained by delaying the first sampling clock signal by the M-stage delay unit according to the first high-level signal is obtained. And simultaneously inputting the first sampling clock signal and the third sampling clock signal into the trigger device to acquire the trigger signal generated by the trigger device. When the trigger signal comprises a first low level signal and a second low level signal, the bit number of M selected bits is continuously increased according to a preset increment until the trigger signal comprises a target high level signal and a target low level signal, the current bit number of M selected bits is recorded as a target bit number, and the target level number of a delay unit corresponding to the target bit number is determined. And determining the target phase of the first sampling clock signal in each delay of the target half period in the delay line according to the target series, and determining the target delay value of each stage of delay unit according to the target series and the target frequency. By dynamically adjusting the select bits to achieve accurate adjustment of the delay of the clock signal, an accurately synchronized clock signal may be provided for subsequent data read operations.

Optionally, the selecting the M selected bits from the N selected bits in the target half period corresponding to the target phase in the second sampling clock signal, and adjusting the number of bits of the M selected bits in turn, so as to perform a data reading operation in different phases of the target half period after adjusting the number of bits of the M selected bits each time, which specifically includes: in a third half period corresponding to a third target phase in the inverted sampling clock signal, selecting M selected bits from the N selected bits, and adjusting the number of bits of the M selected bits in turn, wherein the second sampling clock signal comprises the inverted sampling clock signal, the first phase is delayed from the third target phase on the second sampling clock signal, the target half period comprises the third half period, and the first half period is delayed from the third half period on the second sampling clock signal; after each adjustment of the number of bits of the M selected bits, a data read operation is performed at a different phase of the third half cycle.

By adopting the technical scheme, the second sampling clock signal comprises the reverse sampling clock signal, and then M selected bits are selected from N selected bits in a third half period corresponding to a third target phase in the reverse sampling clock signal, and the number of bits of the M selected bits is adjusted in turn. After each adjustment of the number of M selected bits, the data reading operation is performed at a different phase of the third half cycle. More accurate control can be provided for the key moment of data reading so as to ensure the accuracy of capturing data at different phase points, and further improve the data reading efficiency and reliability.

Optionally, after the correct data is read from the first phase of the first half cycle, the bit number of the M selected bits corresponding to the first phase is recorded as a first adjustment bit number, which specifically includes: after the error data is read from the third target phase, selecting the M selection bits from the N selection bits in the first half period corresponding to the fourth target phase in a forward sampling clock signal, and adjusting the bit number of the M selection bits in turn, wherein the second sampling clock signal comprises the forward sampling clock signal, and the reverse sampling clock signal is an inverse clock signal of the forward sampling clock signal; after the number of bits of the M selection bits is adjusted each time, performing a data reading operation at different phases of the first half cycle; after the correct data is read at the first phase, continuing to adjust the bit number of the M selected bits until the correct data is read at the fourth target phase of the first half cycle; and recording the bit numbers of the M selection bits corresponding to the first phase as the first adjustment bit number.

By adopting the technical scheme, after the error data is read from the third target phase, the data reading operation is required to be continued at the moment, the second sampling clock signal comprises a forward sampling clock signal, and then M selected bits are selected from N selected bits in a first half period corresponding to the fourth target phase in the forward sampling clock signal, and the number of bits of the M selected bits is adjusted in turn. After each adjustment of the number of bits of the M selection bits, a data read operation is performed at different phases of the first half cycle. After the correct data is read at the first phase, the adjustment of the number of bits of the M selected bits is not stopped until the correct data can be read at the fourth target phase of the first half-cycle. After the above operation is completed, the number of bits of the M selection bits corresponding to the first phase is determined as the first adjustment bit number. Thereby ensuring the accuracy of reading data at different phase positions of the clock signal and further improving the reliability of data reading.

Optionally, after the error data is read from the second phase of the second half cycle, the bit number of the M selected bits corresponding to the second phase is recorded as a second adjustment bit number, which specifically includes: after the correct data is read from the fourth target phase, selecting M selected bits from the N selected bits in the second half period corresponding to the second target phase in the reverse sampling clock signal, and adjusting the number of bits of the M selected bits in turn; after each adjustment of the number of bits of the M selected bits, performing a data read operation at a different phase of the second half cycle; after the error data is read at the second phase, continuing to adjust the bit number of the M selected bits until the error data is read at the second target phase; and recording the bit numbers of the M selection bits corresponding to the second phase as the second adjustment bit number.

By adopting the technical scheme, after the correct data is read from the fourth target phase, M selection bits are selected from N selection bits in the second half period corresponding to the second target phase in the reverse sampling clock signal, and the number of bits of the M selection bits is adjusted in turn. After each adjustment of the number of bits of the M selection bits, a data read operation is performed at a different phase of the second half cycle. If erroneous data is read at the second phase, the adjustment of the number of bits of the M selected bits is not stopped until erroneous data is read at the second target phase. After the above operation is completed, the number of bits of the M selection bits corresponding to the second phase is defined as a second adjustment bit number. By fine adjustment, accuracy in data reading is improved.

Optionally, the determining the target clock phase according to the target delay value, the first adjustment bit number and the second adjustment bit number specifically includes: determining a first stage number of the delay unit corresponding to the first adjustment bit number, and determining a second stage number of the delay unit corresponding to the second adjustment bit number; and determining the target clock phase according to the target delay value, the first level and the second level.

Through adopting above-mentioned technical scheme, confirm the first progression of delay element that first adjustment digit corresponds to and confirm the second progression of delay element that second adjustment digit corresponds, can confirm the target clock phase more accurately according to first progression and second progression and target delay value, and can confirm accurate clock phase under the circumstances that environmental factor influences greatly through this mode, and then read data through this clock phase, can ensure clock phase and read data's stability under the circumstances of low pressure high temperature or high pressure low temperature.

Optionally, the determining the target clock phase according to the target delay value and the first stage number and the second stage number specifically includes: the target clock phase a is determined as follows:

a＝(b×d-c×d)÷2+c×d

Wherein b is the first number of stages, d is the target delay value, and c is the second number of stages.

By adopting the technical scheme, the target clock phase a can be calculated by substituting the first stage number b, the second stage number c and the target delay value d into a specific formula, namely, the flexibility of determining the target clock phase is ensured, and the clock phases required under different scenes can be obtained by adjusting the first stage number or the second stage number or the target delay value.

In a second aspect, an embodiment of the present application provides a clock phase determining apparatus, including: the first determining module is used for inputting a first sampling clock signal of a target frequency input by clock control equipment into a delay line after the first sampling clock signal is received, and selecting M selection bits from N selection bits in the delay line to determine that the M selection bits are first high-level signals provided by corresponding M-level delay units, wherein the N selection bits correspond to N+1-level delay units, and M is more than or equal to 2 and less than or equal to N; the second determining module is used for determining a target phase of each delay target half period of the first sampling clock signal in the delay line and a target delay value of each stage of delay unit according to the first sampling clock signal, the first high-level signal and the M stages of the M-stage delay unit; the acquisition module is used for acquiring a second sampling clock signal output by the delay line, wherein the second sampling clock signal is obtained by delaying the first sampling clock signal by the delay line; an execution module, configured to select the M selection bits from the N selection bits in the target half period corresponding to the target phase in the second sampling clock signal, and adjust the number of bits of the M selection bits in a round manner, so as to perform a data reading operation on different phases of the target half period after adjusting the number of bits of the M selection bits each time, where the target phase includes a plurality of phases, and the target half period is a difference value between any two adjacent phases of the plurality of phases; the first reading module is configured to record, as a first adjustment bit, a number of bits of the M selected bits corresponding to a first phase after correct data is read from the first phase of a first half cycle, where data read before the first phase is error data, and data read after the first phase and before a first target phase is correct data, where the first target phase is delayed from the first phase on the second sampling clock signal, the target phase includes the first target phase, and the target half cycle includes the first half cycle; the second reading module is configured to, after the error data is read from the second phase of the second half period, record the number of bits of the M selected bits corresponding to the second phase as a second adjustment bit number, where the data read after the second phase and before the second target phase are all error data, and the data read before the second phase and after the first phase are all correct data, where the second phase is delayed by the first target phase and the second target phase is delayed by the second phase on the second sampling clock signal, the target phase includes the second target phase, the target half period includes the second half period, and the second half period is delayed by the first half period on the second sampling clock signal; and a third determining module, configured to determine a target clock phase according to the target delay value, the first adjustment bit number and the second adjustment bit number.

In a third aspect, an embodiment of the present application provides an electronic device, including: one or more processors and memory; the memory is coupled with the one or more processors, the memory for storing computer program code comprising computer instructions that the one or more processors call to cause the electronic device to perform the method as described in the first aspect and any possible implementation of the first aspect.

In a fourth aspect, embodiments of the present application provide a computer readable storage medium comprising instructions which, when run on an electronic device, cause the electronic device to perform a method as described in the first aspect and any possible implementation of the first aspect.

One or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:

1. The technical problem that the stability of the data read by the sampling clock cannot be maintained under the condition that the influence of environmental factors is large in the related art is solved, and the technical effect of maintaining the stability of the data read by the sampling clock under the condition that the influence of the environmental factors is large is achieved.

2. By dynamically adjusting the select bits to achieve accurate adjustment of the delay of the clock signal, an accurately synchronized clock signal may be provided for subsequent data read operations.

3. More accurate control can be provided for the key moment of data reading so as to ensure the accuracy of capturing data at different phase points, and further improve the data reading efficiency and reliability.

Drawings

Fig. 1 is a flow chart of a method for determining clock phase according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a system architecture to which the clock phase determination method according to the embodiment of the present application is applicable;

FIG. 3 is an enlarged schematic view of a portion of a delay line in accordance with an embodiment of the present application;

FIG. 4 is an enlarged schematic diagram of a portion of a delay line and phase lock circuit in accordance with an embodiment of the present application;

FIG. 5 is a schematic diagram of a delay line and phase lock circuit according to an embodiment of the present application;

FIG. 6 is a second schematic diagram of waveforms of a delay line and a phase lock circuit according to an embodiment of the present application;

FIG. 7 is a schematic diagram of an optimal clock phase waveform in accordance with an embodiment of the present application;

FIG. 8 is a block diagram of a clock phase determining apparatus according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of an electronic device according to the disclosure.

Detailed Description

The terminology used in the following embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates to the contrary. It should also be understood that the term "and/or" as used in this disclosure is intended to encompass any or all possible combinations of one or more of the listed items.

The terms "first," "second," and the like, are used below for descriptive purposes only and are not to be construed as implying or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature, and in the description of embodiments of the application, unless otherwise indicated, the meaning of "a plurality" is two or more.

The application provides a method for determining clock phase, referring to fig. 1, fig. 1 is a flow chart of a method for determining clock phase according to an embodiment of the application, which comprises the following steps:

Step S101, after receiving a first sampling clock signal of a target frequency input by clock control equipment, inputting the first sampling clock signal into a delay line, and selecting M selection bits from N selection bits in the delay line to determine that the M selection bits are first high-level signals provided by corresponding M-level delay units, wherein the N selection bits correspond to N+1-level delay units, and the delay line comprises N selection bits and N+1-level delay units, and M is more than or equal to 2 and less than or equal to N;

Step S102, determining a target phase of each delay target half period of the first sampling clock signal in a delay line and a target delay value of each stage of delay unit according to the first sampling clock signal, the first high level signal and the M stages of delay units;

Step S103, a second sampling clock signal output by a delay line is obtained, wherein the second sampling clock signal is obtained by delaying the first sampling clock signal by the delay line;

Step S104, selecting M selection bits from N selection bits in a target half period corresponding to a target phase in the second sampling clock signal, and adjusting the number of bits of the M selection bits in turn so as to execute a data reading operation in different phases of the target half period after adjusting the number of bits of the M selection bits each time, wherein the target phase comprises a plurality of phases, and the target half period is a difference value between any two adjacent phases in the plurality of phases;

Step S105, after reading correct data from the first phase of the first half-period, counting the number of M selected bits corresponding to the first phase as a first adjustment bit number, wherein the data read before the first phase are all error data, and the data read after the first phase and before the first target phase are all correct data, the first target phase is delayed to the first phase on the second sampling clock signal, the target phase comprises the first target phase, and the target half-period comprises the first half-period; step S106, after the error data is read from the second phase of the second half period, the number of M selected bits corresponding to the second phase is recorded as a second adjustment bit number, wherein the data read after the second phase and before the second target phase are all error data, and the data read before the second phase and after the first phase are all correct data, the second phase is delayed at the first target phase and the second target phase is delayed at the second phase on the second sampling clock signal, the target phase comprises the second target phase, the target half period comprises the second half period, and the second half period is delayed at the first half period on the second sampling clock signal;

step S107, determining the target clock phase according to the target delay value, the first adjustment bit number and the second adjustment bit number.

In the above embodiments, the Clock control device includes, but is not limited to, a Phase-Locked Loop (PLL), an oscillator, a Real-Time Clock (RTC) module, a network Time protocol (Network Time Protocol, NTP) server, a Timer/Counter (Timer/Counter), a Clock distributor, and the like. The delay line includes n+1 stage delay units, each stage delay unit in the n+1 stage delay units has a selection bit, for example, when there are 3 stage delay units in the delay line, the 3 stage delay units have 3 selection bits, and the bits of the 3 selection bits are 0 selection bits, 1 selection bits, and 2 selection bits, respectively. When there are 5-stage delay units in the delay line, the 5-stage delay units have 5 selection bits, and the bits of the 5 selection bits are respectively 0 selection bits, 1 selection bits, 2 selection bits, 3 selection bits, 4 selection bits, and the like.

Through the steps, the received first sampling clock signal is input into the delay line, and M selection bits are selected from N selection bits in the delay line to determine that the M selection bits are the first high-level signal provided by the corresponding M-stage delay unit, so that the flexibility and the adaptability of delay configuration of the clock signal are ensured. And determining the target phase of each delay target half period of the first sampling clock signal in the delay line and the target delay value of each stage of delay unit according to the first sampling clock signal, the first high-level signal and the M stages of delay units. And obtaining a second sampling clock signal which is output by the delay line and is obtained by delaying the first sampling clock signal, wherein in the second sampling clock signal, data reading operation can be performed at different phases by adjusting the bit numbers of the selected M selected bits in a target half period corresponding to the target phase. So that after correctly reading data at the first phase of the first half cycle, the bit at this time can be set to the first adjustment bit number, and when erroneous data is read at the second phase of the second half cycle, the bit at this time can be set to the second adjustment bit number. And determining the target clock phase according to the target delay value, the first adjustment bit number and the second adjustment bit number. And the data can be read according to the target clock phase, so that the purpose that the stability of the data read by the sampling clock is not affected by temperature is realized. The technical problem that the stability of the data read by the sampling clock cannot be maintained under the condition that the influence of environmental factors is large in the related art is solved, and the technical effect of maintaining the stability of the data read by the sampling clock under the condition that the influence of the environmental factors is large is achieved.

The main body of execution of the above steps may be a system, for example, a high-speed clock control system, or a clock control device, for example, a phase lock loop, or a clock processing device, but is not limited thereto.

In an alternative embodiment, determining the target phase of the first sampling clock signal in the delay line and the target delay value of each stage of delay unit according to the first sampling clock signal, the first high level signal and the M-stage number of the M-stage delay unit specifically includes: acquiring a third sampling clock signal obtained by delaying the first sampling clock signal by the M-level delay unit according to the first high-level signal; inputting the first sampling clock signal and the third sampling clock signal into trigger equipment to acquire a trigger signal output by the trigger equipment; under the condition that the trigger signal is obtained and the trigger signal is determined to comprise a first low-level signal and a second low-level signal, continuously increasing the bit number of M selection bits according to a preset increment until the trigger signal comprises a target high-level signal and a target low-level signal; under the condition that the trigger signal comprises a target high-level signal and a target low-level signal, the bit number of the current M selection bits is recorded as a target bit number, and the target level number of the delay unit corresponding to the target bit number is determined; and determining the target phase of the first sampling clock signal in each delay target half period in the delay line according to the target series, and determining the target delay value of each stage of delay unit according to the target series and the target frequency.

In the above embodiments, it is assumed that a system requires precise delay control of the clock signal for high-speed data acquisition. The system is provided with a delay line which is composed of delay units connected with an N+1-level sequence, each level of delay unit is correspondingly provided with a bit of selection bit, and each level of delay unit can delay an input clock signal for a fixed time. The first sampling clock signal is a reference clock signal of the system. The first high level signal is a control signal that selects a bit to trigger the delay cell. The target phase of the first sampling clock signal in the delay line per delay target half period is determined by adjusting the number of bits of the selection bit. The method comprises the steps of obtaining a third sampling clock signal obtained by delaying a first sampling clock signal by an M-level delay unit according to a first high-level signal; simultaneously inputting the first sampling clock signal and the third sampling clock signal into a trigger device (e.g., a D-flip-flop, a T-flip-flop, etc., without limitation herein); acquiring a trigger signal output by trigger equipment; the number of bits of the M selected bits is adjusted by observing the level signal in the trigger signal, thereby adjusting the total delay of the delay line. Starting from a preset increment, continuously increasing the number of M selected bits until the trigger signal shows a target high level signal and a target low level signal (which means that the delay has been adjusted to the target phase); once the trigger signal comprises a target high level signal and a target low level signal, recording the number of bits of the current M selection bits as a target number of bits; determining a target level of the corresponding delay unit according to the target bit number, wherein the target level represents how many delay units are needed to realize the target phase; calculating a target delay value required by each stage of delay unit according to the target level number and the target frequency of the first sampling clock signal; by encoding the target number of bits into the logic controlling the delay line, the delay setting of the system is locked such that the third sampling clock signal can maintain a correct target phase relationship with the first sampling clock signal each time the first high level signal is triggered.

In an alternative embodiment, M selection bits are selected from the N selection bits in a target half period corresponding to the target phase in the second sampling clock signal, and the number of bits of the M selection bits is adjusted in turn, so that after each adjustment of the number of bits of the M selection bits, a data reading operation is performed at a different phase of the target half period, which specifically includes: in a third half period corresponding to a third target phase in the reverse sampling clock signal, selecting M optional bits from N optional bits, and adjusting the number of bits of the M optional bits in turn, wherein the second sampling clock signal comprises the reverse sampling clock signal, the first phase is delayed to the third target phase on the second sampling clock signal, the target half period comprises a third half period, and the first half period is delayed to the third half period on the second sampling clock signal; after each adjustment of the number of bits of the M selected bits, a data read operation is performed at a different phase of the third half cycle.

In the above embodiment, it is assumed that a digital storage oscilloscope is provided, and it is necessary to acquire digital signals at a specific phase angle. The digital storage oscilloscope uses an N-bit register in which N-bit select bits can be set to change the sampling instant. The second sampling clock signal is a delayed clock signal for controlling the data sampling time, data is collected in a third half period corresponding to a third target phase of the inverted sampling clock signal, and data can be collected at different phases. The method comprises the steps of obtaining a second sampling clock signal output by a delay line, and determining a third half period corresponding to a third target phase in a reverse sampling clock signal; optionally M selection bits from the N-bit register for adjusting the sampling instants; setting a bit pattern of the selected bits of the initial test to determine an initial sampling instant in the third half-cycle; starting a cycle, sequentially adjusting the bit numbers of the selected M selection bits, and immediately executing a data reading operation at different phases in the third half period of the inverted sampling clock signal after each adjustment; data reading may be accomplished by grabbing values on the digital signal lines; the number of bits of the M selected bits is continually adjusted in a round, and the data read operation is performed on the new phase after each adjustment. By varying the number of bits of the selection bits, fine-tuning the sampling instants is achieved so that data is acquired at different phase points of the half-cycle. Recording the data acquired by each data reading operation and the corresponding selection bit setting; analyzing the data to determine the phase characteristics of the clock signal; and determining the distribution characteristic of the data in the third half period through a plurality of bit number adjustment and data acquisition. In this embodiment, through fine control over the M selected bits, data may be collected at different phase points within a particular clock cycle to achieve the purpose of dynamically analyzing timing and testing signal integrity.

In an alternative embodiment, after the correct data is read from the first phase of the first half cycle, the number of bits of the M selection bits corresponding to the first phase is recorded as the first adjustment bit number, which specifically includes: after error data is read from the third target phase, selecting M optional bits from N optional bits in a first half period corresponding to a fourth target phase in a forward sampling clock signal, and adjusting the number of bits of the M optional bits in turn, wherein the second sampling clock signal comprises a forward sampling clock signal, and the reverse sampling clock signal is an inverse clock signal of the forward sampling clock signal; after the number of M selected bits is adjusted each time, performing a data reading operation at different phases of the first half cycle; after the correct data is read at the first phase, continuously adjusting the bit number of the M selected bits until the correct data is read at the fourth target phase of the first half period; and recording the bit numbers of M selected bits corresponding to the first phase as a first adjustment bit number.

In the above embodiment, it is assumed that a signal integrity test is required in one digital communication device, and the test process needs to capture data on different clock phases and adjust the sampling time according to the correctness of the captured data. Setting a forward sampling clock signal, and setting an N-bit selective bit register for controlling the time of data sampling; after error data is read at a third target phase in the reverse sampling clock signal, indicating that the sampling time needs to be adjusted; in the first half period of the forward sampling clock signal, selecting M optional selection bits from N selection bits, setting an initial bit mode, and starting the adjustment of sampling time; starting a cycle, sequentially adjusting the bit numbers of the selected M selection bits, and immediately executing a data reading operation at different phases in a first half period after each adjustment; after the correct data is read at the first phase position in the first half period, continuing to adjust M selection bits in turn until the correct data is read at the fourth target phase position in the first half period, stopping adjusting the selection bits, and recording the number of bits of the M selection bits corresponding to the first phase position as a first adjustment bit number; the number of bits of the corresponding M selected bits when the correct data is read at the fourth target phase may also be recorded. In this embodiment, each step is iterative, and it is necessary to verify whether the data is correct after each adjustment of the number of bits of the selected bits, and by this method, the optimal time for data acquisition can be found accurately.

In an alternative embodiment, after the error data is read from the second phase of the second half cycle, the number of M selected bits corresponding to the second phase is recorded as a second adjustment bit number, which specifically includes: after the correct data is read from the fourth target phase, selecting M selection bits from N selection bits in the second half period corresponding to the second target phase in the reverse sampling clock signal, and adjusting the number of bits of the M selection bits in turn; after the number of M selected bits is adjusted each time, performing a data reading operation at different phases of the second half period; after the error data is read at the second phase, continuously adjusting the bit number of the M selected bits until the error data is read at the second target phase; and recording the bit numbers of the M selection bits corresponding to the second phase as a second adjustment bit number.

In the above embodiment, it is assumed that a signal integrity test is required in one digital communication device, and the test process needs to capture data on different clock phases and adjust the sampling time according to the correctness of the captured data. Setting a reverse sampling clock signal, and setting an N-bit selective bit register for fine-tuning the time of data sampling; after the correct data is read from the fourth target phase, optionally selecting M selection bits from N selection bits in a second half period corresponding to the second target phase in the reverse sampling clock signal, and setting an initial bit mode; starting the adjustment of the sampling time; starting a cycle, sequentially adjusting the bit numbers of the selected M selection bits, and immediately executing a data reading operation at different phases in the second half period after each adjustment; after the error data is read at the second phase of the second half period, the bit number of the M selected bits is continuously adjusted until the bit number of the M selected bits corresponding to the second phase is recorded as a second adjustment bit number after the error data is read at the second target phase.

In an alternative embodiment, determining the target clock phase according to the target delay value, the first adjustment bit number and the second adjustment bit number specifically includes: determining a first series of delay units corresponding to the first adjustment digits and determining a second series of delay units corresponding to the second adjustment digits; and determining the target clock phase according to the target delay value, the first series and the second series.

In the above embodiment, when the first adjustment bit number includes sel [8], sel [9], where sel [8] is a selection bit with a bit number of 8, sel [9] is a selection bit with a bit number of 9, that is sel [8] is a 9 th selection bit, sel [9] is a10 th selection bit, the number of stages of the delay unit corresponding to sel [8] is determined as the first number of stages, that is, the delay unit corresponding to sel [8] has 9 stages, and the 9 stages are determined as the first number of stages; when the second adjustment bit number includes sel [44], sel [45], where sel [44] is a selection bit with a bit number of 44, sel [45] is a selection bit with a bit number of 45, that is sel [44] is a 45 th selection bit, sel [45] is a 46 th selection bit, the number of stages of the delay unit corresponding to sel [44] is determined as the second number of stages, that is, the delay unit corresponding to sel [44] has 45 stages, and the 45 stages are determined as the second number of stages. In addition, when the first adjustment bit number includes sel [26], sel [27], where sel [26] is a selection bit with a bit number of 26, sel [27] is a selection bit with a bit number of 27, that is sel [26] is a 27 th selection bit, sel [27] is a 28 th selection bit, the number of stages of the delay unit corresponding to sel [26] is determined as the first number of stages, that is, the delay unit corresponding to sel [26] has 27 stages, and the 27 stages are determined as the first number of stages; when the second adjustment bit number includes sel [100], sel [101], where sel [100] is a selection bit with a bit number of 100, sel [101] is a selection bit with a bit number of 101, that is sel [100] is a 101 th selection bit, sel [101] is a 102 th selection bit, the number of stages of the delay unit corresponding to sel [100] is determined as the second number of stages, that is sel [100] corresponds to a delay unit with 101 stages, the 101 stages are determined as the second number of stages, and so on. It should be noted that the illustration of the first adjustment bit number and the second adjustment bit number is only an exemplary embodiment, and the first adjustment bit number and the second adjustment bit number are not limited to the illustration.

In the above embodiments, it is assumed that a system requiring precise timing control ensures that the entire process from the sending of a signal from the master device to the receiving of the slave device, and finally back to the master device meets specific timing requirements. In this process, environmental factors may affect the clock phase, which in turn may affect the stability and accuracy of data transmission. However, the lock circuit is used for determining the target delay value of each stage of delay unit in the delay line, even if the influence of environmental factors is large, the target delay value of each stage of delay unit in the delay line can be accurately determined, so that the stability of reading data by adopting a clock is not influenced by temperature factors, and the first stage number of the delay unit corresponding to the first adjustment digit and the second stage number of the delay unit corresponding to the second adjustment digit are determined through testing. The first series, the second series and the target delay value are calculated to determine the optimal clock phase of the read data, and the clock signal can be finely adjusted to meet the accurate time sequence requirement of high-speed data communication.

In an alternative embodiment, determining the target clock phase according to the target delay value and the first and second stages specifically includes:

The target clock phase a is determined as follows:

a＝(b×d-c×d)÷2+c×d

Wherein b is the first series, d is the target delay value, and c is the second series.

In the above embodiment, when the first order is 50 orders (of course, 30 orders, 55 orders, 60 orders, etc., not limited thereto), the second order is 10 orders (of course, 15 orders, 20 orders, 25 orders, etc., not limited thereto), and the target delay value is 50ps (of course, 100ps, 150ps, 200ps, etc., not limited thereto), the target clock phase is a= (50×50-10×50)/(2+10×50), that is, the target clock phase is 1500ps. It should be noted that, the examples of the first level, the second level, and the target delay value are only exemplary embodiments, and the first level, the second level, and the target delay value are not limited to the examples.

It will be apparent that the embodiments described above are merely some, but not all, embodiments of the application. The present application will be specifically described with reference to the following examples.

Fig. 2 is a schematic structural diagram of a system architecture to which the clock phase determining method according to the embodiment of the present application is applicable, and referring to fig. 2, the system includes:

The data read DELAY of the operated CHIP (i.e. SLAVE_CHIP before 104) is delayed (i.e. SLAVE_CHIP_RDATA_DELAY before 104), i.e. when the main CHIP reads data through the serial communication interface (Quad SERIAL PERIPHERAL INTERFACE, QSPI) the data return of the operated CHIP to the main CHIP is delayed.

Between the main chip DATA pins (i.e., DATA_PAD [3:0] between 105-106), between 105-106 are 4 DATA pins on the main chip that have a delay.

The Input data path delays (i.e., input_data_path_delay between 106-108), and between 106-108 are the delays of the main chip pin to the read register's line and combinational logic.

A phase locked loop (i.e., a PLL before 100) for generating a clock of the correct frequency.

And an inverter for inverting the clock between 100 and 101.

A Multiplexer (MUX) between 100/101 and 102 is a 2-to-1 selector.

The Clock tree (Clock tree), 102, starts all the register clocks under the Clock tree with the same delay.

An asynchronous First-In-First-Out Module (Asynchronous First-In-First-Out Module, which may be abbreviated as async_fifo) has a write clock domain at 116 output with a regulated delay value and a read clock domain at 115 output to async_fifo.

A delay line (delay_line), a flexibly configurable delay line, the delay value of which needs to exceed a half period (corresponding to the upper target half period).

Fig. 3 is a schematic diagram of a local amplification of a delay line in an embodiment of the present application, referring to fig. 3, fig. 3 is a schematic diagram of a local amplification of a delay line between 115 and 116 in fig. 2, where the delay line includes 128 delay units (DELAY ELEMENT), each small granularity delay unit is composed of 1 in-phase buffer (DELAY CELL), 1 inverter and 3 nand gates, the control selection bit (sel) has 128 bits, and each delay unit controls the delay condition by the bit number of sel. When there is a small granularity of sel [ x ] =1, the delay cells following the x bits are bypassed, and the delay value of the delay line is equal to the sum of the delay values of all delay cells before the 2 nd sel [ x ] =1. To save power consumption, it is ensured that the logic in the following delay cells is not flipped, and two sel [ y ] = 1 are set as a group, for example sel [0] = 1, sel [1] = 1 next to sel [0] = 1, the other sel [ y ] are all 0, for example sel [80] = 1, sel [81] = 1 next to sel [80] = 1, the other sel [ y ] are all 0, and x and y are the number of bits of sel.

A phase LOCK circuit (LOCK) performs LOCK control on a half cycle (corresponding to the target half cycle).

Fig. 4 is a schematic diagram of a delay line and a phase LOCK circuit in an embodiment of the present application, referring to fig. 4, fig. 4 is a schematic diagram of a delay_line and a LOCK between 115 to 116 in fig. 2, and the delay value of each small particle delay unit is calculated by the phase LOCK circuit:

in stage 1, fig. 5 is a schematic diagram of waveforms of a delay line and a phase-locked circuit according to an embodiment of the present application, referring to fig. 5, when the number of bits of sel of the delay line is small, after a clock signal at 115 passes through the delay line, the waveform of the clock signal at 116 is a bit more delayed than the waveform of the clock signal at 115, after the clock signal at 116 passes through an in-phase buffer, the waveform of the clock signal at 117 is a bit more delayed than the waveform of the clock signal at 116, and at this time, both the outputs 118 and 119 of the multi-bit trigger register are 0;

Stage 2: fig. 6 is a schematic diagram of waveforms of a delay line and a phase-locked circuit according to the embodiment of the present application, referring to fig. 6, when the number of bits of sel of the delay line is always becoming larger, after a clock signal at 115 passes through the delay line, the waveform of the clock signal at 116 is delayed a little more than the waveform of the clock signal at 115, after the clock signal at 116 passes through an in-phase buffer, the waveform of the clock signal at 117 is delayed a little more than the waveform of the clock signal at 116, at this time, the output 118 of the multi-bit trigger register is 0 and 119 is 1, at this time, the number of bits of the current sel is recorded, at this time, the number of stages of delay units corresponding to the number of bits of the current sel is the time delay of half period, the input frequency (corresponding to the target frequency) is known, the clock period is determined by the input frequency, and the number of stages divided by half of the clock period is used to obtain the delay value of each stage of delay units.

The embodiment of the application also provides a process for determining the optimal clock phase (corresponding to the target clock phase), which comprises the following steps:

The testing process comprises the following steps:

1. DELAY LINE SEL =1, controller ctl [0] =1 at 102;

2. A central processing unit (Central Processing Unit, which may be referred to simply as a CPU) controls a QSPI main control interface (master IP) to transmit a test command to a slave control interface (slave IP), which transmits known data to the main control interface;

3. the CPU confirms whether the data in the static random access memory (Static Random Access Memory, which can be simply called SRAM) is correct;

4. CPU records DELAY LINE SEL =0, ctl [0] =0, read data correct or incorrect.

Fig. 7 is a schematic diagram of an optimal clock phase waveform in an embodiment of the present application, referring to fig. 7, under a normal pressure room temperature application scenario, assuming that the clock frequency is 200Mhz, the clock period is 5ns (t 1 to t2 are 2500 ps), sel [50] =1, sel [51] =1 when the clock passes through 51-stage delay units, the delay value of each stage delay unit is 50ps, the D0 DATA slice and the D1 DATA slice may respectively include 4bit DATA (i.e. respectively include DATA 0 to 3), and of course, the D0 DATA slice and the D1 DATA slice may also respectively include 8bit DATA, 16bit DATA, 32bit DATA, and the like, which are not limited herein, and the following is specifically:

1. reverse sampling clock t 1-t 2 stage: the controller ctl [0] =1 (providing the inverse sampling clock) at 102, capture_count=0 (t 1 to t4 are 1 st sampling clock), change the number of bits of sel from sel [0] =1, sel [1] =1 round, and each time the number of bits of sel is changed, the steps 2, 3, 4 in the test are cyclically executed:

The reverse sampling clock delay value at the position of sel [0] =1, sel [1] =1, sel [2] =sel [127] =0, t1 is 50ps (the delay bypasses the delay unit of sel bit with the 2 nd being 1, namely bypasses the delay unit of sel [1] bit), and steps 2, 3 and 4 in the test process are circularly executed, and the data error is read at the moment;

The reverse sampling clock delay value at the position of sel [0] -sel [1] =0, sel [2] =1, sel [3] =1, sel [4] -sel [127] =0, t1 is 150ps (the delay bypasses the sel bit with the 2 nd 1, namely bypasses the delay unit of the sel [3] bit, and the similar operation is the same as the subsequent processing), and steps 2, 3 and 4 in the test process are circularly executed, and the data is wrong at the moment;

……

the reverse sampling clock delay value at the position of sel [0] to sel [49] =0, sel [50] =1, sel [51] =1, sel [52] to sel [127] =0, and t1 is 2500ps cycle to execute steps 2,3 and 4 in the test process, and the data is wrong, and the time is the time delay of the reverse sampling clock edge to the position of t 2.

2. Forward sampling clocks t2 to t 4: the controller at 102 ctl [0] =0 (providing the forward sampling clock), capture_count=0 (t 1 to t4 are 1 st sampling clock), sel [0] =1, sel [1] =1 start to change the number of bits of sel in a round, and each time the number of bits of sel is changed, steps 2, 3, 4 in the test are performed in a loop:

The phase changes are continuous through the operation, and the phase changes are continuous before and after the sampling clock takes the reverse position.

The reverse sampling clock delay value at the position of sel [0] =1, el [1] =1, sel [2] -sel [127] =0, t2 is 50ps, and steps 2, 3 and 4 in the test process are circularly executed, and at the moment, data errors are read;

The forward sampling clock delay value at the position of sel [0] -sel [1] =0, sel [2] =1, sel [3] =1, sel [4] -sel [127] =0, t2 is 150ps, steps 2,3 and 4 in the test process are circularly executed, and data errors are read at the moment;

……

The forward sampling clock delay value at the position of sel [0] -sel [19] =0, sel [20] =1, sel [21] =1, sel [22] -sel [127] =0 and t2 is 1000ps, and steps 2, 3 and 4 in the test process are circularly executed, and the data is wrong at the moment;

The forward sampling clock delay value at the position of sel [0] -sel [21] =0, sel [22] =1, sel [23] =1, sel [24] -sel [127] =0, t2 is 1100ps, steps 2,3 and 4 in the test process are circularly executed, the data are correct, the time is the time when the forward sampling clock edge is delayed to the position t3, the data are read in error before the time t3, and the data are read in correct after the time t 3;

……

The forward sampling clock delay value at the position of sel [0] -sel [49] =0, sel [50] =1, sel [51] =1, sel [52] -sel [127] =0, t2 is 2500ps, steps 2,3 and 4 in the test process are circularly executed, the data are correct, and the time is the forward sampling clock edge delay to the position t 4;

3. In the phase t 4-t 6 of the reverse sampling clock, the controller ctl [0] =1 (providing the reverse sampling clock), the capture_count=1 (t 4-t 7 is the 2 nd sampling clock), sel [0] =1, sel [1] =1 starts to change the number of bits of sel in turn, and each time the number of bits of sel is changed, steps 2, 3, 4 in the test process are circularly executed:

The reverse sampling clock delay value at the position of sel [0] =1, sel [1] =1, sel [2] -sel [127] =0 and t4 is 50ps, and steps 2,3 and 4 in the test process are circularly executed, and the read data are correct at the moment;

The reverse sampling clock delay value at the position of sel [0] -sel [1] =0, sel [2] =1, sel [3] =1, sel [4] -sel [127] =0 and t4 is 150ps, and steps 2,3 and 4 in the test process are circularly executed, and the read data are correct at the moment;

……

the reverse sampling clock delay value at the position of sel [0] -sel [49] =0, sel [50] =1, sel [51] =1, sel [52] -sel [127] =0, t4 is 2500ps, steps 2,3 and 4 in the test process are circularly executed, the data are correct, and the time is the time when the reverse sampling clock edge is delayed to the position of t6

4. Forward sampling clock t 6-t 7: the controller at 102 ctl [0] =0 (providing the forward sampling clock), capture_count=1 (t 4-t 7 are the 2 nd sampling clock), sel [0] =1, sel [1] =1 starts to change the number of bits of sel in a round, and steps 2, 3, 4 in the test are performed in a loop every time the number of bits of sel is changed once:

The forward sampling clock delay value at the position of sel [0] =1, sel [1] =1, sel [2] -sel [127] =0 and t6 is 50ps, and steps 2,3 and 4 in the test process are circularly executed, and the read data are correct at the moment;

The forward sampling clock delay value at the position of sel [0] -sel [1] =0, sel [2] =1, sel [3] =1, sel [4] -sel [127] =0 and t6 is 150ps, and steps 2, 3 and 4 in the test process are circularly executed, and the read data are correct at the moment;

……

The forward sampling clock delay value at the position of sel [0] -sel [49] =0, sel [50] =1, sel [51] =1, sel [52] -sel [127] =0, t6 is 2500ps, steps 2,3 and 4 in the test process are circularly executed, the data are correct, and the time is the forward sampling clock edge delay to the position of t 7;

5. The inverse sampling clock t 7-t 9 stage, the controller ctl [0] =1 (providing the inverse sampling clock) at 102, capture_count=2 (t 4-t 7 is the 3 rd sampling clock), sel [0] =1, sel [1] =1 starts to change the number of bits of sel in turn, and steps 2, 3, 4 in the test are executed in a loop each time the number of bits of sel is changed:

The reverse sampling clock delay value at the position of sel [0] =1, sel [1] =1, sel [2] -sel [127] =0 and t7 is 50ps, and steps 2,3 and 4 in the test process are circularly executed, and the read data are correct at the moment;

the reverse sampling clock delay value at the position of sel [0] -sel [1] =0, sel [2] =1, sel [3] =1, sel [4] -sel [127] =0 and t7 is 150ps, and steps 2, 3 and 4 in the test process are circularly executed, and the read data are correct at the moment;

……

The reverse sampling clock delay value at the position of sel [0] -sel [5] =0, sel [6] =1, sel [7] =1, sel [8] -sel [127] =0 and t7 is 300ps, and steps 2, 3 and 4 in the test process are circularly executed, and the data are correct at the moment;

the reverse sampling clock delay value at the position of sel [0] -sel [7] =0, sel [8] =1, sel [9] =1, sel [10] -sel [127] =0, and t7 is 400ps, steps 2,3 and 4 in the test process are circularly executed, the data is wrong, the time is the time when the reverse sampling clock edge is delayed to the position of t8, the data is correct before the time of t8, and the data is wrong after the time of t 8;

……

The reverse sampling clock delay value at the position of sel [0] -sel [49] =0, sel [50] =1, sel [51] =1, sel [52] -sel [127] =0, t7 is 2500ps, steps 2,3 and 4 in the test process are circularly executed, the data is wrong, and the time is the time when the reverse sampling clock edge is delayed to the position t 9;

The optimal clock phase is calculated as time t5 by

When the time delay at t7 is sel [50] ×4, namely 50-level×50ps×4, wherein 4 is 4 half-period delay between t0 and t 7; when the time delay at t8 is sel [50 ]. Times.4+sel [6], namely 50-level×50ps×4+6-level×50, wherein sel [6] is the time delay between t7 and t 8;

when t2 is sel [50 ]. Times.1, it is 50 level. Times.50 ps. Times.1;

when t3 is sel [50] ×1+sel [22], namely 50-level×50ps×1+22-level×50, wherein sel [22] is the time delay between t2 and t 3;

the last time t5 is near the controller ctl [0] =1, the capture_count=1 (t 4 to t7 are the 2 nd sampling clocks), sel [39] =1, sel [40] =1 at 102.

In the embodiment of the application, the delay value of each stage of delay unit is determined by adjusting the delay unit with small granularity, and the stability of data reading by the sampling clock can be effectively ensured under the condition of larger influence of environmental factors by combining the adjustment of the clock edge with large granularity, so that the aim of reading and writing data at high speed is fulfilled.

The determination of the clock phase in the embodiment of the present application is described above, and the determination device of the clock phase in the embodiment of the present application is described in detail below in conjunction with the determination of the clock phase, referring to fig. 8, fig. 8 is a block diagram of a structure of the determination device of the clock phase provided in the embodiment of the present application, where the device includes:

A first determining module 801, configured to, after receiving a first sampling clock signal of a target frequency input by a clock control device, input the first sampling clock signal into a delay line, and select M selection bits from N selection bits in the delay line to determine that the M selection bits are first high-level signals provided by corresponding M-level delay units, where the N selection bits correspond to n+1-level delay units, and M is greater than or equal to 2 and less than or equal to N;

A second determining module 802, configured to determine, according to the first sampling clock signal, the first high level signal, and the M-level number of the M-level delay unit, a target phase of each delay target half cycle of the first sampling clock signal in the delay line and a target delay value of each level delay unit;

The obtaining module 803 is configured to obtain a second sampling clock signal output by the delay line, where the second sampling clock signal is obtained by delaying the first sampling clock signal by the delay line;

An execution module 804, configured to select M selection bits from the N selection bits in a target half period corresponding to a target phase in the second sampling clock signal, and adjust the number of bits of the M selection bits in a round manner, so as to perform a data reading operation on different phases of the target half period after adjusting the number of bits of the M selection bits each time, where the target phase includes a plurality of phases, and the target half period is a difference value between any two adjacent phases of the plurality of phases;

A first reading module 805, configured to, after reading correct data from a first phase of a first half cycle, count a number of bits of M selected bits corresponding to the first phase as a first adjustment bit number, where the data read before the first phase are all error data, and the data read after the first phase and before a first target phase are all correct data, where the first target phase is delayed from the first phase on a second sampling clock signal, the target phase includes the first target phase, and the target half cycle includes the first half cycle;

A second reading module 806, configured to, after the error data is read from the second phase of the second half period, record the number of M selected bits corresponding to the second phase as a second adjustment bit number, where the data read after the second phase and before the second target phase are all error data, and the data read before the second phase and after the first phase are all correct data, where the second phase is delayed by the first target phase and the second target phase is delayed by the second phase on the second sampling clock signal, the target phase includes the second target phase, the target half period includes the second half period, and the second half period is delayed by the first half period on the second sampling clock signal;

a third determining module 807 for determining a target clock phase based on the target delay value and the first adjustment bit number and the second adjustment bit number.

In an alternative embodiment, the second determining module 802 includes: the first acquisition unit is used for acquiring a third sampling clock signal obtained by delaying the first sampling clock signal according to the first high-level signal by the M-level delay unit; the second acquisition unit is used for inputting the first sampling clock signal and the third sampling clock signal into the trigger equipment so as to acquire the trigger signal output by the trigger equipment; the first processing unit is used for continuously increasing the bit number of M selection bits according to a preset increment until the trigger signal comprises a target high-level signal and a target low-level signal under the condition that the trigger signal is acquired and the trigger signal is determined to comprise a first low-level signal and a second low-level signal; a first determining unit, configured to, when the trigger signal includes a target high level signal and a target low level signal, record a current number of bits of the M selection bits as a target number of bits, and determine a target number of stages of the delay unit corresponding to the target number of bits; and the second determining unit is used for determining the target phase of the first sampling clock signal in each delay target half period in the delay line according to the target level number and determining the target delay value of each level of delay unit according to the target level number and the target frequency.

In an alternative embodiment, the executing module 804 includes: the first adjusting unit is configured to select M selection bits from the N selection bits in a third half period corresponding to a third target phase in the inverted sampling clock signal, and adjust the number of bits to the M selection bits in a round manner, where the second sampling clock signal includes the inverted sampling clock signal, the first phase is delayed from the third target phase on the second sampling clock signal, the target half period includes the third half period, and the first half period is delayed from the third half period on the second sampling clock signal; the first execution unit is used for executing one data reading operation at different phases of the third half period after adjusting the bit number of the M selection bits each time.

In an alternative embodiment, the first reading module 805 includes: the second adjusting unit is used for selecting M optional bits from N optional bits in a first half period corresponding to a fourth target phase in the forward sampling clock signal after error data are read from the third target phase, and adjusting the number of bits of the M optional bits in turn, wherein the second sampling clock signal comprises a forward sampling clock signal and a reverse sampling clock signal is an inverse clock signal of the forward sampling clock signal; a second execution unit for executing a data read operation at different phases of the first half cycle after each adjustment of the number of bits of the M selection bits; the third adjusting unit is used for continuously adjusting the bit number of the M selection bits after the correct data is read at the first phase until the correct data is read at the fourth target phase of the first half period; the second processing unit is used for recording the bit numbers of the M selection bits corresponding to the first phase as a first adjustment bit number.

In an alternative embodiment, the second reading module 806 includes: a fourth adjustment unit, configured to, after reading the correct data from the fourth target phase, select M selection bits from the N selection bits in the second half period corresponding to the second target phase in the inverted sampling clock signal, and adjust the number of bits to the M selection bits in a round; a third execution unit for executing a data reading operation at different phases of the second half period after each adjustment of the number of bits of the M selection bits; a fifth adjusting unit, configured to continue adjusting the number of bits of the M selected bits after the error data is read at the second phase until the error data is read at the second target phase; and the third processing unit is used for recording the bit numbers of the M selection bits corresponding to the second phase as a second adjustment bit number.

In an alternative embodiment, the third determining module 807 includes: the third determining unit is used for determining a first series of delay units corresponding to the first adjusting digits and determining a second series of delay units corresponding to the second adjusting digits; and the fourth determining unit is used for determining the target clock phase according to the target delay value, the first series and the second series.

In an alternative embodiment, the fourth determining unit includes: a determining subunit, configured to determine the target clock phase a according to the following formula:

a＝(b×d-c×d)÷2+c×d

The application also discloses an electronic device, referring to fig. 9, fig. 9 is a schematic structural diagram of the electronic device according to the embodiment of the application. The electronic device 900 may include: at least one processor 901, at least one network interface 904, a user interface 903, memory 905, at least one communication bus 902.

Wherein a communication bus 902 is employed to facilitate a coupled communication between the components.

The user interface 903 may include a Display screen (Display) and a Camera (Camera), and the optional user interface 903 may further include a standard wired interface and a wireless interface.

The network interface 904 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others.

Processor 901 may include one or more processing cores, among other things. The processor 901 connects various portions of the overall electronic device (e.g., server) using various interfaces and lines, performs various functions of the server and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 905, and invoking data stored in the memory 905. Alternatively, the processor 901 may be implemented in at least one hardware form of digital signal Processing (DIGITAL SIGNAL Processing, DSP), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 901 may integrate one or a combination of several of a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), and a modem, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It will be appreciated that the modem may not be integrated into the processor 901 and may be implemented by a single chip.

The Memory 905 may include a random access Memory (Random Access Memory, RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 905 includes a non-transitory computer readable medium (non-transitory computer-readable storage medium). The memory 905 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 905 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the above-described respective method embodiments, etc.; the storage data area may store data or the like involved in the above respective method embodiments. The memory 905 may also optionally be at least one storage device located remotely from the processor 901. Referring to fig. 9, an operating system, a network communication module, a user interface module, and an application program of a method of determining a clock phase may be included in the memory 905 as a computer storage medium.

In the electronic device 900 shown in fig. 9, the user interface 903 is mainly used for providing an input interface for a user, and acquiring data input by the user; and processor 901 may be used to invoke an application of a method of determining clock phase stored in memory 905, which when executed by one or more processors 901, causes electronic device 900 to perform the method as described in one or more of the embodiments above. It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all of the preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.

The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

As used in the above embodiments, the term "when …" may be interpreted to mean "if …" or "after …" or "in response to determination …" or "in response to detection …" depending on the context. Similarly, the phrase "at the time of determination …" or "if detected (a stated condition or event)" may be interpreted to mean "if determined …" or "in response to determination …" or "at the time of detection (a stated condition or event)" or "in response to detection (a stated condition or event)" depending on the context.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk), etc.

Those of ordinary skill in the art will appreciate that implementing all or part of the above-described method embodiments may be accomplished by a computer program to instruct related hardware, the program may be stored in a computer readable storage medium, and the program may include the above-described method embodiments when executed. And the aforementioned storage medium includes: ROM or random access memory RAM, magnetic or optical disk, etc.

Claims

1. A method for determining a clock phase, comprising:

After a first sampling clock signal of a target frequency input by clock control equipment is received, inputting the first sampling clock signal into a delay line, and selecting M selection bits from N-bit selection bits in the delay line to determine that the M selection bits are first high-level signals provided by corresponding M-level delay units, wherein the N-bit selection bits correspond to N+1-level delay units, and the delay line comprises the N-bit selection bits and the N+1-level delay units, wherein M is more than or equal to 2 and less than or equal to N;

Determining a target phase of each delay target half period of the first sampling clock signal in the delay line and a target delay value of each stage of delay unit according to the first sampling clock signal, the first high-level signal and the M stages of delay units;

acquiring a second sampling clock signal output by the delay line, wherein the second sampling clock signal is obtained by delaying the first sampling clock signal by the delay line;

optionally selecting the M selection bits from the N selection bits in the target half period corresponding to the target phase in the second sampling clock signal, and adjusting the bit number of the M selection bits in turn so as to execute a data reading operation in different phases of the target half period after adjusting the bit number of the M selection bits each time, wherein the target phase comprises a plurality of phases, and the target half period is a difference value between any two adjacent phases in the plurality of phases;

After correct data is read from a first phase of a first half period, recording the bit numbers of the M selected bits corresponding to the first phase as a first adjustment bit number, wherein the data read before the first phase are all error data, and the data read after the first phase and before a first target phase are all correct data, the first target phase is delayed from the first phase on the second sampling clock signal, the target phase comprises the first target phase, and the target half period comprises the first half period;

After error data is read from a second phase of a second half period, and the number of bits of the M selected bits corresponding to the second phase is recorded as a second adjustment bit number, wherein the data read after the second phase and before a second target phase are all error data, and the data read before the second phase and after the first phase are all correct data, the second phase is delayed at the first target phase and the second target phase is delayed at the second phase on the second sampling clock signal, the target phase comprises the second target phase, the target half period comprises a second half period, and the second half period is delayed at the first half period on the second sampling clock signal;

And determining a target clock phase according to the target delay value, the first adjustment bit number and the second adjustment bit number.

2. The method according to claim 1, wherein determining the target phase of the first sampling clock signal per delay target half period and the target delay value of each stage of delay unit in the delay line according to the first sampling clock signal, the first high level signal and the M-stage number of M-stage delay units specifically comprises:

acquiring a third sampling clock signal obtained by delaying the first sampling clock signal by the M-stage delay unit according to the first high-level signal;

Inputting the first sampling clock signal and the third sampling clock signal into a trigger device to acquire a trigger signal output by the trigger device;

Under the condition that the trigger signal is acquired and the trigger signal is determined to comprise a first low-level signal and a second low-level signal, continuously increasing the bit number of the M selection bits according to a preset increment until the trigger signal comprises a target high-level signal and a target low-level signal;

If the trigger signal includes the target high level signal and the target low level signal, recording the current number of bits of the M selection bits as a target number of bits, and determining a target level of the delay unit corresponding to the target number of bits;

And determining the target phase of the first sampling clock signal in the delay line every time delay of the target half period according to the target level number, and determining a target delay value of the delay unit of each level according to the target level number and the target frequency.

3. The method according to claim 1, wherein the selecting the M selected bits from the N selected bits in the target half period corresponding to the target phase in the second sampling clock signal, and adjusting the number of bits of the M selected bits in turn, to perform a data reading operation in a different phase of the target half period after each adjustment of the number of bits of the M selected bits, comprises:

In a third half period corresponding to a third target phase in the inverted sampling clock signal, selecting M selection bits from the N selection bits, and adjusting the number of bits of the M selection bits in turn, wherein the second sampling clock signal comprises the inverted sampling clock signal, the first phase is delayed from the third target phase on the second sampling clock signal, the target half period comprises the third half period, and the first half period is delayed from the third half period on the second sampling clock signal;

after each adjustment of the number of bits of the M selected bits, a data read operation is performed at a different phase of the third half cycle.

4. The method of claim 3, wherein after the correct data is read from the first phase of the first half cycle, the bit number of the M selected bits corresponding to the first phase is recorded as a first adjustment bit number, and specifically comprising:

After the error data is read from the third target phase, selecting the M selection bits from the N selection bits in the first half period corresponding to a fourth target phase in a forward sampling clock signal, and adjusting the bit number of the M selection bits in turn, wherein the second sampling clock signal comprises the forward sampling clock signal, and the reverse sampling clock signal is an inverse clock signal of the forward sampling clock signal;

After each adjustment of the number of bits of the M selection bits, performing a data read operation at different phases of the first half cycle;

after the correct data is read at the first phase, continuing to adjust the bit number of the M selected bits until the correct data is read at the fourth target phase of the first half cycle;

and recording the bit numbers of the M selection bits corresponding to the first phase as the first adjustment bit number.

5. The method of claim 4, wherein after the error data is read from the second phase of the second half cycle, the number of bits of the M selected bits corresponding to the second phase is recorded as a second adjustment bit number, and specifically comprising: after the correct data is read from the fourth target phase, optionally selecting the M selection bits from the N selection bits in the second half period corresponding to the second target phase in the reverse sampling clock signal, and adjusting the number of bits of the M selection bits in turn;

after each adjustment of the number of bits of the M selection bits, performing a data read operation at a different phase of the second half cycle;

After the error data is read at the second phase, continuing to adjust the bit number of the M selected bits until the error data is read at the second target phase;

And recording the bit numbers of the M selection bits corresponding to the second phase as the second adjustment bit number.

6. The method according to claim 1, wherein said determining a target clock phase from said target delay value and said first adjustment bit number and said second adjustment bit number, comprises:

Determining a first series of delay units corresponding to the first adjustment digits and determining a second series of delay units corresponding to the second adjustment digits;

and determining the target clock phase according to the target delay value, the first stage number and the second stage number.

7. The method according to claim 6, wherein said determining said target clock phase from said target delay value and said first number of stages and said second number of stages, comprises:

The target clock phase a is determined as follows:

a＝(b×d-c×d)÷2+c×d

8. A clock phase determining apparatus, comprising:

The first determining module is used for inputting a first sampling clock signal of a target frequency input by clock control equipment into a delay line after the first sampling clock signal is received, and selecting M selection bits from N selection bits in the delay line to determine that the M selection bits are first high-level signals provided by corresponding M-level delay units, wherein the N selection bits correspond to N+1-level delay units, and M is more than or equal to 2 and less than or equal to N;

The second determining module is used for determining a target phase of each delay target half period of the first sampling clock signal in the delay line and a target delay value of each stage of delay unit according to the first sampling clock signal, the first high-level signal and the M stages of the M-stage delay units;

the acquisition module is used for acquiring a second sampling clock signal output by the delay line, wherein the second sampling clock signal is obtained by delaying the first sampling clock signal by the delay line;

An execution module, configured to select the M selection bits from the N selection bits in the target half period corresponding to the target phase in the second sampling clock signal, and adjust the number of bits of the M selection bits in a round manner, so as to perform a data reading operation on different phases of the target half period after adjusting the number of bits of the M selection bits each time, where the target phase includes a plurality of phases, and the target half period is a difference value between any two adjacent phases of the plurality of phases;

A first reading module, configured to record, as a first adjustment bit number, a bit number of the M selected bits corresponding to a first phase after correct data is read from the first phase of a first half cycle, where data read before the first phase is error data, and data read after the first phase and before a first target phase is correct data, where the first target phase is delayed from the first phase on the second sampling clock signal, the target phase includes the first target phase, and the target half cycle includes the first half cycle;

A second reading module, configured to, after error data is read from a second phase of a second half period, record, as a second adjustment bit number, a bit number of the M selected bits corresponding to the second phase, where the data read after the second phase and before a second target phase are all error data, and the data read before the second phase and after the first phase are all correct data, where the second phase is delayed by the first target phase and the second target phase is delayed by the second phase on the second sampling clock signal, the target phase includes the second target phase, and the target half period includes a second half period, where the second half period is delayed by the first half period on the second sampling clock signal;

And a third determining module, configured to determine a target clock phase according to the target delay value, the first adjustment bit number and the second adjustment bit number.

9. An electronic device, comprising: one or more processors and memory;

The memory is coupled with the one or more processors, the memory for storing computer program code comprising computer instructions that the one or more processors invoke to cause the electronic device to perform the method of any of claims 1-7.

10. A computer readable storage medium comprising instructions which, when run on an electronic device, cause the electronic device to perform the method of any of claims 1-7.