CN117955626A - Sampling rate conversion method, device, chip and medium - Google Patents

Abstract

The application discloses a sampling rate conversion method, a sampling rate conversion device, a sampling rate conversion chip and a sampling rate conversion medium, and relates to the field of signal sampling processing. The method comprises the following steps: converting a signal to be processed with the sampling rate being the original sampling rate into n parallel signals through a first filter, wherein n is a positive integer not less than 2; converting a first parallel signal with a first sampling rate into a first conversion signal with a second sampling rate in the n parallel signals through a converter, wherein the original sampling rate is n times of the first sampling rate; the first converted signal is converted by the second filter into a first output signal having a sampling rate that is n times the second sampling rate.

Description

Sampling rate conversion method, device, chip and medium

Technical Field

The present application relates to the field of signal sampling processing, and in particular, to a sampling rate conversion method, apparatus, chip, and medium.

Background

In the wireless communication process, the receiver or the transmitter needs to convert the sampling frequency of the signal to the corresponding operating frequency, and at this time, sampling rate conversion is needed. In which, at different frequency points, there are also different accuracy requirements for sample rate conversion.

With the gradual increase in wireless bandwidth (e.g., 320 bandwidth), sampling rate conversion would require the use of higher speed clocks or the use of a greater number of clocks to meet sampling requirements. But this will lead to increased performance requirements for the converter or to an increased number of clocks, multipliers, adders, which results in a more difficult implementation of sample rate conversion at large bandwidths.

Disclosure of Invention

The embodiment of the application provides a sampling rate conversion method, a sampling rate conversion device, a sampling rate conversion chip and a sampling rate conversion medium, which can reduce the implementation difficulty of sampling rate conversion. The technical scheme is as follows:

according to an aspect of the present application, there is provided a sample rate conversion method, the method comprising:

Converting a signal to be processed with the sampling rate being the original sampling rate into n parallel signals through a first filter, wherein n is a positive integer not less than 2;

Converting a first parallel signal with a first sampling rate into a first conversion signal with a second sampling rate in the n parallel signals through a converter, wherein the original sampling rate is n times of the first sampling rate;

the first converted signal is converted by the second filter into a first output signal having a sampling rate that is n times the second sampling rate.

According to an aspect of the present application, there is provided a sample rate conversion apparatus comprising:

the signal processing module is configured to convert a signal to be processed with the sampling rate being the original sampling rate into n parallel signals, wherein n is a positive integer not less than 2;

A sampling rate conversion module configured to convert a first parallel signal of the n parallel signals having a sampling rate of a first sampling rate into a first converted signal of a sampling rate of a second sampling rate, the original sampling rate being n times the first sampling rate;

The signal processing module is further configured to convert the first converted signal into a first output signal having a sampling rate that is n times the second sampling rate.

According to an aspect of the present application, there is provided a chip comprising: a first filter, a converter and a second filter, the chip being for implementing the sample rate conversion method as described above.

According to an aspect of the present application, there is provided a receiver comprising the chip described above.

According to an aspect of the present application, there is provided a transmitter including the above chip.

According to one aspect of the present application, there is provided a computer device comprising a memory and a processor; at least one program code is stored in the memory, and the program code is loaded into and executed by the processor to implement the sample rate conversion method as described above.

According to an aspect of the present application, there is provided a computer readable storage medium having stored therein a computer program for execution by a processor to implement the sample rate conversion method as described above.

According to one aspect of the application, there is provided a chip comprising a processor for implementing a sample rate conversion method as described above.

According to one aspect of the present application, there is provided a computer program product comprising computer instructions stored in a computer readable storage medium, the computer instructions being read from the computer readable storage medium and executed by a processor to implement a sample rate conversion method as described above.

The technical scheme provided by the embodiment of the application has the beneficial effects that at least:

The parallel division of the signals to be processed is performed, and the converter processes only one of the parallel signals, so that the processing capacity of the converter is reduced, the performance requirement of the converter is reduced, and the number of clocks, multipliers and adders can be reduced; the first output signal with the third sampling rate output by the second filter can ensure that the sampling rate conversion of the signal to be processed can still meet the precision requirement.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of one implementation of sample rate conversion provided by an exemplary embodiment of the present application;

FIG. 2 is a schematic diagram of another implementation of sample rate conversion provided by an exemplary embodiment of the present application;

FIG. 3 is a schematic diagram of an implementation of a sample rate conversion method according to an exemplary embodiment of the present application;

FIG. 4 is a flow chart of a sample rate conversion method provided by an exemplary embodiment of the present application;

FIG. 5 is a flow chart of a sample rate conversion method provided by an exemplary embodiment of the present application;

FIG. 6 is a schematic diagram of a chip provided in an exemplary embodiment of the application;

fig. 7 is a schematic diagram of a receiver provided by an exemplary embodiment of the present application;

FIG. 8 is a schematic diagram of a transmitter provided by an exemplary embodiment of the present application;

FIG. 9 is a schematic diagram of a sample rate conversion apparatus according to an exemplary embodiment of the present application;

fig. 10 shows a schematic structural diagram of a communication device according to an exemplary embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

The sampling rate conversion refers to increasing or decreasing the number of sampling points in a unit time under the condition of ensuring that the signal quality is unchanged. Sample rates are important in digital signal processing in wireless communication systems.

In the wireless communication process, the receiver or the transmitter needs to convert the sampling frequency of the signal to the corresponding operating frequency, and at this time, sampling rate conversion is needed. In which, at different frequency points, there are also different accuracy requirements for sample rate conversion.

For the receiver, when the digital signal is processed in the receiving system, the operating frequency of the receiving digital processing system often does not coincide with the sampling frequency of the signal itself due to different processing requirements. In order for the system to operate properly in synchronization, the receiver needs to convert the sampling rate of the digital signal to the operating frequency of the receiving digital processing system. For example, in a Wireless-Fidelity (Wi-Fi) receiver, a Variable Sampling Rate Converter (VSRC) may be used to sample the received signal for bias correction. Wherein the VSRC is used to convert input samples at one sampling rate to output samples at another sampling rate.

For transmitters, an orthogonal frequency division multiple access (Orthogonal Frequency Division Multiple Access, OFDMA) mechanism was introduced in the last few years communication protocols. When all Resource Units (RU) sent by the wireless terminal device (Station, STA) are required to reach the wireless Access Point (AP), the frequencies and the sampling rates are aligned, and at this time, the receiver of the AP does not make frequency and sampling rate compensation. This requires the transmitter to also implement the pre-compensation function of frequency and sampling rate. Illustratively, calculating with the accuracy required by the protocol.+ -. 350Hz, the accuracy required at the 7GHz frequency is up to.+ -. 0.05ppm, which would present a high challenge for VSRC.

Illustratively, the VSRC needs to operate at a sampling rate of at least 2 times the signal bandwidth. In one implementation scenario, wi-Fi7 out of the last few years supports up to 320M bandwidth, which requires a higher speed clock. For example, in the context of high-speed circuits, when the input signal is 320M bandwidth of Wi-Fi7 channel bandwidth (Channel Bandwidth, CBW), the sampling rate of the 320M signal is typically 640M. Based on this, the VSRC may operate at 2 times or 4 times the signal bandwidth for sample rate conversion.

In light of the foregoing, there is a certain accuracy requirement for sample rate conversion, which is typically set by the value of the error vector magnitude (Error Vector Magnitude, EVM), which is an important parameter for measuring signal quality.

Illustratively, table 1 shows a simulated evaluation of EVM, taking a sampling frequency of 320MHz for the signal to be processed, and an up-sampling filter taking a 2-fold up-sampling (determinable based on the nyquist sampling theorem) as an example.

TABLE 1

Wherein, when VSRC works at 1280M, which is 4 times overdriven, evm= -58.169dB; when VSRC is operating at 2-fold overdriving, 640M, evm= -35.357dB. Illustratively, 1kQAM requires an EVM of at least less than-35 dB, where the 2-fold oversampled EVM is near the threshold; while 4kQAM requires an EVM of at least less than-38 dB, the 2-fold over-sampled EVM is insufficient, and 4-fold over-sampled EVM is required.

It can be seen that in the 320M bandwidth scenario, the processing speed of the VSRC is as high as 1280M/S, i.e., 1280M signal sampling points need to be determined per second, if the EVM requirement is to be satisfied.

With the increasing wireless bandwidth (e.g., 320 bandwidth supported in WiFi 7), the sampling rate conversion would require the use of higher speed clocks or the use of a greater number of clocks to meet the sampling requirements. But this will lead to increased performance requirements for the converter or to an increased number of clocks, multipliers, adders, which results in a more difficult implementation of sample rate conversion at large bandwidths.

Based on this, two solutions are given in the related art: FIG. 1 illustrates a schematic diagram of one implementation of sample rate conversion provided by an exemplary embodiment of the present application; fig. 2 shows another implementation of sample rate conversion provided by an exemplary embodiment of the present application.

Taking the sampling frequency of the signal to be processed as 320MHz, the filter takes as an example 2 times as the upper sampling:

Referring to fig. 1, the input signal to be processed has a sampling frequency of 320MHz, and based on 2-fold up sampling, the sampling rate of the 320M signal is typically 640M (determined by the nyquist sampling theorem), and the 640M signal is input to the filter. In order to meet the EVM requirement, the VSRC needs to work in an environment of 4 times overdriving (4 times of the signal to be processed), that is, the filter outputs 1280M signals to the VSRC, the single-path VSRC completes the determination of sampling points of the 1280M signals, and the processed 1280M signals are output to other processors for subsequent processing.

Based on the sample rate conversion approach shown in fig. 1, this would result in the VSRC requiring a higher speed clock due to the processing speed of the VSRC requiring up to 1280M/S. Meanwhile, high-speed processing based on VSRC will cause timing to be difficult to converge.

Referring to fig. 2, the sampling frequency of the signal to be processed is 320MHz, and based on 2-fold up sampling, the sampling rate of the 320M signal is typically 640M, and the 640M signal is input to the filter. In order to reduce the requirement on the clock performance and meet the requirement on the EVM, the 1280M signal to be processed output by the filter can be divided into two parallel paths of signals, and the two paths of signals are respectively processed by the first VSRC and the second VSRC. The first VSRC and the second VSRC respectively complete the determination of sampling points of 640M signals, and output the processed 640M signals to other processors for subsequent processing.

Based on this, the sample rate conversion approach shown in fig. 2 can reduce the processing speed of a single VSRC to some extent, thereby reducing the demand on clock performance. However, each VSRC requires multiple multipliers or adders, such as farrow filter structures, which require at least 4 multipliers for this type of filter, and at least 8 multipliers for a parallel 2-way VSRC. In this way, the number of multipliers or adders is increased, resulting in an increase in the area, volume, and cost of a chip, receiver, transmitter, or other device that performs sample rate conversion.

With reference to the foregoing, the two sampling rate conversion methods cannot meet the throughput requirement and the accuracy requirement of the converter at the same time.

The application provides a sampling rate conversion method which can simultaneously meet the processing capacity requirement of a converter and the precision requirement. Fig. 3 is a schematic diagram illustrating an implementation of the sample rate conversion method according to an exemplary embodiment of the present application.

Still taking the sampling frequency of the signal to be processed as 320MHz, the first filter takes the example of 2 times up:

Based on the 2-fold up-sampling, a 640M signal is input to the first filter. To meet the EVM requirement, the VSRC needs to operate in a 4-fold overdriving (4-fold of the signal to be processed) environment, it being understood that the VSRC actually needs to process 1280M of the signal. Meanwhile, to reduce the processing capacity of the VSRC, the first filter divides 1280M signals into two paths of parallel signals to be transmitted to the VSRC, and each path of parallel signals has 640M bandwidth.

Then, the VSRC only processes one of the parallel signals, that is, the VSRC only needs to complete the determination of the sampling point of one 640M signal, and outputs the processed 640M signal to the second filter, and the second filter recovers the sampling rate of 1280M signal, and determines the sampling point of 1280M bandwidth accordingly. Which is then transmitted to other processors for subsequent processing.

Based on the above, the parallel division of the signals to be processed by the first filter and the processing of the converter on only one of the plurality of parallel signals reduces the processing capacity of the converter, thereby reducing the performance requirement of the converter (as can be understood, the processing capacity requirement of only a single VSRC needs to be met), and reducing the number of clocks, multipliers and adders; the output signal with the third sampling rate output by the second filter can ensure that the sampling rate conversion of the signal to be processed can still meet the precision requirement.

Wherein it should be understood that the 320M signal to be processed referred to in the foregoing example refers to an original signal, and the sampling frequency may be determined based on the nyquist sampling theorem when the original signal is sampled. Illustratively, the signal is uniformly sampled at a rate that exceeds at least twice the highest frequency of the original signal. Based on this, 640M and 1280M referred to in the foregoing example can both be understood as bandwidth rates to distinguish from the 320M bandwidth.

Alternatively, referring to the foregoing, the sample rate conversion method provided by the embodiments of the present application may be performed by a chip, a receiver, a transmitter, or other devices, and the method may be applied to the receiver and/or the transmitter or other devices.

Fig. 4 shows a flowchart of a sample rate conversion method according to an exemplary embodiment of the present application, the method comprising the steps of:

Step 102: the signal to be processed with the sampling rate being the original sampling rate is divided into n parallel signals by a first filter.

Wherein n is a positive integer not less than 2.

It should be understood that the signal to be processed refers to the original digital signal or raw signal that needs to be processed, and that the sampling frequency of the signal that is ultimately input to the first filter may be multiple times the sampling frequency, such as up-sampling by twice as determined according to the nyquist sampling theorem. Where the sampling frequency is the original sampling rate of the signal to be processed (or signal frequency of the signal to be processed is understood). Referring to fig. 3, taking the sampling frequency of the signal to be processed as 320MHz as an example, based on 2-fold upsampling, the signal with 640M bandwidth finally input into the first filter can also be understood as the bandwidth rate of the processing performed by the first filter is 640M.

During signal processing, the first filter may be up-sampled or down-sampled, i.e. the first filter is an up-sampled filter or a filter is to be employed. The sampling multiple of the first filter may be an integer or a fraction. In some embodiments, the first filter performs 2-fold up-sampling, or 3-fold up-sampling, or 4-fold up-sampling, or other integer-fold up-sampling; in other embodiments, the first filter performs 2.5 times upsampling, or 3.5 times upsampling, or other fractional upsampling.

It should be appreciated that the signal to be processed is divided by the first filter by an integer multiple, whether the sampling multiple of the first filter is an integer or a fraction.

The signal divided by the first filter in integer multiple is the sum of analog signals corresponding to the signal to be processed under the condition that the sampling requirement is met, and the sampling requirement can be set according to actual needs. In some embodiments, the sampling requirement is used to indicate that the EVM requirement is met when the signal to be processed is sampled. For example, if the sampling frequency of the signal to be processed is 320MHz, the sampling requirement is that the EVM is at least less than-38 dB, and the bandwidth of the signal input to the converter by the first filter is 1280M (the sum of analog signals under the sampling requirement is satisfied), which can be understood as that the bandwidth rate of the processing performed by the converter is 1280M.

For example, the signal to be processed is 320M, the first filter performs 4 times up sampling, the sum of analog signals required to perform parallel signal division is 1280M, the first filter may divide the signal to be processed of 12800M into n parallel signals, and n may be 2,3,4, 5 or other positive integers. For another example, the signal to be processed is still 320M, the first filter performs 3.5 times up sampling, the sum of analog signals required to perform parallel signal division is still 1280M, the first filter may divide the signal to be processed of 1280M into n parallel signals, and n may be 2,3,4, 5 or other positive integers.

Illustratively, step 102 may be implemented as follows:

Dividing a signal to be processed into 2 parallel signals through a first filter;

Or dividing the signal to be processed into 3 parallel signals through a first filter;

or the signal to be processed is split into 4 parallel signals by the first filter.

To process the signal to be processed, the first filter should be in circuit connection with the converter. The converter is used for carrying out sampling rate conversion processing on the signal to be processed.

It should be appreciated that the signal to be processed is split into n parallel signals based on the first filter, there should be n parallel circuits between the first filter and the converter. For example, in the case that the sampling frequency of the signal to be processed is 320MHz, the signal to be processed can be divided into 2, or 3, or 4 parallel signals by the first filter, and there should be 2, or 3, or 4 parallel circuits between the first filter and the previous.

Step 104: a first parallel signal with a first sampling rate of the n parallel signals is converted into a first converted signal with a second sampling rate by a converter.

Illustratively, the original sampling rate is n times the first sampling rate.

The original sampling rate is also understood to be the signal frequency of the signal to be processed. Based on the division of the parallel signals by the signal to be processed, the sampling rate of the first parallel signal should be one n-th of the sampling rate of the signal to be processed, i.e. the first sampling rate is one n-th of the original sampling rate.

In some embodiments, step 104 may also be implemented as: and carrying out sampling rate conversion processing on a first parallel signal with a first sampling rate in the n parallel signals through a converter to obtain a first converted signal with a second sampling rate.

The converter is used for carrying out sampling rate conversion processing on the signal to be processed transmitted by the first filter. The sampling rate conversion process refers to converting the sampling frequency of the signal to be processed to a corresponding operating frequency, which may also be understood as the sampling rate at which the signal to be processed is sampled.

It should be understood that the sample rate conversion is to convert the signal frequency of the original signal to the operating frequency at which the signal sampling process is performed. Based on this, the bandwidths of the first parallel signal and the first converted signal can be understood as two signals of the same bandwidth but with different sampling rates. That is, the first sampling rate and the second sampling rate are two different sampling rates.

Illustratively, the converter is a VSRC.

With reference to the foregoing, the first filter divides the signal to be processed into n parallel signals, so as to reduce the performance requirement of the converter, reduce the processing capacity of the converter, and only perform frequent sample rate conversion processing on the first parallel signal of the n parallel signals, where the sample rate after conversion of other parallel signals of the n parallel signals is the same as the sample rate after conversion of the first parallel signal, which can be used as a reference.

Wherein the first parallel signal may be any one of n parallel signals.

Optionally, the first parallel signal is a first parallel signal of the n parallel signals; or the first parallel signal is the last parallel signal of the n parallel signals; or the first parallel signal is a preset parallel signal in the n parallel signals; or the first parallel signal is any one of the n parallel signals.

It should be understood that after the converter performs sampling rate conversion processing on any one of the n parallel signals (i.e., the first parallel signal), a first converted signal may be obtained, where the second sampling rate corresponding to the first converted signal is one-nth of the sampling rate required for sampling the signal to be processed. Based on this, it can also be understood that the sampling rate obtained by performing the sampling rate conversion processing on the signal to be processed is n times the second sampling rate.

Step 106: the first converted signal is converted into a first output signal with a sampling rate of a third sampling rate by a second filter.

Illustratively, the third sampling rate is n times the second sampling rate.

With reference to the foregoing, the second sampling rate of the first converted signal is one-nth of the sampling rate required for sampling the signal to be processed. In order for the sample rate conversion to meet the accuracy requirement (i.e., EVM), the first converted signal is input to a second filter, thereby recovering the sample rate of the signal to be processed. The recovery of the sampling rate of the signal to be processed refers to obtaining the sampling rate of sampling the signal to be processed through processing of the first conversion signal, and thus obtaining the third sampling rate.

The second filter may be an up-sampling filter or a down-sampling filter, similar to the first filter. Optionally, the first filter and the second filter are of the same type. That is, the first filter and the second filter are both up-sampling filters, or the first filter and the second filter are both down-sampling filters.

The recovery of the sampling rate by the second filter may be understood as multiplying the sampling rate by n times based on the second sampling rate, thereby obtaining the sampling rate of the signal to be processed. After determining the third sampling rate, the second filter may determine sampling points of the output signal based on the sampling rate. The output signal is understood to be a signal having a third sampling rate, the output signal having the same bandwidth as the sum of the analog signals of the parallel signal division by the first filter.

Optionally, the third sampling rate is equal to an operating frequency of a processing system that samples the first output signal. The processing system may be a transmitter, a receiver, a chip or other devices capable of implementing the sample rate conversion method provided by the present application, or the processing system may be a chip, a transmitter, a receiver or other systems included in the devices capable of implementing the sample rate conversion method provided by the embodiments of the present application. Referring to fig. 3, the processing system may be some component located after the second filter.

In summary, according to the sampling rate conversion method provided by the embodiment of the application, the parallel division of the signals to be processed is performed, and the converter processes only one of the parallel signals, so that the processing capacity of the converter is reduced, the performance requirement of the converter is reduced, and the number of clocks, multipliers and adders can be reduced; the output signal with the third sampling rate output by the second filter can ensure that the sampling rate conversion of the signal to be processed can still meet the precision requirement.

Based on fig. 4, fig. 5 shows a flowchart of a sample rate conversion method according to an exemplary embodiment of the present application, which preferably includes step 108, specifically as follows:

Step 108: according to the third sampling rate, a sampling point of the first output signal is determined.

The determining of the third sampling rate may refer to the foregoing, and will not be described herein.

After the third sampling rate is determined, a sampling point for the first output signal may be determined therefrom, which may be determined by the second filter, or by other devices or components. For example, the second filter sends the third sampling rate to the component for sampling the signal, which component enables the determination of the sampling point.

Referring to fig. 3, taking the sampling frequency of the signal to be processed as 320MHz, the first filter takes 2 times as an example, the sampling rate conversion method provided by the embodiment of the present application may be implemented as follows:

Based on the 2-fold up-sampling, 640M of the signal to be processed is input to the first filter. To meet the EVM requirement, the VSRC needs to operate in a 4-fold overdraw environment, i.e., the total bandwidth of the signal output by the first filter should be 1280M (or understood as the bandwidth rate at which the converter processes is 1280M/S).

To reduce the processing capacity of the converter, the first filter divides the 1280M signal into two parallel signals, and each parallel signal has a bandwidth of 640M, and transmits the parallel signals to the converter. Wherein the converter is a VSRC.

Then, the VSRC only processes one of the parallel signals, that is, the VSRC only needs to complete the determination of the sampling point of the signal of one path 640M, and outputs the processed signal of 640M (that is, the first converted signal) to the second filter. The one parallel signal (i.e., the first parallel signal) selected by the VSRC may be any one of two parallel signals output by the first filter.

Based on the received processed 640M signal, the second filter may recover 1280M signal sample rate and determine 1280M bandwidth signal sample points based thereon (sample points on the other 640M signal may be referenced to the determined sample points on the processed 640M). It will be appreciated that after the sample rate of a signal is determined, the sample point of the first output signal may be determined based on the sample rate and the signal bandwidth.

Which is then transmitted to other processors for subsequent processing.

Based on this, table 2 shows a simulated evaluation of EVM.

TABLE 2

Referring to tables 1 and 2, taking 320MHz as an example of the sampling frequency of the signal to be processed, the EVM loss is about 0.6dB by adopting the sampling rate conversion method provided by the application, and the overall EVM is still less than-56 dB. Therefore, by adopting the sampling rate conversion method provided by the application, the converter can still keep better performance, so that the use of Wi-Fi6 and Wi-Fi7 can be satisfied.

Based on this, it is known from the EVM simulation results in table 2 that the performance of VSRC is not degraded or the loss of EVM is negligible. Meanwhile, after the second filter is used, a real multiplier is not needed in the second filter, so that a chip or equipment for executing the method is simple and convenient in design and low in manufacturing cost.

It should be appreciated that in the context of high-speed circuits, the clock used by the VSRC is reduced in a parallel manner (i.e., the signal division process by the first filter); in parallel processing, VSRC only needs to realize one path, so that half of sampling points can be obtained; then, the number of sampling points is doubled by a second filter, so that a finally needed sampling point signal is obtained.

Based on this, taking two paths of parallel signals as an example, compared with the sampling rate conversion mode shown in fig. 2, the sampling rate conversion method provided by the embodiment of the application can obtain the following advantages:

(1) One path is deleted by two paths in parallel, and only one path is needed to be realized, so that the complexity and the realization difficulty of the circuit are reduced; (2) The multiplier, adder and the like used by the VSRC are half of the original ones, which is equivalent to the area of a chip or equipment for executing the method, and the power consumption can be saved by half; (3) The processing clock of VSRC is doubled, making timing easy to converge.

In summary, in the sample rate conversion method provided by the embodiment of the present application, a specific processing manner of the converter and the second filter on the first parallel signal is provided, and recovery of the sample rate of the sample processing of the signal to be processed can be achieved through the second filter by means of the second sample rate, so that it is ensured that the sample rate conversion of the signal to be processed still can meet the precision requirement.

Referring to the foregoing, the sample rate conversion method provided by the embodiment of the present application may be performed by a chip, and fig. 6 shows a schematic diagram of the chip provided by an exemplary embodiment of the present application.

Illustratively, the chip includes a first filter, a converter, and a second filter, the chip being configured to implement the sample rate conversion method described above. The foregoing may be referred to for the sample rate conversion method, and will not be described herein.

In some embodiments, the first filter and the second filter are of the same type, such as both up-sampling filters, or both down-sampling filters.

In some embodiments, the converter is a VSRC.

Optionally, referring to fig. 6, the first filter is connected with the converter through n parallel circuits to achieve n times division of the signal to be processed; the converter is connected with the second filter through a single circuit. For example, the first filter is connected with the converter through two parallel circuits, so that the signal to be processed is divided into two parallel signals; for another example, the first filter and the converter are connected through three paths of parallel circuits, so that the signal to be processed is divided into three parallel signals.

Based on the converter processing a first parallel signal of the n parallel signals, the converter and the second filter can be connected through a single circuit, so that the processed first parallel signal can be transmitted to the second filter.

With reference to the foregoing, the sample rate conversion method provided by the embodiment of the present application may be applied to a receiver and/or a transmitter. Based on this, in some embodiments, the present application also provides a receiver, including the chip as described above, and fig. 7 shows a schematic diagram of the receiver provided by an exemplary embodiment of the present application. In other embodiments, the present application also provides a transmitter including a chip as described above, and fig. 8 shows a schematic diagram of a transmitter provided in an exemplary embodiment of the present application.

It should be appreciated that the above chip may also be referred to as a sample rate conversion chip.

Referring to fig. 7, the chip is connected to the first processor, and after the sample rate conversion is completed, the chip informs the first processor of the determined sampling point, and the first processor performs subsequent signal processing, such as signal sampling, according to the determined sampling point. Referring to fig. 8, the chip is connected to the second processor, and after the sample rate conversion is completed, the chip informs the second processor of the determined sample point, and the second processor performs subsequent signal processing, such as pre-compensation of the signal sample rate, according to the determined sample point.

The following is an embodiment of the device according to the present application, and details of the embodiment of the device that are not described in detail may be combined with corresponding descriptions in the embodiment of the method described above, which are not described herein again.

Fig. 9 shows a schematic diagram of a sample rate conversion apparatus according to an exemplary embodiment of the present application, the apparatus includes:

A signal processing module 920 configured to convert a signal to be processed having a sampling rate of an original sampling rate into n parallel signals, n being a positive integer not less than 2;

a sampling rate conversion module 940 configured to convert a first parallel signal of the n parallel signals having a sampling rate of a first sampling rate into a first converted signal of a sampling rate of a second sampling rate, the original sampling rate being n times the first sampling rate;

The signal processing module 920 is further configured to convert the first converted signal into a first output signal having a sampling rate that is n times the second sampling rate.

Optionally, the sampling rate of the signal to be processed is n times the sampling rate of the first parallel signal after processing.

Optionally, the first parallel signal is a first parallel signal of the n parallel signals; or the first parallel signal is the last parallel signal of the n parallel signals; or the first parallel signal is a preset parallel signal in the n parallel signals; or the first parallel signal is any one of the n parallel signals.

Optionally, the signal processing module 920 is further configured to determine a sampling point of the first output signal according to the third sampling rate.

Optionally, the signal processing module 920 is configured to divide the signal to be processed into 2 parallel signals; or dividing the signal to be processed into 3 parallel signals; or divide the signal to be processed into 4 parallel signals.

Optionally, the first filter and the second filter are of the same type.

Optionally, the first filter and/or the second filter is one of the following: an up-sampling filter; a downsampling filter.

Optionally, the converter is a VSRC.

Optionally, the apparatus is applied in a receiver and/or a transmitter.

Fig. 10 is a schematic structural diagram of a communication device (any bluetooth device) according to an exemplary embodiment of the present application, where the communication device includes: a processor 1001, a receiver 1002, a transmitter 1003, a memory 1004, and a bus 1005.

The processor 1001 includes one or more processing cores, and the processor 1001 executes various functional applications and information processing by running software programs and modules.

The receiver 1002 and the transmitter 1003 may be implemented as one communication component, which may be a communication chip.

The memory 1004 is connected to the processor 1001 through a bus 1005.

The memory 1004 may be used for storing at least one instruction, which the processor 1001 is configured to execute to implement the steps of the sample rate conversion method mentioned in the above method embodiment.

Further, the memory 1004 may be implemented by any type of volatile or nonvolatile storage device or combination thereof, including but not limited to: magnetic or optical disk, electrically erasable programmable Read-Only Memory (EEPROM), erasable programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM), static random access Memory (Static Random Access Memory, SRAM), read-Only Memory (ROM), magnetic Memory, flash Memory, programmable Read-Only Memory (Programmable Read-Only Memory, PROM).

The application also provides a computer device comprising a memory and a processor; at least one program code is stored in the memory, and the program code is loaded into and executed by the processor to implement the sample rate conversion method as described above.

The present application also provides a computer readable storage medium having stored therein a computer program for execution by a processor to implement a sample rate conversion method as described above.

The application also provides a chip comprising a processor for implementing the sample rate conversion method as described above.

The present application also provides a computer program product comprising computer instructions stored in a computer readable storage medium, the computer instructions being read from the computer readable storage medium and executed by a processor to implement the sample rate conversion method as described above.

It should be understood that references herein to "a plurality" are to two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

The foregoing description of the preferred embodiments of the present application is not intended to limit the application, but rather, the application is to be construed as limited to the appended claims.

Claims (20)

1. A sample rate conversion method, the method comprising:

Converting a signal to be processed with the sampling rate being the original sampling rate into n parallel signals through a first filter, wherein n is a positive integer not less than 2;

converting a first parallel signal with a first sampling rate from the n parallel signals into a first converted signal with a second sampling rate by a sampling rate converter, wherein the original sampling rate is n times of the first sampling rate;

The first converted signal is converted by a second filter into a first output signal having a third sampling rate, which is n times the second sampling rate.

2. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The third sampling rate is equal to an operating frequency of a processing system that samples the first output signal.

3. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The first parallel signal is a first parallel signal of the n parallel signals;

or the first parallel signal is the last parallel signal of the n parallel signals;

or the first parallel signal is a preset parallel signal in the n parallel signals;

or the first parallel signal is any one of the n parallel signals.

4. A method according to any one of claims 1 to 3, wherein the method further comprises:

and determining the sampling point of the first output signal according to the third sampling rate.

5. A method according to any one of claims 1 to 3, wherein,

The first filter and the second filter are of the same type.

6. A method according to any one of claims 1 to 3, wherein the first filter and/or the second filter is one of the following filters:

An up-sampling filter;

A downsampling filter.

7. A method according to any one of claims 1 to 3, wherein,

The converter is a variable sample rate converter VSRC.

8. A sample rate conversion apparatus, the apparatus comprising:

The signal processing module is configured to convert a signal to be processed with the sampling rate being the original sampling rate into n parallel signals, wherein n is a positive integer not less than 2;

A sampling rate conversion module configured to convert a first parallel signal of the n parallel signals having a first sampling rate into a first converted signal having a second sampling rate, the original sampling rate being n times the first sampling rate;

the signal processing module is further configured to convert the first converted signal into a first output signal having a sampling rate that is n times the second sampling rate.

9. The apparatus of claim 8, wherein the device comprises a plurality of sensors,

The third sampling rate is equal to an operating frequency of a processing system that samples the first output signal.

10. The apparatus of claim 8, wherein the device comprises a plurality of sensors,

The first parallel signal is a first parallel signal of the n parallel signals;

or the first parallel signal is the last parallel signal of the n parallel signals;

or the first parallel signal is a preset parallel signal in the n parallel signals;

or the first parallel signal is any one of the n parallel signals.

11. The device according to any one of claims 8 to 10, wherein,

The signal processing module is further configured to determine a sampling point of the first output signal according to the third sampling rate.

12. The device according to any one of claims 8 to 10, wherein,

The device is applied to a receiver and/or a transmitter.

13. A chip, the chip comprising: a first filter, a converter and a second filter, the chip being adapted to implement the sample rate conversion method according to any one of claims 1 to 10.

14. The chip of claim 13, wherein the chip further comprises a plurality of chips,

The first filter is connected with the converter through n paths of parallel circuits;

The converter is connected with the second filter through a single circuit.

15. A receiver comprising a chip as claimed in claim 13 or 14.

16. A transmitter comprising a chip as claimed in claim 13 or 14.

17. A computer device, the computer device comprising a memory and a processor;

At least one program code is stored in the memory, which is loaded and executed by the processor to implement the sample rate conversion method of any one of claims 1 to 7.

18. A computer readable storage medium, characterized in that the storage medium has stored therein a computer program for execution by a processor to implement the sample rate conversion method of any one of claims 1 to 7.

19. A chip comprising a processor for implementing the sample rate conversion method of any one of claims 1 to 7.

20. A computer program product comprising computer instructions stored in a computer readable storage medium, the computer instructions being read from the computer readable storage medium and executed by a processor to implement the sample rate conversion method of any one of claims 1 to 7.