CN117955470A

CN117955470A - Output buffer circuit, display driver, data driver and display device

Info

Publication number: CN117955470A
Application number: CN202311372381.1A
Authority: CN
Inventors: 土弘
Original assignee: Lanbishi Technology Co ltd
Current assignee: Lanbishi Technology Co ltd
Priority date: 2022-10-31
Filing date: 2023-10-23
Publication date: 2024-04-30

Abstract

The invention provides an output buffer circuit, a display driver, a data driver and a display device which can realize area saving under the condition of adopting a multi-output structure. The invention comprises: a first transistor that supplies a first high-voltage power supply voltage to an output terminal when the first transistor is turned on in response to a voltage of an input signal received by a gate; a second transistor that supplies a second high-voltage power supply voltage to the output terminal when the second transistor is turned on in response to a voltage of an input signal received by the gate; an output control unit that, when the voltage of the input signal changes, changes the gate voltage of the transistor in the on state of the first transistor and the second transistor to the off state, and changes the gate voltage of the transistor in the off state to the on state at a rate of change based on the current value controlled by the bias voltage; and a bias modulation unit that sets the voltage value of the bias voltage to a predetermined voltage value.

Description

Output buffer circuit, display driver, data driver and display device

Technical Field

The present invention relates to an output buffer circuit for driving a load, a display driver, a data driver, and a display device including the output buffer circuit.

Background

In a semiconductor integrated device that drives an externally connected load, an output buffer that outputs a drive signal for driving the load is provided. The output buffer includes, for example, a P-channel metal oxide semiconductor (metal oxide semiconductor, MOS) type transistor and an N-channel MOS type transistor that receive binary (logic level 0, logic level 1) input signals with respective gate terminals and have respective drain terminals connected to each other at an output node. According to the above configuration, the output buffer complementarily sets the two transistors to the on state by the binary input signal, thereby outputting the binary drive signal from the output node.

In other words, when the load to be driven is a large-capacity load having a relatively large capacity and requiring pulse driving of a high voltage, such as a liquid crystal display panel or an organic Electroluminescence (EL) display panel, a high-driving type output buffer is used as the output buffer.

In such a high-drive output buffer, there is a case where one of the two transistors is turned on at a timing when the other transistor is turned off from the off state to the on state, and the two transistors are temporarily turned on at the same time. Thus, there are the following problems: a relatively large through current flows between the two transistors, resulting in the generation of electromagnetic interference (electro MAGNETIC INTERFERENCE, EMI) caused by the through current and an increase in power consumption. In addition, there is a problem of EMI generation due to current fluctuation associated with charge/discharge current at the time of load driving.

In order to solve this problem, an output buffer circuit has been proposed in which a pre-buffer section is provided in a stage preceding a buffer section including the P-channel MOS transistor and the N-channel MOS transistor (see patent document 1).

The pre-buffer section included in the output buffer circuit described in patent document 1 includes: a first inverter receiving an input signal and supplying an inverted signal thereof to a gate of the P-channel MOS transistor; and a second inverter receiving an input signal and supplying an inverted signal thereof to a gate of the N-channel MOS transistor. In this case, a current source is connected to the source of the N-channel MOS transistor of the first inverter, and a current source is connected to the source of the P-channel MOS transistor of the second inverter. In the output buffer circuit described in patent document 1, the current flowing in the current source of the pre-buffer unit is adjusted so that the two transistors of the buffer unit transition from the on state to the off state faster than from the off state to the on state. In this way, in the output buffer circuit, the state in which both transistors of the buffer section are simultaneously turned on is avoided, and the through current is prevented from slowing down the voltage change of the output signal.

[ Prior Art literature ]

[ Patent literature ]

[ Patent document 1] Japanese patent laid-open No. 6-152374

Disclosure of Invention

[ Problem to be solved by the invention ]

In the output buffer circuit described in patent document 1, the time required for the two transistors of the buffer section to transition from the off state to the on state increases as the current flowing through the current source of the pre-buffer section decreases.

Thus, since the voltage change of the output signal is smoothed, the through current can be reliably suppressed, and the EMI can be reduced. However, since the current driving capability of the output buffer circuit is lowered, the passivation of the pulse voltage waveform of the output signal becomes large, and thus high-speed load driving cannot be performed.

In this way, the reduction of EMI is in a trade-off relationship with the current driving capability, and its optimal adjustment value differs according to each load as a driving object. Accordingly, an output buffer circuit having an adjustment circuit incorporated therein for adjusting current drive capability is desired.

In the case of a high-drive output buffer circuit, the current drive capability adjustment circuit itself needs to be constructed using a transistor having a relatively large size corresponding to a high voltage. Therefore, in particular, in the case of employing a multi-output structure including a plurality of output buffer circuits as described above for driving a plurality of loads, there is a problem that the circuit area increases in proportion to the number of output buffer circuits.

Accordingly, an object of the present application is to provide an output buffer circuit having a current drive capability adjustment function and capable of saving an area when a multi-output structure is adopted, a display driver including the output buffer circuit, and a display device.

[ Means of solving the problems ]

An output buffer circuit of the present invention is an output buffer circuit for outputting an output signal obtained by amplifying an input signal from an output terminal, and includes: a first transistor of a first conductivity type that supplies a first high-voltage power supply voltage to the output terminal when the first transistor is turned on in response to a voltage of the input signal received by a gate of the first transistor; a second transistor of a second conductivity type that supplies a second high-voltage power supply voltage lower than the first high-voltage power supply voltage to the output terminal when the second transistor is turned on in response to a voltage of the input signal received by a gate of the second transistor; a bias unit for generating a bias voltage; an output control unit that, when the voltage of the input signal changes, changes the voltage of the gate of the transistor in the on state of the first transistor and the second transistor at a change speed corresponding to the voltage change of the input signal, thereby shifting the transistor in the on state to the off state, and changes the voltage of the gate of the transistor in the off state of the first transistor and the second transistor at a change speed based on the current value controlled by the bias voltage, thereby bringing the transistor in the off state to the on state; and a drive setting unit that designates a voltage value of the bias voltage and generates a setting signal for setting the voltage value, wherein the bias unit includes a bias modulation unit that operates by receiving a first low-voltage power supply voltage having a voltage value equal to or lower than the first high-voltage power supply voltage and a second low-voltage power supply voltage having a voltage value equal to or higher than the second high-voltage power supply voltage, and sets the voltage value of the bias voltage to a voltage value based on the setting signal.

The output buffer circuit of the present invention is an output buffer circuit for outputting first to mth output signals obtained by amplifying first to mth input signals (M is an integer of 2 or more), and includes: a bias unit for generating a bias voltage; a drive setting unit that designates a voltage value of the bias voltage and generates a setting signal for setting the voltage value; and first to mth buffer units for receiving the first to mth input signals, respectively, and outputting the first to mth output signals via respective output terminals, the first to mth buffer units each including: a first transistor of a first conductivity type that supplies a first high-voltage power supply voltage to the output terminal thereof when the first transistor is turned on in response to a voltage of the input signal received by the gate thereof; a second transistor of a second conductivity type that supplies a second high-voltage power supply voltage lower than the first high-voltage power supply voltage to the output terminal of the second transistor when the second transistor is turned on in response to a voltage of the input signal received by the gate of the second transistor; and an output control unit that, when the voltage of the input signal changes, causes the transistor in the on state to shift to the off state by changing the voltage of the gate of the transistor in the on state among the first transistor and the second transistor at a change rate corresponding to the voltage change of the input signal, and causes the transistor in the off state to reach the on state by changing the voltage of the gate of the transistor in the off state among the first transistor and the second transistor at a change rate based on a current value controlled by the bias voltage, wherein the bias unit is provided in common with each of the first to M-th buffer units, and the bias unit includes a bias modulation unit that receives a first low voltage power supply voltage having a voltage value less than or equal to the first high voltage power supply voltage and a second low voltage power supply voltage having a voltage value higher than or equal to the second high voltage power supply voltage, and that causes the transistor in the off state to reach the on state by changing the voltage of the gate of the transistor in the off state, and the bias unit presses the bias voltage to the first buffer unit having the bias value to the bias value based on the bias value.

The display driver according to the present invention is a display driver for driving a display panel corresponding to a video signal, the display panel including: a plurality of scanning lines arranged along a horizontal direction of a screen, and a plurality of data lines arranged to intersect the plurality of scanning lines, wherein the display driver includes: a data driver for generating a plurality of driving signals based on the video signal and supplying the driving signals to the plurality of data lines; and a scan driver driving the plurality of scan lines at a timing corresponding to the plurality of scan timing signals, the data driver including a scan control signal output circuit outputting the plurality of scan timing signals, the scan control signal output circuit including an output buffer circuit of the multi-output structure.

The display driver according to the present invention is a display driver for driving a passive matrix display panel corresponding to a video signal, the display panel including: a plurality of scanning lines arranged along a horizontal direction of a screen, and a plurality of data lines arranged to intersect the plurality of scanning lines, the display driver including: a data driver including a first output buffer section that outputs a plurality of driving pulse signals having pulse widths corresponding to luminance levels of pixels shown by the video signal to a plurality of data lines; and a scan driver including a second output buffer section that outputs a plurality of scan pulse signals to the plurality of scan lines, the first output buffer section and the second output buffer section including output buffer circuits of the multi-output structure.

The display device of the present invention is a display device including: a display panel including a plurality of scanning lines arranged along a horizontal direction of a screen and a plurality of data lines arranged to intersect the plurality of scanning lines; and a display driver that drives the display panel in response to a video signal, the display driver having: a scan driver driving a plurality of scan lines at a timing corresponding to a plurality of scan timing signals; and a data driver for generating a plurality of driving signals based on the video signal and supplying the driving signals to the plurality of data lines, wherein the data driver includes a scan control signal output circuit for outputting the plurality of scan timing signals, and the scan control signal output circuit includes an output buffer circuit having the multi-output structure.

[ Effect of the invention ]

In the output buffer circuit of the present invention, the output control section controls the gate voltages of the first transistor and the second transistor of the output stage based on the input signal, thereby complementarily setting the first transistor and the second transistor to an on state and an off state, respectively. At this time, the output control unit controls the first transistor and the second transistor as follows when the voltage of the input signal changes. That is, the gate voltage of the transistor in the on state of the first transistor and the second transistor is changed at a change speed corresponding to a voltage change of the input signal, so that the transistor is shifted to the off state. Further, the gate voltage of the transistor in the off state among the first transistor and the second transistor is changed at a rate of change in the current value controlled by the bias voltage set by the setting signal, so that the transistor is brought into the on state. The bias unit that generates the bias voltage to be supplied to the output buffer unit includes a bias modulation unit that operates at a low power supply voltage equal to or lower than the power supply voltage used in the output control unit and the output stage, and the bias modulation unit sets the voltage value of the bias voltage to be variable.

Thus, the output buffer circuit of the present invention can avoid the simultaneous turn-on of the first transistor and the second transistor of the output stage when the voltage of the input signal changes. As a result, an instantaneous through current flowing between the first transistor and the second transistor can be prevented, and generation of EMI accompanying the through current can be suppressed. Further, since the bias modulation section for generating the bias voltage for setting the current driving capability of the output buffer circuit of the present invention may include a low voltage circuit, the adjustment range of the bias voltage can be increased with a small area-saving configuration. Thus, the EMI generated by the fluctuation of the charge/discharge current during the load driving can be reduced, and the voltage waveform of the output signal can be optimally adjusted while suppressing the deformation to the minimum.

In addition, when a plurality of buffer units including the output stage and the output control unit are provided and the output buffer circuit is configured to be multi-output, the bias unit that generates the bias voltage that is responsible for adjustment of the current driving capability may be configured by one system shared by the plurality of buffer units. Therefore, even when the output buffer circuit having a plurality of buffer sections is provided, the area of the entire device can be reduced.

Therefore, according to the present invention, it is possible to provide an output buffer circuit which has a current drive capability adjusting function for optimizing reduction of distortion and EMI reduction of a voltage waveform of an output signal and which can achieve area saving in the case of employing a plurality of outputs.

Drawings

Fig. 1 is a circuit diagram showing a configuration of an output buffer circuit 100 as an example of the output buffer circuit of the present invention.

Fig. 2 is a circuit diagram showing a configuration of the bias unit 30A1 as an example of the bias unit 30A.

Fig. 3A is a circuit diagram showing a configuration of the variable current source 41A1 as an example of the variable current source 41A.

Fig. 3B is a circuit diagram showing a configuration of the variable current source 42A1 as an example of the variable current source 42A.

Fig. 4 is a circuit diagram showing a configuration of an output buffer circuit 100A as a modification of the output buffer circuit 100.

Fig. 5 is a circuit diagram showing a configuration of the bias unit 30B1 as an example of a configuration of the bias unit 30B.

Fig. 6 is a circuit diagram showing a configuration of a bias unit 30C as a modification of the bias unit 30B.

Fig. 7 is a circuit diagram showing an example of the internal configuration of each of the amplifier 71c_p and the amplifier 71c_n.

Fig. 8 is a circuit diagram showing a configuration of an output buffer circuit 100B as a modification of the output buffer circuit 100.

Fig. 9A is a circuit diagram showing a configuration of an output buffer circuit 100C as still another modification of the output buffer circuit 100.

Fig. 9B is a timing chart showing waveforms of the output signal So and voltages V1 and V2 generated at the nodes n1 and n2 of the buffer section 10C when the high-voltage input signal Si1 and the high-voltage input signal Si2 are received, respectively.

Fig. 10 is a block diagram showing the structure of a multi-output buffer device 200 having M output channels.

Fig. 11 is a block diagram showing the structure of a multi-output buffer device 200A having M output channels.

Fig. 12 is a block diagram showing a schematic configuration of the active matrix display device 300.

Fig. 13 is a block diagram showing a schematic configuration of a passive matrix display device 300A.

Fig. 14 is a block diagram showing a configuration of a multi-output buffer device 200B having a buffer section 10Ax and a buffer section 10Ay for driving two loads X and Y, which are required to have mutually different current driving capacities, respectively.

Fig. 15A and 15B are diagrams showing the setting operation of the current driving capability of the buffer portion 10 Ay.

Fig. 16 is a block diagram showing a configuration of a multi-output buffer device 200C as another example of the multi-output buffer device.

Fig. 17 is a block diagram showing a schematic configuration of a time-division driving type display device 600 using the multi-output buffer device 200B and the multi-output buffer device 200C shown in fig. 14 and 16.

Fig. 18 is a diagram showing an example of the arrangement positions of the drive setting unit 20A, the control buffer unit BU1, and the control buffer unit BU2 in the data driver 120B of the display apparatus 600.

[ Description of symbols ]

10A, 10B, 10C: buffer part

11. 12, 15, 16: Transistor with a high-voltage power supply

13. 14: Inverter with a high-speed circuit

20: Drive setting part

30A, 30B, 30C: offset part

90-92: Level shifter

Detailed Description

Example 1

As shown in fig. 1, the output buffer circuit 100 includes a buffer section 10A, a drive setting section 20, a bias section 30A, and a level shifter (LEVEL SHIFTER, LS) 90.

The level shifter 90 receives an input signal Si0L of a binary value (logic level 0 or logic level 1) whose voltage varies within the amplitude of the low voltage (power supply voltage VSS to power supply voltage VDD) via the input terminal TI. The level shifter 90 converts the input signal Si0L into a high-voltage input signal Si0 whose amplitude level is converted into a high-voltage range (power supply voltage VGL to power supply voltage VGH). The power supply voltage VSS, the power supply voltage VDD, the power supply voltage VGL, and the power supply voltage VGH have the following magnitude relationship

VGH＞VDD＞VSS≧VGL

Or alternatively

VGH≧VDD＞VSS＞VGL。

Then, the level shifter 90 supplies the high voltage input signal Si 0to the buffer section 10A via the node Ti 0.

The buffer section 10A includes high-voltage elements, and includes the following high-voltage elements operating in a high-voltage power supply voltage range (VGL to VGH).

That is, the buffer section 10A includes: an output stage including a P-channel transistor 11 and an N-channel transistor 12, and an output control unit 19A for controlling gate voltages of the transistors 11 and 12.

The power supply voltage VGH is applied to the source of the transistor 11, and the power supply voltage VGL is applied to the source of the transistor 12. The drains of the transistors 11 and 12 are connected TO an output terminal TO, and a signal having a binary value (logic level 0 or logic level 1) of a voltage generated at the output terminal TO is outputted as an output signal So.

The output control unit 19A includes an inverter 13, an inverter 14, an N-channel transistor 15, and a P-channel transistor 16.

The inverter 13 includes an N-channel transistor 13N and a P-channel transistor 13P, the gates of which are commonly connected to each other, form an input terminal of the inverter 13 and are connected to the node Ti0, and the drains of which are commonly connected to each other, form an output terminal of the inverter 13 and are connected to the node N1. The source of the transistor 13p is connected to the positive side power supply terminal, receives the power supply voltage VGH, and the source of the transistor 13n is connected to the negative side power supply terminal via the transistor 15, and receives the power supply voltage VGL. That is, the inverter 13 supplies the voltage of the signal obtained by inverting the phase of the high-voltage input signal Si0 received via the node Ti0 to the gate of the transistor 11 via the node n 1.

The inverter 14 includes an N-channel transistor 14N and a P-channel transistor 14P, the gates of which are commonly connected to each other, form an input terminal of the inverter 14 and are connected to a node Ti0, and the drains of which are commonly connected to each other, form an output terminal of the inverter 14 and are connected to a node N2. The source of the transistor 14p is connected to the positive side power supply terminal via the transistor 16, and receives the power supply voltage VGH, while the source of the transistor 14n is connected to the negative side power supply terminal, and receives the power supply voltage VGL. That is, the inverter 14 supplies the voltage of the signal obtained by inverting the phase of the high-voltage input signal Si0 received via the node Ti0 to the gate of the transistor 12 via the node n 2.

The drain of the transistor 15 is connected to the negative power supply terminal of the inverter 13, and receives the power supply voltage VGL from the source and the bias voltage VBN supplied from the bias unit 30A via the node n3 from the gate.

The drain of the transistor 16 is connected to the positive power supply terminal of the inverter 14, and receives the power supply voltage VGH from the source and the bias voltage VBP supplied from the bias unit 30A via the node n4 from the gate.

The drive setting unit 20 includes a storage unit (not shown) that instructs the bias voltage VBN and the voltage value of the bias voltage VBP, and stores setting data for setting the voltage value. The drive setting unit 20 generates a setting signal Cs indicating a voltage value indicated by the setting data stored in the storage unit, and supplies the setting signal Cs to the bias unit 30A. The drive setting unit 20 may receive setting data supplied from the outside, generate a setting signal Cs indicating a voltage value indicated by the setting data, and supply the setting signal Cs to the bias unit 30A.

The bias unit 30A includes a bias modulation unit 40A, a voltage protection unit 50A, and a current-voltage conversion unit 60A.

The bias modulation unit 40A receives the power supply voltage VDD and the power supply voltage VSS, and operates in the high voltage power supply voltage range (VSS to VDD) of the buffer unit 10A. Bias modulation unit 40A generates a pair of currents I1A and I2A having current values corresponding to setting signal Cs, and supplies the currents to voltage protection unit 50A.

The voltage protection unit 50A controls the voltage applied to the output of the bias modulation unit 40A to fall within the low-voltage power supply voltage range (VSS to VDD) while eliminating the influence of the high-voltage power supply voltage VGH and the high-voltage power supply voltage VGL while relaying the current I1A and the current I2A to the current-voltage conversion unit 60A.

The current-voltage converting unit 60A receives the power supply voltage VGH and the power supply voltage VGL, and converts the current I1A and the current I2A into the bias voltage VBN and the bias voltage VBP having voltage values within the high-voltage power supply voltage range (VGL to VGH), respectively. Then, the current-voltage converting section 60A supplies the bias voltage VBN to the gate of the transistor 15 via the node n3, and supplies the bias voltage VBP to the gate of the transistor 16 via the node n 4.

The operation of the output buffer circuit 100 shown in fig. 1 will be described below.

First, when receiving an input signal Si0L having a power supply voltage VSS corresponding to a logic level 0, the level shifter 90 generates a high-voltage input signal Si0 having a logic level 0 obtained by level-shifting the Voltage (VSS) of the input signal Si0L to the power supply voltage VGL, and supplies the high-voltage input signal Si0 to the inverter 13 and the inverter 14. Thus, the inverter 13 supplies a signal having the power supply voltage VGH corresponding to the logic level 1 to the gate of the transistor 11, and the inverter 14 supplies a signal having the power supply voltage VGH corresponding to the logic level 1 to the gate of the transistor 12. Therefore, at this time, the transistor 11 is turned off, the transistor 12 is turned on, and the output signal So having the logic level 0 of the power supply voltage VGL is output through the output terminal TO.

Next, when receiving an input signal Si0L having a power supply voltage VDD corresponding to a logic level 1, the level shifter 90 generates a high-voltage input signal Si0 for level-shifting the Voltage (VDD) of the input signal Si0L to a logic level 1 of the power supply voltage VGH, and supplies the high-voltage input signal Si0 to the inverter 13 and the inverter 14. Thus, the inverter 13 supplies a signal having the power supply voltage VGL corresponding to the logic level 0 to the gate of the transistor 11, and the inverter 14 supplies a signal having the power supply voltage VGL corresponding to the logic level 0 to the gate of the transistor 12. Therefore, at this time, the transistor 11 is turned on, the transistor 12 is turned off, and the output signal So having the logic level 1 of the power supply voltage VGH is output via the output terminal TO.

In this way, in the output buffer circuit 100, the output control unit 19A controls the gate voltages of the transistors 11 and 12 of the output stage based on the high-voltage input signal Si0, and sets the transistors 11 and 12 to the on state or the off state complementarily. At this time, the output control unit 19A controls the transistors 11 and 12 of the output stage as follows when the voltage of the high-voltage input signal Si0 changes. That is, the gate voltages of the transistors 11 and 12 in the on state are changed at a change speed corresponding to the voltage change of the input signal, and the transistors are quickly shifted to the off state. Further, the gate voltages of the transistors 11 and 12 in the off state are changed at a rate of change in the current value controlled by the bias voltages (VBN, VBP) having the voltage value indicated by the setting signal Cs, so that the transistors are brought into the on state.

Specifically, when the high-voltage input signal Si0 changes from the power supply voltage VGL of the logic level 0 to the power supply voltage VGH of the logic level 1, the transistor 14n of the inverter 14 changes from the off state to the on state by the switching operation corresponding to the voltage change of the high-voltage input signal Si0, and the gate of the transistor 12 changes rapidly from the power supply voltage VGH to the power supply voltage VGL, whereby the transistor 12 changes rapidly from the on state to the off state. At this time, the transistor 13n of the inverter 13 is turned on, the gate of the transistor 11 is changed from the power supply voltage VGH to the power supply voltage VGL at a rate corresponding to the change rate of the current value controlled by the bias voltage VBN, and the transistor 11 is changed from the off state to the on state at a rate corresponding to the change rate. On the other hand, when the high-voltage input signal Si0 changes from the power supply voltage VGH of the logic level 1 to the power supply voltage VGL of the logic level 0, the transistor 13p of the inverter 13 changes from the off state to the on state by the switching operation corresponding to the voltage change of the high-voltage input signal Si0, and the gate of the transistor 11 changes rapidly from the power supply voltage VGL to the power supply voltage VGH, whereby the transistor 11 changes rapidly from the on state to the off state. At this time, the transistor 14p of the inverter 14 is turned on, the gate of the transistor 12 is changed from the power supply voltage VGL to the power supply voltage VGH at a rate corresponding to the change rate of the current value controlled by the bias voltage VBP, and the transistor 12 is changed from the off state to the on state at a rate corresponding to the change rate.

This prevents the transistors 11 and 12 of the output stage from being turned on at the same time when the voltage of the input signal changes. As a result, an instantaneous through current flowing between the transistor 11 and the transistor 12 can be prevented, and generation of EMI and increase in power consumption associated with the through current can be suppressed. In addition, by controlling the change speed of the voltage of the output signal So, the change speed of the charge/discharge current at the time of load driving can be controlled, and EMI can be reduced.

When the output buffer circuit 100 is provided with a plurality of output stages 11 and 12 and the output control unit 19A and is configured to be multi-output, the bias unit 30A for generating the bias voltage for adjusting the current driving capability may be configured by only one system shared by the multi-output. Further, the bias modulation unit 40A, which sets the voltage values of the bias voltages (VBN, VBP) included in the bias unit 30A to an arbitrary value, may include low-voltage elements operating at power supply voltages (VDD, VSS) equal to or lower than the power supply voltages (VGH, VGL) used in the output stages (11, 12) and the output control unit 19A, and thus may reduce the addition of high-voltage elements and save the area. The bias modulation section 40A including the low-voltage element can suppress an increase in circuit area and increase the number of adjustment steps of the bias voltage.

Therefore, according to the output buffer circuit 100 of the present invention, by including the adjustment means utilizing the current driving capability of the bias voltage VBN and the bias voltage VBP, it is possible to prevent the EMI accompanying the through current or the increase in the power consumption while maintaining the current driving capability (the output waveform with less distortion) required for the load driving, and also to reduce the EMI generated by the charge/discharge current accompanying the load driving, and to achieve the area saving in the case of the multiple outputs.

In fig. 1, the structure of the output buffer circuit 100 is shown as an example of the structure of the output buffer circuit, but the structure is not limited to this.

In short, the output buffer circuit of the present invention may include the first transistor and the second transistor which serve as output stages, the bias unit, the output control unit, and the drive setting unit as follows.

When the first transistor (11) is in an on state in response TO the voltage of an input signal received by the gate of the first transistor, a first high-voltage power supply Voltage (VGH) is supplied TO an output Terminal (TO). When the second transistor (12) is in an on state in response TO the voltage of an input signal received by the gate of the second transistor, a second high-voltage power supply Voltage (VGL) is supplied TO the output Terminal (TO). The bias unit (30A) generates bias voltages (VBN, VBP). When the voltage of an input signal (Si 0) changes, an output control unit (19A) changes the voltage of the gate of the transistor in the on state of the first transistor and the second transistor at a change speed corresponding to the voltage change of the input signal, thereby shifting the transistor in the on state to the off state. The output control unit changes the voltage of the gate of the transistor in the off state among the first transistor and the second transistor at a rate that is based on the current value controlled by the bias voltages (VBN, VBP), thereby turning on the transistor in the off state. The drive setting unit specifies the voltage value of the bias voltage, and generates a setting signal (Cs) for setting the voltage value.

The bias unit (30A) includes the following bias modulation unit.

The bias modulation unit (40A) receives and operates a first low-voltage power supply Voltage (VDD) having a voltage value less than or equal to the first high-voltage power supply Voltage (VGH) and a second low-voltage power supply Voltage (VSS) having a voltage value greater than or equal to the second high-voltage power supply Voltage (VGL), and sets the voltage value of the bias voltages (VBN, VBP) to a voltage value based on the set signal (Cs).

Example 2

Fig. 2 is a circuit diagram showing a configuration of the bias unit 30A1 as an example of the bias unit 30A shown in fig. 1.

The bias unit 30A1 includes a bias modulation unit 40A1, a withstand voltage protection unit 50A1, and a current-voltage conversion unit 60A1, and generates a bias voltage VBN and a bias voltage VBP having voltage values based on the set signal Cs in a high-voltage power supply voltage range (VGL to VGH).

The bias modulation unit 40A1 includes a variable current source 41A and a variable current source 42A, and the variable current source 41A and the variable current source 42A include low-voltage elements, each operate in a low-voltage power supply voltage range (VSS to VDD), and generate a current I1A and a current I2A having current values based on the setting signal Cs supplied from the drive setting unit 20. The variable current source 41A receives the power supply voltage VDD and sends out the current I1A, and the variable current source 42A receives the power supply voltage VSS and sends out the current I2A.

The voltage protection portion 50A1 includes a P-channel transistor 51A and an N-channel transistor 52A of a high-voltage element. The transistor 51A receives the current I1A generated by the variable current source 41A by applying the power supply voltage VSS to its gate and using its source. The transistor 52A applies the power supply voltage VDD to its gate, and connects the variable current source 42A to its drain.

The current-voltage conversion unit 60A1 includes an N-channel transistor 61A and a P-channel transistor 62A of a high-voltage element. The gate and drain of the transistor 61A are connected to the drain of the transistor 51A, and the power supply voltage VGL is applied to the source thereof. The gate and drain of the transistor 62A are connected to the drain of the transistor 52A, and the power supply voltage VGH is applied to the source thereof.

Here, the voltage generated by the gate and the drain of the transistor 61A is output as the bias voltage VBN via the node n3, and the voltage generated by the gate and the drain of the transistor 62A is output as the bias voltage VBP via the node n 4.

According to the configuration shown in fig. 2, the current I1A and the current I2A output from the bias modulation section 40A1 are supplied to the current-voltage conversion section 60A1 via the transistor 51A and the transistor 52A of the voltage protection section 50A1, respectively.

The transistor 51A of the voltage protection unit 50A1 receives the power supply voltage VSS at its gate, receives the current I1A generated by the variable current source 41A with reference to the power supply voltage VDD at its source, and outputs the current I1A from its drain. Accordingly, the source voltage of the transistor 51A is maintained at a voltage higher than the gate-source voltage difference from the gate application voltage VSS, and thus the transistor 51A causes the current I1A to flow through the transistor 61A of the current-voltage converting unit 60A1 while clamping the voltage applied to the variable current source 41A within the voltage range (VSS to VDD). The voltage applied to the gate of the transistor 51A may be changed to a voltage different from the power supply voltage VSS within a range in which the variable current source 41A does not deviate from the power supply voltage range (VSS to VDD).

The transistor 52A of the voltage protection unit 50A1 receives the power supply voltage VDD from its gate, receives the current I2A generated by the variable current source 42A with reference to the power supply voltage VSS from its source, and outputs the current I2A from its drain. Thus, the source voltage of the transistor 52A is maintained at a voltage lower than the gate-source voltage difference from the gate applied voltage VDD, and thus the transistor 52A causes the current I2A to flow through the transistor 62A of the current-voltage converting portion 60A1 while clamping the voltage applied to the variable current source 41A within the voltage range (VSS to VDD). The voltage applied to the gate of the transistor 52A may be changed to a voltage different from the power supply voltage VDD within a range in which the variable current source 42A does not deviate from the power supply voltage range (VSS to VDD).

As shown in fig. 2, the current-voltage conversion unit 60A1 receives the current I1A through the drain and gate of the transistor 61A connected to the diode, converts the current I1A into a voltage, and supplies the bias voltage VBN indicating the voltage to the buffer unit 10A. Further, in the current-voltage conversion unit 60A1, as shown in fig. 2, the current I2A is received by the drain and gate of the transistor 62A connected to the diode, the current I2A is converted into a voltage, and the bias voltage VBP indicating the voltage is supplied to the buffer unit 10A.

As shown in fig. 1 and 2, the first current mirror circuit may be configured by the transistor 61A included in the bias unit 30A1 and the transistor 15 included in the buffer unit 10A, and the second current mirror circuit may be configured by the transistor 62A included in the bias unit 30A1 and the transistor 16 included in the buffer unit 10A.

In the structure shown in fig. 2, the transistor 61A and the transistor 62A each include a plurality of diode-connected transistors stacked in the vertical direction, so that the current flowing through the transistor 15 and the transistor 16 of the buffer portion 10A can be increased.

In the voltage protection unit 50A1 shown in fig. 2, the transistor 51A can be deleted when the power supply voltage VGL is equal to the power supply voltage VSS, and the transistor 52A can be deleted when the power supply voltage VGH is equal to the power supply voltage VDD.

Fig. 3A is a circuit diagram showing a configuration of the variable current source 41A1 as an example of the variable current source 41A shown in fig. 2.

The variable current source 41A1 includes the following low voltage elements operating in the low voltage power supply voltage range (VSS to VDD).

That is, the variable current source 41A1 includes, for example, a plurality of constant current sources 43A, 43a_1 to 43a_k (k is an integer of 2 or more) connected in parallel between a power supply terminal to which the power supply voltage VDD is applied and the node n41A connected to the source of the transistor 51A. The variable current source 41A1 further includes switches 44a_1 to 44a_k, and the switches 44a_1 to 44a_k are connected in series to the constant current sources 43a_1 to 43a_k, respectively, and control current supply to the node n41A or current interruption by the digital setting signals csp_1 to csp_k included in the setting signal Cs.

According to the configuration shown in fig. 3A, the total current of the constant current sources 43A, 43a_1 to 43a_k, which are in a state in which current can be supplied by the digital setting signal csp_1 to csp_k, is generated as the current I1A in the variable current source 41 A1. That is, the variable current source 41A1 can variably set the current value of the current I1A by the digital setting signals csp_1 to csp_k.

Fig. 3B is a circuit diagram showing a configuration of the variable current source 42A1, which is an example of the variable current source 42A shown in fig. 2.

The variable current source 42A1 includes the following low voltage elements operating in the low voltage power supply voltage range (VSS to VDD).

That is, the variable current source 42A1 includes, for example, a plurality of constant current sources 45A, 45a_1 to 45a_k (k is an integer of 2 or more) connected in parallel between a power supply terminal to which the power supply voltage VSS is applied and the node n42A connected to the source of the transistor 52A. The variable current source 42A1 further includes switches 46a_1 to 46a_k, and the switches 46a_1 to 46a_k are connected in series to the constant current source 45a_1 to 45a_k, respectively, and control current supply to the node n42A or current interruption by the digital setting signals csn_1 to csn_k included in the setting signal Cs.

According to the configuration shown in fig. 3B, the total current of the constant current sources 45A, 45a_1 to 45a_k, which are in a state in which current can be supplied by the digital setting signal csn_1 to csn_k, is generated as the current I2A in the variable current source 42 A1. That is, the variable current source 42A1 can variably set the current value of the current I2A by the digital setting signals csn_1 to csn_k.

Example 3

Fig. 4 is a circuit diagram showing a configuration of an output buffer circuit 100A as a modification of the output buffer circuit 100 shown in fig. 1.

In the configuration shown in fig. 4, the configuration is the same as that shown in fig. 1 except that the offset portion 30A shown in fig. 1 is changed to the offset portion 30B. Therefore, only the biasing portion 30B will be described in detail below.

The bias unit 30B includes a bias modulation unit 40B and a voltage protection unit 50B, and supplies a bias voltage VBN and a bias voltage VBP having voltage values corresponding to the setting signal Cs to the gates of the transistors 15 and 16 of the buffer unit 10A via the nodes n3 and n 4.

The bias modulation unit 40B receives the power supply voltage VDD and the power supply voltage VSS, and operates in the high voltage power supply voltage range (VSS to VDD) of the buffer unit 10A. The bias modulation unit 40B generates a pair of voltages V1B and V2B having voltage values corresponding to the setting signal Cs, and supplies the voltages to the voltage protection unit 50B.

The voltage protection unit 50B relays these voltages V1B and V2B as the bias voltages VBN and VBP to the buffer unit 10A via the nodes n3 and n4, respectively, while controlling the voltages V1B and V2B not to deviate from the low voltage power supply voltage ranges (VSS to VDD).

Example 4

Fig. 5 is a circuit diagram showing a configuration of the bias unit 30B1, which is an example of the configuration of the bias unit 30B shown in fig. 4.

As shown in fig. 5, the bias unit 30B1 includes a bias modulation unit 40B1 and a voltage protection unit 50B1, and outputs a bias voltage VBN and a bias voltage VBP within a high-voltage power supply voltage range (VGL to VGH) in which the buffer unit 10A operates.

The bias modulation unit 40B1 includes a reference voltage generation unit 41B and a digital-to-analog (digital to analog, D/a) conversion unit 42B.

The reference voltage generating unit 41B includes, for example, a resistor ladder that generates a plurality of reference voltages by dividing the voltage between the power supply voltage VDD and the power supply voltage VSS, and supplies the generated plurality of reference voltages to the D/a converting unit 42B.

The D/a conversion unit 42B selects two voltages from the plurality of reference voltages based on the setting signal Cs of the drive setting unit 20, and supplies the voltages as the voltage V1B and the voltage V2B to the voltage protection unit 50B1 via the node n3 and the node n4, respectively.

The voltage protection unit 50B1 includes N-channel transistors 51N and 52N, and P-channel transistors 51P and 52P.

As shown in fig. 5, the power supply voltage VSS is commonly applied to the drains of the transistors 51P and 52P, and a predetermined control voltage Vclp is commonly applied to the gates of the transistors. The source of the transistor 51P is connected to the node n3 receiving the voltage V1B, and the source of the transistor 52P is connected to the node n4 receiving the voltage V2B.

In addition, the control voltage Vclp is set to

Vclp＜VDD-|Vtp|

Vtp: threshold voltages of the transistor 51P and the transistor 52P.

According to the above configuration, when the voltage of the node n3 (n 4) is higher than the predetermined voltage (Vclp +|vtp|) around the power supply voltage VDD controlled by the control voltage Vclp, the transistor 51P (52P) is turned on, and the voltage of the node n3 (n 4) does not exceed the power supply voltage VDD.

As shown in fig. 5, the power supply voltage VDD is commonly applied to the drains of the transistors 51N and 52N, and a predetermined control voltage Vcln is commonly applied to the gates. A source of the transistor 51N is connected to the node N3, and a source of the transistor 52N is connected to the node N4.

In addition, the control voltage Vcln is set to

Vcln＞VSS+Vtn

Vtn: threshold voltages of the transistor 51N and the transistor 52N.

According to the above configuration, when the voltage at the node N3 (N4) is lower than the predetermined voltage (Vcln-Vtn) around the power supply voltage VSS controlled by the control voltage Vcln, the transistor 51N (52N) is turned on, and the voltage at the node N3 (N4) is not lower than the power supply voltage VSS.

The voltage protection unit 50B1 shares the voltages at the nodes n3 and n4 as the bias voltages VBN and VBP, respectively, to the buffer unit 10A.

That is, the voltage protection unit 50B1 shown in fig. 5 operates so that even if the bias voltage VBN and the bias voltage VBP vary due to, for example, capacitive coupling during operation of the buffer unit 10A, the respective voltage values do not deviate from the voltage ranges (VSS to VDD).

In this way, when the driving capability of the buffer section 10A operating in the high-voltage power supply voltage range (VGL to VGH) is set, the circuit configuration of the buffer section 10A shown in fig. 4 can bring the voltages of the bias voltage VBN and the bias voltage VBP within the low-voltage power supply voltage range (VSS to VDD). Thus, the bias modulation unit 40B1 and the voltage protection unit 50B1 can be realized by the low-voltage circuit shown in fig. 5 operating in the low-voltage power supply voltage range (VSS to VDD), and the area can be reduced.

Example 5

Fig. 6 is a circuit diagram showing a configuration of a bias unit 30C as a modification of the bias unit 30B shown in fig. 4.

As shown in fig. 6, the bias unit 30C includes an amplifying unit 70C added to the bias modulation unit 40B and the voltage protection unit 50B shown in fig. 4 or 5.

The voltage protection unit 50B shown in fig. 6 relays the voltage V1B and the voltage V2B supplied from the bias modulation unit 40B to the amplification unit 70C, and controls the voltage V1B and the voltage V2B so as not to deviate from the voltage ranges (VSS to VDD) of the low-voltage power supply.

The amplifying section 70C includes an amplifier 71c_n and an amplifier 71c_p that operate at the power supply voltage VGH and the power supply voltage VGL. The amplifier 71c_n outputs, as the bias voltage VBN, a voltage obtained by expanding the voltage value of the voltage V1B supplied from the bias modulation unit 40B via the withstand voltage protection unit 50B to a high voltage power supply voltage range (VGL to VGH). The amplifier 71c_p outputs, as the bias voltage VBP, a voltage obtained by expanding the voltage value of the voltage V2B supplied from the bias modulation unit 40B via the withstand voltage protection unit 50B to a high voltage power supply voltage range (VGL to VGH).

Fig. 7 is a circuit diagram showing an example of the internal structure of the amplifier 71c_p.

The amplifier 71c_p including the configuration shown in fig. 7 receives the voltage V2B in the low voltage range (VSS to VDD), and outputs the voltage whose voltage value is extended toward the power supply voltage VGH side as the bias voltage VBP.

As shown in fig. 7, the amplifier 71c_p is an operational amplifier including constant current sources 72C, N channel type transistors 73C and N channel type transistors 74C, P channel type transistors 75C to P channel type transistors 77C, load resistors 78C, and constant current sources 79.

In fig. 7, one end of the constant current source 72C is connected to the sources of the transistors 73C and 74C that constitute the differential pair. The power supply voltage VGL is applied to the other end of the constant current source 72C. The voltage V2B is supplied to the gate of the transistor 73C, and the drain of the transistor 75C and the gate of the transistor 77C are connected to each other. The drain and gate of transistor 76C and the gate of transistor 75C are connected to the drain of transistor 74C. The power supply voltage VGH is applied to the sources of the transistors 75C and 76C. The source of the transistor 77C is supplied with the power supply voltage VGH, and the drain is connected to one end of the load resistor 78C. The other end of the load resistor 78C is connected to the gate of the transistor 74C and one end of the constant current source 79. The power supply voltage VGL is applied to the other end of the constant current source 79. The power supply voltage VSS may be applied to the other end of each of the constant current source 72C and the constant current source 79 instead of the power supply voltage VGL.

According to the structure shown in FIG. 7, a gate of transistor 77C is formed on the drain of the transistor

VBP＝V2B+Ic·Rc

Ic: current of constant current source 79

Rc: resistance value of load resistor

The bias voltage VBP of the indicated voltage value. That is, the amplifier 71c_p shown in fig. 7 generates the bias voltage VBP obtained by expanding the input voltage V2B to the power supply voltage VGH side.

The amplifier 71c_n may also be configured in the same manner as in fig. 7 to generate the bias voltage VBN obtained by expanding the input voltage V1B toward the power supply voltage VGL.

Example 6

Fig. 8 is a circuit diagram showing a configuration of an output buffer circuit 100B as a modification of the output buffer circuit 100 shown in fig. 1.

In the configuration shown in fig. 8, a buffer portion 10B is used instead of the buffer portion 10A shown in fig. 1, and the other configurations (20, 30A to 30C, 90) are the same as those shown in fig. 1 to 7.

The buffer section 10B includes high-voltage elements, and includes the following high-voltage elements operating in a high-voltage power supply voltage range (VGL to VGH).

That is, the buffer section 10B includes an output stage including the P-channel transistor 11 and the N-channel transistor 12, and an output control section 19B for controlling the gate voltages of the transistors 11 and 12.

The power supply voltage VGH is applied to the source of the transistor 11, and the power supply voltage VGL is applied to the source of the transistor 12.

The drains of the transistors 11 and 12 are connected TO an output terminal TO, and a signal having a binary value (logic level 0 or logic level 1) of the voltage (VGL, VGH) generated at the output terminal TO is outputted as an output signal So.

The configuration of the output control unit 19B is different from that of the output control unit 19A shown in fig. 1, but the function of controlling the gate voltages of the transistors 11 and 12 of the output stage based on the high-voltage input signal Si0, the bias voltage VBN, and the bias voltage VBP is the same.

As shown in fig. 8, the output control unit 19B includes N-channel transistors 14B and 15B, and P-channel transistors 13B and 16B.

The high voltage input signal Si0 is supplied to the gates of the transistors 13B and 14B. A power supply voltage VGH is applied to the source of the transistor 13B, and the drain thereof is connected to the source of the transistor 16B, the drain of the transistor 15B, and the gate of the transistor 11 via the node n1, respectively. A power supply voltage VGL is applied to the source of the transistor 14B, and the drain thereof is connected to the drain of the transistor 16B, the source of the transistor 15B, and the gate of the transistor 12 via a node n2, respectively.

The bias voltage VBN generated by the bias unit 30A (30B, 30C) is supplied to the gate of the transistor 15B, and the bias voltage VBP generated by the bias unit 30A (30B, 30C) is supplied to the gate of the transistor 16B.

As the transistor 13B and the transistor 14B, transistors having larger current drive capability than the transistor 15B and the transistor 16B are used.

The operation of the buffer section 10B will be described below. Next, an operation when the high voltage input signal Si0 changes from the state of the logic level 0 (VGL) to the state of the logic level 1 (VGH) and changes again to the state of the logic level 0 (VGL) will be described.

First, while the high voltage input signal Si0 is in the state of logic level 0 (VGL), the transistor 13B is turned on, and the power supply voltage VGH is supplied to the node n1. Thereby, the transistor 11 is turned off. In addition, the transistor 14B is turned off, and the node n2 is blocked from the power supply voltage VGL. As a result, the voltage at the node n1 becomes the power supply voltage VGH, and the gate-source voltage of the transistor 16B exceeds the threshold voltage, whereby the transistor 16B is turned on. Therefore, the Voltage (VGH) of the node n1 is supplied to the node n2 via the transistor 16B, and the voltage of the node n2 becomes the power supply voltage VGH. As a result, the gate-source voltage of the transistor 12 exceeds the threshold voltage, and thus the transistor 12 is turned on, and the output signal So of logic level 0 (VGL) is output from the output terminal TO. Further, the transistor 15B is turned off because the voltage at the node n2 rises and the gate-source voltage is less than the threshold voltage.

After that, when the voltage of the high-voltage input signal Si0 starts to rise and exceeds the threshold voltage of the transistor 14B, the transistor 14B is turned on, and the power supply voltage VGL is supplied to the node n2. In addition, as the voltage of the high-voltage input signal Si0 increases, the current driving capability of the transistor 14B increases, while the current driving capability of the transistor 13B decreases, and the transistor 13B shifts to an off state. At this time, since the current driving capability of the transistor 14B is higher than that of the transistor 16B, the voltage of the node n2 drops relatively steeply from the state of the power supply voltage VGH to the power supply voltage VGL. Thereby, the transistor 12 shifts to the off state. In addition, the gate-source voltage of the transistor 15B exceeds the threshold voltage, and the transistor 15B is turned on. As a result, the transistor 15B supplies the voltage of the node n2 to the node n1 with a current driving capability corresponding to the current value controlled by the bias voltage VBN, so that the voltage of the node n1 drops gently. In addition, the gate-source voltage of the transistor 16B is lower than the threshold voltage, and the transistor 16B shifts to the off state.

Then, when the gate-source voltage of the transistor 11 exceeds the threshold voltage, the transistor 11 is turned on, and the power supply voltage VGH is supplied TO the output terminal TO. As a result, the voltage of the output signal So gently rises, and transitions from the state of logic level 0 (VGL) to the state of logic level 1 (VGH).

After that, when the voltage of the high-voltage input signal Si0 starts to drop and exceeds the threshold voltage of the transistor 13B, the transistor 13B is turned on, and the power supply voltage VGH is supplied to the node n1. In addition, as the voltage of the high-voltage input signal Si0 decreases, the current driving capability of the transistor 13B increases, while the current driving capability of the transistor 14B decreases to shift to the off state. At this time, since the current driving capability of the transistor 13B is higher than that of the transistor 15B, the voltage of the node n1 rises relatively steeply from the state of the power supply voltage VGL to reach the power supply voltage VGH. Thereby, the transistor 11 shifts to the off state. In addition, the gate-source voltage of the transistor 16B exceeds the threshold voltage, and the transistor 16B is turned on. As a result, the transistor 16B supplies the Voltage (VGH) of the node n1 to the node n2 with a current drive capability corresponding to the current value controlled by the bias voltage VBP, so that the voltage of the node n2 gently rises. In addition, the gate-source voltage of the transistor 15B is lower than the threshold voltage, and the transistor 15B shifts to the off state.

Then, when the gate-source voltage of the transistor 12 exceeds the threshold voltage, the transistor 12 is turned on, and the power supply voltage VGL is supplied TO the output terminal TO. As a result, the voltage of the output signal So gradually decreases, and transitions from the state of logic level 1 (VGH) to the state of logic level 0 (VGL).

As described above, in the buffer section 10B, when the transistors (11, 12) of the output stage are shifted from the on state to the off state, the gate voltages of the transistors of the output stage are controlled by the transistors (13B, 14B) having high current driving capability. On the other hand, when the transistors (11, 12) of the output stage are shifted from the off-state to the on-state, the gate voltage of the transistors of the output stage is gently changed via the transistors (15B, 16B) having current driving capability corresponding to the current values controlled by the bias voltages (VBN, VBP).

Therefore, after one transistor 11 (12) of the output stage is shifted to the off state in response to the high voltage input signal Si0, the other transistor 12 (11) is shifted to the on state, so that both are prevented from being simultaneously turned on, and the through current is suppressed.

Here, the number of elements (6 transistors) constituting the output control unit 19B shown in fig. 8 is smaller than the number of elements (8 transistors) constituting the output control unit 19A shown in fig. 1, and therefore, further area saving can be achieved. In addition, since the input capacitance of the output control unit 19B as seen from the node Ti0 is also smaller than that of the output control unit 19A, high-speed response can be achieved. Further, the output control unit 19B shown in fig. 8 can reliably suppress the through current of the transition generated when the voltage of the high-voltage input signal Si0 changes, as compared with the output control unit 19A shown in fig. 1.

Example 7

Fig. 9A is a circuit diagram showing a configuration of an output buffer circuit 100C as still another modification of the output buffer circuit 100 shown in fig. 1.

The output buffer circuit 100C is a non-inverting buffer that receives the input signal Si1L and the input signal Si2L of the low voltage of the two systems, which are slightly shifted in phase from each other, and outputs the output signal So of the high voltage of one system. Here, the input signal Si1L is a binary signal in which the state of the power supply voltage VSS (logic level 0) and the state of the power supply voltage VDD (logic level 1) are alternately repeated, and the input signal Si2L is a binary signal in which the rising timing of the voltage is slightly earlier and the falling timing is slightly later than the input signal Si 1L.

The configuration shown in fig. 9A is similar to that shown in fig. 1 to fig. 7 except that the configuration shown in fig. 9A is changed from the buffer section 10A shown in fig. 1 to the buffer section 10C, and the level shifter 90 shown in fig. 1 is changed from the level shifter 90 of one system to the level shifter 91 and the level shifter 92 of two systems, so that the configuration (20, 30A to 30C) corresponding to the input of the input signal Si1L and the input signal Si2L of two systems is similar to that shown in fig. 1 to fig. 7.

In the buffer portion 10C shown in fig. 9A, the inverter 13 and the inverter 14 shown in fig. 1 are changed to the inverter 13C and the inverter 14C, and the other configurations (11, 12, 15, 16) except for the above-described aspects are the same as those shown in fig. 1.

Inverter 13C receives the high voltage input signal Si1 via node Ti 1. When the high voltage input signal Si1 is at logic level 0 (VGL), the power supply voltage VGH is supplied to the node n1, and when the high voltage input signal Si1 is at logic level 1 (VGH), the power supply voltage VGL is supplied to the node n1 via the transistor 15. That is, the inverter 13C supplies the voltage of the phase-inverted signal to the gate of the transistor 11 via the node n1. The inverter 13C is identical to the inverter 13 of fig. 1 except for the input signal.

Inverter 14C receives the high voltage input signal Si2 via node Ti 2. The power supply voltage VGH is supplied to the node n2 via the transistor 16 when the high voltage input signal Si2 is a logic level 0 (VGL), and is supplied to the node n2 when the high voltage input signal Si2 is a logic level 1 (VGH). That is, the inverter 14C supplies the voltage of the phase-inverted signal to the gate of the transistor 12 via the node n2. Inverter 14C is identical to inverter 14 of fig. 1 except for the input signal.

The level shifter 91 receives the input signal Si1L via the input terminal TI1, and converts the input signal Si1L into a high-voltage input signal Si1 having an amplitude level converted into a high-voltage range (VGL to VGH). The level shifter 91 supplies the high-voltage input signal Si1 to the inverter 13C via the node Ti 1.

The level shifter 92 receives the input signal Si2L via the input terminal TI2, and converts the input signal Si2L into a high-voltage input signal Si2 having an amplitude level converted into a high-voltage range (VGL to VGH). The level shifter 92 supplies the high voltage input signal Si2 to the inverter 14C via the node Ti 2.

First, while the high-voltage input signal Si1 and the high-voltage input signal Si2 are in the state of logic level 0 (VGL), the inverter 13C and the inverter 14C supply the signals of the logic level 1 (VGH) after the phase inversion to the nodes n1 and n2, respectively. Therefore, the voltage V1 at the node n1 and the voltage V2 at the node n2 are both the power supply voltage VGH, the transistor 11 is turned off, and the transistor 12 is turned on, so that the output signal So at the logic level 0 (VGL) is output from the output terminal TO.

Thereafter, at time tr0 shown in fig. 9B, the voltage of the high-voltage input signal Si2 transits from the state of logic level 0 (VGL) to the state of logic level 1 (VGH). Thus, the inverter 14C supplies the power supply voltage VGL to the node n2, and the voltage V2 of the node n2 shifts to the power supply voltage VGL, thereby turning off the transistor 12.

Then, at a time tr1 later than the time tr0, the voltage of the high voltage input signal Si1 transits from the state of logic level 0 (VGL) to the state of logic level 1 (VGH). Thereby, the inverter 13C supplies the power supply voltage VGL to the node n1 via the transistor 15. At this time, the voltage V1 of the node n1 gradually decreases toward the power supply voltage VGL at a rate of change corresponding to the current value controlled by the bias voltage VBN applied to the gate of the transistor 15. During this period, at a time tr2 when the gate-source voltage of the transistor 11 based on the voltage V1 exceeds the threshold voltage, the transistor 11 is turned on, and the power supply voltage VGH is supplied TO the output terminal TO. As a result, the voltage of the output signal So gently rises, and transitions from the state of logic level 0 (VGL) to the state of logic level 1 (VGH).

Thereafter, at time tf0 shown in fig. 9B, first, the high voltage input signal Si1 transitions from the state of logic level 1 (VGH) to logic level 0 (VGL). Thus, the inverter 13C supplies the power supply voltage VGH to the node n1, and the voltage V1 of the node n1 shifts to the power supply voltage VGH, thereby turning off the transistor 11. Then, at time tf1 later than the time tf0, the high voltage input signal Si2 transits from the state of logic level 1 (VGH) to logic level 0 (VGL). Thereby, the inverter 14C supplies the power supply voltage VGH to the node n2 via the transistor 16. At this time, the voltage V2 of the node n2 gently rises toward the power supply voltage VGH at a rate of change corresponding to the current value controlled by the bias voltage VBP applied to the gate of the transistor 16. During this period, at a time tf2 when the gate-source voltage of the transistor 12 exceeds the threshold voltage based on the voltage V2, the transistor 12 is turned on, and the power supply voltage VGL is supplied TO the output terminal TO. As a result, the voltage of the output signal So gradually decreases, and transitions from the state of logic level 1 (VGH) to the state of logic level 0 (VGL).

In this way, in the output buffer circuit 100C, the inverters (13C, 14C) are controlled using two kinds of input signals (Si 1L, si2L, si, si 2), respectively. At this time, as shown in fig. 9B, by slightly shifting the phases of the two input signals, a period is provided in which both the transistor 11 and the transistor 12 constituting the output stage are turned off when the voltage of the input signal changes.

Therefore, according to the output buffer circuit 100C shown in fig. 9A, the through current generated between the transistor 11 and the transistor 12 of the output stage can be completely blocked.

Further, by applying the same configuration as that of fig. 9A to the output buffer circuit 100B of fig. 8, the effect of completely blocking the through current generated between the transistor 11 and the transistor 12 of the output stage as shown in fig. 9B can be achieved. Specifically, the switching can be easily realized by switching to supply the high-voltage input signal Si1 and the high-voltage input signal Si2 of fig. 9A to the gates of the transistors 13B and 14B of the output buffer circuit 100B of fig. 8.

Example 8

Fig. 10 is a block diagram showing the structure of a multi-output buffer device 200 having M (M is an integer of 2 or more) output channels.

In the multi-output buffer device 200, each of the input terminals ti0_1 to ti0_m receives a binary (logic level 0 or logic level 1) input signal si0l_1 to si0l_m, the voltage of which varies with the amplitude of the low voltage (VSS to VDD), and each of the signals expanded to the amplitude of the high voltage (VGL to VGH) is outputted as an output signal so_1 to so_m from the output terminal t0_1 to the output terminal t0_m. Thus, the input signals si0l_1 to si0l_m may be signals having different phases.

In the multi-output buffer device 200, M (M is an integer of 2 or more) systems are provided for the bias unit 30A, the bias unit 30B, or the bias unit 30C and the drive setting unit 20 shown in fig. 1,4, or 6, together with the buffer unit 10A (10B) and the level shifter 90 shown in fig. 1 (fig. 8), so that the output buffer circuit is multi-channelized.

That is, the multi-output buffer device 200 receives the input signals si0l_1 to si0l_m by using the level shifters 90_1 to 90_m each having the same configuration as the level shifter 90 shown in fig. 1 or 8.

The level shifters 90_1 to 90_m supply the generated M high voltage input signals Si0 to the respective buffer sections 10_1 to 10_m including the buffer section 10A shown in fig. 1 or the buffer section 10B shown in fig. 8.

The buffer units 10_1 to 10_m output the output signals so_1 to so_m from the respective outputs via the output terminals t0_1 to t0_m.

The bias unit 30A (30B, 30C) supplies the bias voltage VBN based on the setting signal Cs supplied from the drive setting unit 20 to the gates of the transistors 15 (15B) of the buffer units 10_1 to 10_m via the node n 3. Further, the bias unit 30A (30B, 30C) supplies the bias voltage VBP based on the setting signal Cs supplied from the drive setting unit 20 to the gates of the transistors 16 (16B) of the buffer units 10_1 to 10_m via the node n 4.

Further, a bypass capacitor for suppressing and stabilizing the variations of the bias voltage VBN and the bias voltage VBP may be connected to the node n3 and the node n 4.

As described above, in the multi-output buffer device 200, for M output channels, each of the buffer units 10_1 to 10_m and the level shifters 90_1 to 90_m of M systems having the same configuration as the buffer unit 10A shown in fig. 1 or the buffer unit 10B shown in fig. 8 is required.

However, since the drive setting unit 20 and the bias units 30A (30B, 30C) can share the buffer units 10_1 to 10_m of M systems, only one system is required regardless of the number of output channels, and therefore, the area of the entire apparatus can be reduced.

Example 9

Fig. 11 is a block diagram showing a structure of a multi-output buffer device 200A as another structure of a multi-output buffer device having M output channels.

The multi-output buffer device 200A includes M (M is an integer of 2 or more) systems for the bias unit 30A, the bias unit 30B, or the bias unit 30C and the drive setting unit 20 shown in fig. 9A, and for the buffer unit 10C, the level shifter 91, and the level shifter 92 shown in fig. 9A, to multi-channel the output buffer circuit.

That is, each of the level shifters 91_1 to 91_m having the same configuration as the level shifter 91 supplies M high-voltage input signals Si1 obtained by level-converting the input signals si1l_1 to si1l_m to each of the buffer sections 10a_1 to 10a_m having the same configuration as the buffer section 10C shown in fig. 9A. The level shifters 92_1 to 92_m each having the same configuration as the level shifter 92 supply M high-voltage input signals Si2 obtained by level-converting the input signals si2l_1 to si2l_m to the buffer sections 10a_1 to 10a_m, respectively.

The buffer sections 10a_1 to 10a_m output the output signals so_1 to so_m from the respective outputs via the output terminals t0_1 to t0_m.

The bias unit 30A (30B, 30C) supplies the bias voltage VBN based on the setting signal Cs supplied from the drive setting unit 20 to the gates of the transistors 15 of the buffer units 10a_1 to 10a_m via the node n 3. Further, the bias unit 30A (30B, 30C) supplies the bias voltage VBP based on the setting signal Cs supplied from the drive setting unit 20 to the gates of the transistors 16 of the buffer units 10a_1 to 10a_m via the node n 4.

As described above, in the multi-output buffer device 200A, for the M output channels, the buffer sections 10a_1 to 10a_m, the level shifters 91_1 to 91_m, and the level shifters 92_1 to 92_m of M systems each having the same configuration as the buffer section 10C shown in fig. 9A are required. However, since the drive setting unit 20 and the bias units 30A (30B, 30C) can share the buffer units 10a_1 to 10a_m of M systems, only one system is required regardless of the number of output channels, and therefore, the area of the entire apparatus can be reduced.

Example 10

As shown in fig. 12, the display device 300 includes a display controller 130, a data driver 120, and a display panel 150.

The display panel 150 includes gate lines GL1 to GLr (r is an integer of 2 or more) arranged along the horizontal direction of the screen, and data lines DL1 to DLk (k is an integer of 2 or more) arranged to intersect the gate lines. Display cells 154 for carrying pixels are formed at intersections of the gate lines GL1 to GLr and the data lines DL1 to DLk.

Further, the display panel 150 is provided with a scan driver 110_1 and a scan driver 110_2 integrally formed with the display panel 150. The scan driver 110_1 and the scan driver 110_2 are each constituted by a thin film transistor circuit formed integrally with pixels and wirings on an insulating substrate such as glass or plastic.

The data driver 120 receives the video data signal VDS sent from the display controller 130, generates driving signals G1 to Gk each having a voltage value corresponding to a luminance level based on the video data signal VDS, and supplies the driving signals G1 to Gk to the data lines DL1 to DLk. Further, the data driver 120 supplies r gate timing signals GSa and r gate timing signals GSb synchronized with the respective horizontal synchronizing signals included in the video data signal VDS to the scan driver 110_1 and the scan driver 110_2, respectively. Each of the gate timing signals GSa and GSb is a pulse signal having a high voltage with an amplitude of, for example, 30 to 40 volts.

The data driver 120 is typically formed of a silicon integrated circuit (INTEGRATED CIRCUIT, IC), and is mounted on the display panel 150 by a Chip On Glass (COG) or a Chip On Film (COF) or the like. Here, in the case where the data driver 120 includes a plurality of IC chips, the video data signal VDS and various control signals corresponding to the data lines that carry out the respective driving are supplied from the display controller 130 to the respective IC chips. At this time, in the case where the screen size of the display device 300 is relatively small, the display controller 130 may be built in the data driver 120. In this case, the video data signal VDS is supplied from the system side to the data driver 120.

The scan driver 110_1 is connected to one end of each of the gate lines GL1 to GLr, and the scan driver 110_2 is connected to the other end of each of the gate lines GL1 to GLr. The scan driver 110_1 sequentially generates gate selection signals at the timings of the gate timing signals GSa supplied from the data driver 120, and supplies the gate selection signals to one ends of the gate lines GLr to GL 1. The scan driver 110_2 sequentially generates gate selection signals at the timings of the gate timing signals GSb supplied from the data driver 120, and supplies the respective gate selection signals to the other ends of the gate lines GLr to GL 1.

In addition, the data driver 120 includes a gate control signal output circuit (GCO) 122_1 for outputting the r gate timing signals GSa and a gate control signal output circuit 122_2 for outputting the r gate timing signals GSb.

At this time, the gate control signal output circuit 122_1 (122_2) includes the multi-output buffer device 200 or the multi-output buffer device 200A shown in fig. 10 or 11, and r gate timing signals GSa (GSb) are output from the multi-output buffer device 200 or the multi-output buffer device 200A.

In fig. 12, a configuration is shown in which k data lines DL1 to DLk of the display panel 150 are driven by the data driver 120 having k output terminals, and a multiplexer circuit including a switch (not shown) for switching a driving signal outputted from one of the data drivers to a plurality of data lines in a time-division manner may be included. In this case, the number of outputs of the data driver is the number of k data lines divided by the time fraction. In addition, a multiplexer selection signal output circuit for supplying a multiplexer selection signal for sequentially selecting a selector switch of a multiplexer circuit on the display panel to the panel is provided in the data driver. The multiplexer selection signal output circuit outputs the same high voltage pulse signal as the gate control signal output circuit, and the same circuit as the gate control signal output circuit 122_1 (122_2) may be provided in the data driver as the multiplexer selection signal output circuit.

Therefore, by adjusting the bias voltage VBN and the bias voltage VBP by the setting signal Cs of the drive setting section 20, the voltage change rate of the output signal So outputted from the output buffer circuit is optimized, and thus, it is possible to suppress an EMI or an increase in power consumption accompanying a through current, and also to reduce an EMI generated by a charge/discharge current accompanying a load drive, and it is possible to obtain the gate timing signal GSa (GSb) having a required current driving capability (an output waveform with less distortion) at a low power consumption in an area-saving configuration.

Example 11

As shown in fig. 13, the display device 300A includes a display controller 130, a scan driver 110_1, a data driver 120A, and a display panel 150.

The display panel 150 includes scanning lines GL1 to GLr (r is an integer of 2 or more) arranged along the horizontal direction of the screen, and data lines DL1 to DLk (k is an integer of 2 or more) arranged to intersect each scanning line. Display units 154 for carrying pixels are formed at intersections of the scanning lines GL1 to GLr and the data lines DL1 to DLk.

The display controller 130 supplies the video data signal VDS including the horizontal and vertical synchronization signals, the various control signals, and the series of pixel data pieces representing the luminance levels of the respective pixels to the data driver 120A. Further, the display controller 130 supplies r gate timing signals GS synchronized with each horizontal synchronizing signal included in the video data signal VDS to the scan driver 110_1.

The data driver 120A generates driving pulse signals G1 to Gk each having a pulse width corresponding to a luminance level based on the video data signal VDS, and supplies the driving pulse signals G1 to Gk to the data lines DL1 to DLk.

The scan driver 110_1 is connected to one end of each of the gate lines GL1 to GLr, sequentially generates r scan selection pulse signals at the timing of the scan timing signal GS, and supplies each of the r scan selection pulse signals to one end of each of the scan lines GLr to GL 1.

The data driver 120A includes an output buffer 125 for outputting the drive pulse signals G1 to Gk, and the scan driver 110_1 includes an output buffer 115 for outputting the r gate selection pulse signals.

At this time, the output buffer section 115 includes the multi-output buffer device 200 or the multi-output buffer device 200A shown in fig. 10 or 11, and outputs r scan selection pulse signals from the multi-output buffer device 200 or the multi-output buffer device 200A. The output buffer section 125 also includes the multi-output buffer device 200 or the multi-output buffer device 200A shown in fig. 10 or 11, and outputs the drive pulse signals G1 to Gk from the multi-output buffer device 200 or the multi-output buffer device 200A.

By adjusting the bias voltage VBN and the bias voltage VBP, the voltage change rate of the output signal So outputted from the output buffer circuit is optimized, and therefore, it is possible to suppress the EMI accompanying the through current or the increase in power consumption, and also it is possible to reduce the EMI generated by the charge/discharge current accompanying the load driving, and it is possible to output r scan selection pulse signals having a required current driving capability (less distorted output waveform) and the driving pulse signals G1 to Gk with a small area-saving configuration at a low power consumption.

Example 12

Fig. 14 is a block diagram showing a configuration of a multi-output buffer device 200B having a pair of buffer units 10Ax and 10Ay for driving two loads X and Y, which are required to have mutually different current driving capabilities, respectively.

As shown in fig. 14, the multi-output buffer device 200B includes: a buffer section 10Ax for driving the load X connected to the output terminal TOx, a buffer section 10Ay for driving the load Y connected to the output terminal TOy, a bias section 30A, a drive setting section 20A, a level shifter 90x_1, a level shifter 90y_1, a level shifter 97y_1, and a level shifter 97y_2.

In fig. 14, the offset portion 30A is the same as the offset portion 30A shown in fig. 1, for example, and the buffer portion 10Ax has the same internal structure as the buffer portion 10A shown in fig. 1, and therefore, a detailed description of both portions is omitted.

The level shifter 90x_1 receives, as an input signal for driving the load X, a binary (logic level 0 or logic level 1) input signal Si0Lx1 whose voltage varies within the amplitude (VSS to VDD) of the low voltage. The level shifter 90x_1 supplies a high voltage input signal obtained by level-converting the amplitude of the input signal Si0Lx1 into the amplitudes (VGL to VGH) of high voltages to the buffer section 10Ax.

The buffer unit 10Ax supplies an output signal having a waveform such as the output signal So shown in fig. 9B to the load X through the output terminal TOx in response to the high-voltage input signal.

The drive setting unit 20A generates a setting signal Cs and supplies the setting signal Cs to the bias unit 30A, for example, in the same manner as the drive setting unit 20 shown in fig. 1. Further, the drive setting unit 20A supplies a drive capability control signal Pctl and a drive capability control signal Pctl, each including, for example, 2 bits, for setting the drive capability of the buffer unit 10Ay, to the level shifters 97y_1 and 97y_2, respectively.

The level shifter 97y_1 generates a 2-bit drive capability control signal Pc1 whose amplitude level of the drive capability control signal Pctl is converted into the amplitude (VGL to VGH) of a high voltage, and supplies the signal to the buffer section 10Ay.

The level shifter 97y_2 generates a 2-bit drive capability control signal Pc2 whose amplitude level of the drive capability control signal Pctl is converted into the amplitude (VGL to VGH) of the high voltage, and supplies it to the buffer section 10Ay.

The level shifter 90y_1 receives, as an input signal for driving the load Y, a binary (logic level 0 or logic level 1) input signal Si0Ly1 whose voltage varies within the amplitude (VSS to VDD) of the low voltage. The level shifter 90y_1 supplies the high voltage input signal, which has the amplitude level of the input signal Si0Ly1 converted into the amplitude of the high voltage (VGL to VGH), to the buffer portion 10Ay.

The buffer unit 10Ay supplies an output signal having a waveform such as the output signal So shown in fig. 9B to the load Y through the output terminal TOy in response to the high-voltage input signal.

The buffer unit 10Ay includes high-voltage elements, and includes the following high-voltage elements operating in a high-voltage power supply voltage range (VGL to VGH).

That is, the buffer unit 10Ay includes: the semiconductor device includes an output stage including a P-channel transistor 11y and an N-channel transistor 12y, and an output control unit 19Ay for controlling gate voltages of the transistors 11y and 12 y. The output control unit 19Ay includes the inverters 13Ay and 14Ay, the discharge rate control unit 19Ay1, and the charge rate control unit 19Ay2.

The inverter 13Ay includes an N-channel transistor 13yn and a P-channel transistor 13yp, and the inverter 14Ay includes an N-channel transistor 14yn and a P-channel transistor 14yp. The inverter 13Ay and the inverter 14Ay each receive, with their respective gates, a high-voltage input signal which is level-converted into the amplitudes VGL to VGH of the high-voltage power supply voltage by the level converter 90y_1. A source of the transistor 13yp of the inverter 13Ay is connected to the positive side power supply terminal, receives the power supply voltage VGH, and a source of the transistor 13yn is connected to the charging speed control unit 19Ay 2. A source of the transistor 14yn of the inverter 14Ay is connected to the negative side power supply terminal, receives the power supply voltage VGL, and a source of the transistor 14yp is connected to the discharge rate control unit 19Ay 1.

The discharge rate control unit 19Ay1 controls the discharge rate with respect to the load Y connected to the output terminal TOy in response to the driving capability control signal Pc 1. The discharge rate control unit 19Ay1 includes a switching element 84, a switching element 85, and P-channel transistors 81 to 83.

The power supply voltage VGH is applied to the sources of the transistors 81 to 83, and the bias voltage VBP is applied to the gates of the transistors. The drain of the transistor 81 is connected to the source of the transistor 14yp of the inverter 14Ay, and the drains of the transistors 82 and 83 are connected to the source of the transistor 14yp via the switching elements 84 and 85, respectively.

Note that, regarding the size (W/L) ratio of each of the transistors 81 to 83, for example, when the size of the transistor 81 and the transistor 82 is 1, 1:1:2.

The switching element 84 is set to an on state or an off state corresponding to the 1 st bit of the driving capability control signal Pc1, and connects the drain of the transistor 82 to the source of the transistor 14yp of the inverter 14Ay in the on state.

The switching element 85 is set to an on state or an off state in response to the 2 nd bit of the driving capability control signal Pc1, and connects the drain of the transistor 83 to the source of the transistor 14yp of the inverter 14Ay in the on state.

Fig. 15A is a diagram showing the states of the switching element 84 and the switching element 85 according to the driving capability control signal Pc1, and the magnitude (ratio) of the current flowing through the discharge rate control unit 19Ay 1.

The discharge rate control unit 19Ay1 can switch the magnitude of the current supplied to the node n2y when the transistor 12y shifts to the on state in four stages (set 1 to set 4) by the combination of the on state and the off state of the switching element 84 and the switching element 85 based on the driving capability control signal Pc1 as shown in fig. 15A. At this time, the larger the current, the faster the discharge speed with respect to the load Y. On the other hand, the smaller the current, the slower the discharge speed with respect to the load Y.

According to the above configuration, the discharge rate control unit 19Ay1 can switch the current value that receives the bias voltage VBP and supplies it to the node n2y by the driving capability control signal Pc 1. Thus, the buffer unit 10Ay can adjust the speed of discharging the load Y via the transistor 12Y, thereby optimizing the EMI reduction and the output waveform to the load Y.

The charge rate control unit 19Ay2 controls the charge rate with respect to the load Y connected to the output terminal TOy in response to the driving capability control signal Pc 2. The charge rate control unit 19Ay2 includes a switching element 95, a switching element 96, and P-channel transistors 91 to 93.

The power supply voltage VGL is applied to the source of each of the transistors 91 to 93, and the bias voltage VBN is applied to the gate of each of the transistors. The drain of the transistor 91 is connected to the source of the transistor 13yn of the inverter 13Ay, and the drains of the transistors 92 and 93 are connected to the source of the transistor 13yn via the switching elements 95 and 96, respectively.

Note that, regarding the size (W/L) ratio of each of the transistors 91 to 93, for example, when the size of the transistor 91 and the transistor 92 is 1, 1:1:2.

The switching element 95 is set to an on state or an off state corresponding to the 1 st bit of the driving capability control signal Pc2, and connects the drain of the transistor 92 to the source of the transistor 13yn of the inverter 13Ay in the on state.

The switching element 96 is set to an on state or an off state corresponding to the 2 nd bit of the driving capability control signal Pc2, and connects the drain of the transistor 93 to the source of the transistor 13yn of the inverter 13Ay in the on state.

Fig. 15B is a diagram showing states of the switching element 95 and the switching element 96 corresponding to the driving capability control signal Pc2, and magnitudes (ratios) of currents flowing through the charge rate control unit 19Ay2 in accordance with the states.

The charge rate control unit 19Ay2 can switch the magnitude of the current drawn from the node n1y when the transistor 11y shifts to the on state in four stages (set 1 to set 4) by the combination of the on state and the off state of the switching element 95 and the switching element 96 based on the driving capability control signal Pc2 as shown in fig. 15B. At this time, the larger the current, the faster the charging speed with respect to the load Y. On the other hand, the smaller the current, the slower the charging speed with respect to the load Y.

According to the above configuration, the charge speed control unit 19Ay2 can switch the current value that receives the bias voltage VBN and is extracted from the node n1y by the driving capability control signal Pc 2. Thus, the buffer unit 10Ay can adjust the speed of charging the load Y via the transistor 11Y, and optimize the EMI reduction and the output waveform to the load Y.

Therefore, in the buffer section 10Ay including the discharge rate control section 19Ay1 and the charge rate control section 19Ay2, the current driving capability of itself is adjusted by the driving capability control signals (Pctl, pctl 2), so that the bias section 30A can be shared and the load Y requiring the current driving capability different from the load X can be appropriately driven.

In the example shown in fig. 14, the pair of buffer units 10Ax and 10Ay are shared by the bias unit 30A of one system, but the plurality of buffer units 10Ax and the plurality of buffer units 10Ay may be shared by the bias unit 30A of one system.

Example 13

Fig. 16 is a block diagram showing a configuration of a multi-output buffer device 200C as another example of the multi-output buffer device in view of the above.

As shown in fig. 16, the multi-output buffer device 200C includes: each of the buffer sections 10x_1 to 10x_m (M is an integer of 2 or more) having the same structure as the buffer section 10Ax shown in fig. 14, and the buffer sections 10y_1 to 10y_f (F is an integer of 2 or more) having the same structure as the buffer section 10Ay shown in fig. 14.

Further, the multi-output buffer device 200C includes: input terminals ti0x_1 to ti0x_m for receiving the input signals si0lx_1 to si0lx_m, respectively, input terminals ti0y_1 to ti0y_f for receiving the input signals si0ly_1 to si0ly_f, respectively, level shifters 90x_1 to 90x_m, and level shifters 90y_1 to 90y_f.

The level shifters 90x_1 to 90x_m generate high-voltage input signals each having an amplitude that is respectively level-converted into a high-voltage amplitude (VGL to VGH) for the input signals si0lx_1 to si0lx_m, and supply the high-voltage input signals to the buffer sections 10x_1 to 10x_m. The level shifters 90y_1 to 90y_f generate high-voltage input signals each having an amplitude of which is respectively ground-converted into an amplitude of a high voltage (VGL to VGH) for the input signals si0ly_1 to si0ly_f, and supply the input signals to the buffer units 10y_1 to 10y_f.

The drive setting unit 20A, the level shifters 97y_1 and 97y_2, and the bias unit 30A (30B, 30C) shown in fig. 16 are the same as those described above, and therefore, their operation descriptions are omitted.

In the multi-output buffer device 200C, the bias voltage VBP and the bias voltage VBN generated by the bias sections 30A (30B, 30C) are supplied to all of the buffer sections 10x_1 to 10x_m and the buffer sections 10y_1 to 10y_f. The level shifter 97y_1 supplies the generated drive capability control signal Pc1 to the buffer sections 10y_1 to 10y_f, and the level shifter 97y_2 supplies the generated drive capability control signal Pc2 to the buffer sections 10y_1 to 10y_f.

Example 14

Fig. 17 is a block diagram showing a schematic configuration of a time-division driving display device 600 including the multi-output buffer device 200B shown in fig. 14.

The display device 600 includes a data driver 120B and a display panel 150A, wherein the display panel 150A includes gate lines GL1 to GLr (r is an integer of 2 or more) arranged along the horizontal direction of the screen, and data lines DL1 to DLm (m is an integer of 2 or more) arranged to intersect each gate line. The display device 600 employs a time division driving method in which the data lines DL1 to DLm are grouped for each of three data lines, for example, and three data lines are driven one by one in a time division manner in each of the groups in one horizontal scanning period. In the display panel 150A, display units 154 for each pixel are formed at intersections of the gate lines GL1 to GLr and the data lines DL1 to DLm.

Further, the scan drivers 110_1 and 110_2 and the multiplexers MX1 to MXk (k is an integer of 2 or more) are disposed on the display panel 150A.

The scan driver 110_1 is connected to one end of each of the gate lines GL1 to GLr, and the scan driver 110_2 is connected to the other end of each of the gate lines GL1 to GLr. The scan driver 110_1 generates gate selection signals at timings indicated by the gate line timing signal group gs_l supplied from the data driver 120B, and sequentially supplies the gate selection signals to one ends of the gate lines GL1 to GLr. The scan driver 110_2 generates a gate selection signal at a timing indicated by the gate line timing signal group gs_r supplied from the data driver 120B, and sequentially supplies the gate selection signal to the other ends of the gate lines GL1 to GLr.

The multiplexers MX1 to MXk each include: one input terminal of the grayscale voltage signals Ds1 to Dsk corresponding to each pixel, three output terminals connected to the same group of three data lines of the data lines DL1 to DLm, and switches SW1 to SW3 for connecting or disconnecting the input terminal and each of the three output terminals, respectively, are received from the data driver 120B. The switches SW1 to SW3 are set to an on state in order by the data line selection signal Sa, the data line selection signal Sb, and the data line selection signal Sc supplied from the data driver 120B.

The data driver 120B includes a semiconductor IC chip, and includes a drive setting unit 20A, a power supply voltage generating unit 99, a gradation voltage outputting unit 126, a control buffer unit BU1, and a control buffer unit BU2. The data driver 120B includes, for example, a single or a plurality of semiconductor chips, and receives the video data signal VDS and various control signals from the outside thereof.

As shown in fig. 18, the data driver 120B has a rectangular planar area having a long side along the extending direction of the gate lines of the display panel 150A, a drive setting section 20A is disposed in the central portion thereof, and a control buffer section BU1 and a control buffer section BU2 are disposed at one end and the other end in the long side direction of the drive setting section 20A, respectively.

The drive setting unit 20A acquires a series of video data pieces representing the luminance levels of the pixels based on the video data signal VDS, and supplies the series to the grayscale voltage output unit 126 (not shown in fig. 18).

The drive setting unit 20A supplies a control signal group based on the first to third data line switching signals, which sequentially set the switches SW1 to SW3 of the multiplexers MX1 to MXk to the on state, and the gate line timing signal indicating the timing of the selection gate line to the control buffer unit BU1 and the control buffer unit BU 2.

The drive setting unit 20A further includes a drive capability control unit, a reference current generation unit, and an active/passive control unit.

Each of the driving capability control units generates the setting signal cs_l and the setting signal cs_r included in the setting signal Cs and the driving capability control signal Pctl and the driving capability control signal Pctl2, and supplies the setting signal cs_l to the control buffer unit BU1 and the setting signal cs_r to the control buffer unit BU2.

The reference current generating unit generates 2 system reference currents is_l and is_r, supplies the reference currents is_l to the control buffer unit BU1, and supplies the reference currents is_r to the control buffer unit BU2.

The active/passive control unit generates an active/passive control signal en_l and an active/passive control signal en_r indicating which state the control buffer unit BU1 and the control buffer unit BU2 are set to be active or passive, supplies the active/passive control signal en_l to the control buffer unit BU1, and supplies the active/passive control signal en_r to the control buffer unit BU2. As shown in fig. 17, when the display panel 150A is driven by one data driver 120B, the active/passive control unit outputs an active/passive control signal en_l and an active/passive control signal en_r that make both the control buffer unit BU1 and the control buffer unit BU2 active. On the other hand, when the display panel 150A is driven by using the plurality of data drivers 120B, the active/passive control unit of the data driver closest to the scan driver 110_1 of the display panel 150A outputs the active/passive control signals en_l and en_r, which make the control buffer unit BU1 and the control buffer unit BU2 active and passive, respectively. The active/passive control unit of the data driver closest to the scan driver 110_2 of the display panel 150A outputs the active/passive control signals en_l and en_r, which make the control buffer unit BU1 and the control buffer unit BU2 passive and active, respectively. Further, when three or more data drivers for driving the display panel 150A are provided, the active/passive control units of the data drivers other than the two ends output the active/passive control signals en_l and en_r for making both the control buffer unit BU1 and the control buffer unit BU2 passive.

The power supply voltage generation unit 99 receives an external power supply voltage, generates various power supply voltages for operating the respective modules based on the external power supply voltage, and supplies the generated power supply voltages to the drive setting unit 20A, the gradation voltage output unit 126, the control buffer unit BU1, and the control buffer unit BU2.

The gradation voltage output section 126 generates gradation voltage signals Ds1 to Dsk having voltage values corresponding to the luminance levels of the pixels indicated by the series of video data supplied from the drive setting section 20A, and supplies the gradation voltage signals to the input terminals of the multiplexers MX1 to MXk, respectively.

The control buffer unit BU1 and the control buffer unit BU2 each include: the offset portion 30A shown in fig. 14, the multiple-output buffers 10Nx each including the plurality of buffer portions 10Ax shown in fig. 14, and the multiple-output buffers 10Ny each including the plurality of buffer portions 10Ay shown in fig. 14.

The bias units 30A of the control buffer unit BU1 and the control buffer unit BU2 supply the shared bias voltage VBP and bias voltage VBN for setting the current driving capability to the multi-output buffer 10Nx and the multi-output buffer 10Ny.

The multi-output buffers 10Nx of the control buffer unit BU1 and the control buffer unit BU2 are set to current driving capacities based on the bias voltage VBP and the bias voltage VBN. At this time, the multi-output buffer 10Nx of the control buffer unit BU1 generates the gate line timing signal group gs_l indicating the timing of the selection gate lines, and supplies it to the scan driver 110_1 as a load. The multi-output buffer 10Nx of the control buffer unit BU2 generates a gate line timing signal group gs_r indicating the timing of selecting a gate line, and supplies the same to the scan driver 110_2 as a load.

The multi-output buffers 10Ny of the control buffer unit BU1 and the control buffer unit BU2 are set to current drive capacities based on the bias voltages VBP and VBN and the drive capacity control signals (Pctl 1, pctl 2). The multi-output buffer 10Ny of the control buffer unit BU1 generates a data line selection signal Sa, a data line selection signal Sb, and a data line selection signal Sc for sequentially selecting three data lines connected to each of the multiplexers MX1 to MXk.

As shown in fig. 17, the multi-output buffer 10Ny of the control buffer unit BU1 supplies the data line selection signal Sa, the data line selection signal Sb, and the data line selection signal Sc to the multiplexers MX1 to MXk serving as loads from the left end portions of the three wirings respectively extending in the horizontal scanning direction of the display panel 150A. As shown in fig. 17, the multi-output buffer 10Ny of the control buffer unit BU2 supplies the data line selection signal Sa, the data line selection signal Sb, and the data line selection signal Sc to the multiplexers MX1 to MXk serving as loads from the right end portions of the three wirings respectively extending in the horizontal scanning direction of the display panel 150A.

In this way, in the time-division driving type display device shown in fig. 17, by applying the multi-output buffer device 200B shown in fig. 14, it is possible to drive loads (scan driver, multiplexer) of two systems requiring mutually different current driving capabilities.

Claims

1. An output buffer circuit that outputs an output signal obtained by amplifying an input signal from an output terminal, the output buffer circuit comprising:

a first transistor of a first conductivity type that supplies a first high-voltage power supply voltage to the output terminal when the first transistor is turned on in response to a voltage of the input signal received by a gate of the first transistor;

A second transistor of a second conductivity type that supplies a second high-voltage power supply voltage lower than the first high-voltage power supply voltage to the output terminal when the second transistor is turned on in response to a voltage of the input signal received by a gate of the second transistor;

a bias unit for generating a bias voltage;

An output control unit that, when the voltage of the input signal changes, changes the voltage of the gate of the transistor in the on state of the first transistor and the second transistor at a change speed corresponding to the voltage change of the input signal, thereby shifting the transistor in the on state to the off state, and changes the voltage of the gate of the transistor in the off state of the first transistor and the second transistor at a change speed based on the current value controlled by the bias voltage, thereby bringing the transistor in the off state to the on state; and

A drive setting unit for designating a voltage value of the bias voltage, generating a setting signal for setting the voltage value,

The bias section includes a bias modulation section,

The bias modulation unit receives and operates a first low-voltage power supply voltage having a voltage value equal to or lower than the first high-voltage power supply voltage and a second low-voltage power supply voltage having a voltage value equal to or higher than the second high-voltage power supply voltage, and sets the voltage value of the bias voltage to a voltage value based on the setting signal.

2. The output buffer circuit according to claim 1, wherein the bias section includes a withstand voltage protection section that excludes an influence of the first high-voltage power supply voltage and the second high-voltage power supply voltage, and controls so that a voltage applied to an output of the bias modulation section is in a low-voltage power supply voltage range from the second low-voltage power supply voltage to the first low-voltage power supply voltage.

3. The output buffer circuit according to claim 1, wherein the bias modulation section includes a current source that generates a current having a current value corresponding to the setting signal,

The bias unit includes a current-voltage conversion unit that converts the current into a voltage and outputs the converted voltage as the bias voltage.

4. The output buffer circuit according to claim 2, wherein the bias modulation section generates a voltage having a voltage value within the low-voltage power supply voltage range based on the setting signal and outputs it as the bias voltage.

5. The output buffer circuit according to claim 3, wherein the bias modulation section includes:

a reference voltage generation unit that generates a plurality of reference voltages; and

And a digital-to-analog conversion unit that selects a reference voltage based on the setting signal from the plurality of reference voltages, and outputs the selected reference voltage as the bias voltage.

6. The output buffer circuit of claim 2, wherein,

The bias modulation section generates a voltage having a voltage value within the low-voltage power supply voltage range based on the setting signal,

The bias unit includes an amplifier that outputs, as the bias voltage, an amplified voltage obtained by amplifying the voltage generated by the bias modulation unit to a voltage within a high-voltage power supply voltage range from the second high-voltage power supply voltage to the first high-voltage power supply voltage.

7. The output buffer circuit of claim 1 wherein the first low voltage supply voltage is less than the first high voltage supply voltage and the second low voltage supply voltage is above the second high voltage supply voltage or the first low voltage supply voltage is below the first high voltage supply voltage and the second low voltage supply voltage is greater than the second high voltage supply voltage.

8. The output buffer circuit according to any one of claims 1 to 7, wherein the bias section generates a pair of a first bias voltage and a second bias voltage as the bias voltages,

The output control unit includes:

A first node supplying a first voltage to a gate of the first transistor;

A second node supplying a second voltage to a gate of the second transistor;

a third transistor of a first conductivity type, which receives the input signal by a gate, and supplies a first power supply voltage to the first node when the input signal is turned on, thereby causing the first transistor to shift to an off state;

A fourth transistor of a second conductivity type, which receives the input signal by a gate, and supplies a second power supply voltage to the second node when the input signal is turned on, thereby causing the second transistor to shift to an off state;

A fifth transistor of a second conductivity type, which receives the first bias voltage by a gate, and when activated in response to a voltage change of the input signal, changes the first voltage of the first node to a second power supply voltage side at a change speed based on a current value controlled by the first bias voltage, thereby shifting the first transistor to an on state; and

And a sixth transistor of the first conductivity type, which receives the second bias voltage at a gate electrode, and when activated in response to a voltage change of the input signal, changes the second voltage of the second node to a first power supply voltage side at a rate of change of a current value controlled by the second bias voltage, thereby shifting the second transistor to an on state.

9. The output buffer circuit according to any one of claims 1 to 7, wherein the bias section generates a pair of a first bias voltage and a second bias voltage as the bias voltages,

The output control unit includes:

A first inverter that receives the first high-voltage power supply voltage using its positive power supply terminal and supplies a voltage of a signal obtained by inverting a phase of the input signal to a gate of the first transistor;

A third transistor of a second conductivity type, a drain of which is connected to a negative side power supply terminal of the first inverter, receiving the second high voltage power supply voltage with a source, and receiving the first bias voltage with a gate;

a second inverter that receives the second high-voltage power supply voltage using its negative-side power supply terminal and supplies a voltage of a signal obtained by inverting the phase of the input signal to a gate of the second transistor; and

And a fourth transistor of the first conductivity type, a drain of which is connected to a positive side power supply terminal of the second inverter, receives the first high voltage power supply voltage by a source, and receives the second bias voltage by a gate.

10. The output buffer circuit according to any one of claims 1 to 7, wherein the bias section generates a pair of a first bias voltage and a second bias voltage as the bias voltages,

The output control unit includes:

a third transistor of a first conductivity type that receives the input signal with a gate and supplies the first high-voltage power supply voltage to a first node connected to the gate of the first transistor when the third transistor is turned on in response to the input signal;

A fourth transistor of a second conductivity type that receives the input signal with a gate and supplies the second high-voltage power supply voltage to a second node connected to the gate of the second transistor when the transistor is turned on in response to the input signal;

a fifth transistor of a second conductivity type receiving the first bias voltage with a gate, a source connected to the second node and a drain connected to the first node; and

And a sixth transistor of the first conductivity type receiving the second bias voltage with a gate, a source connected to the first node and a drain connected to the second node.

11. The output buffer circuit according to any one of claims 1 to 7, wherein the bias section generates a pair of a first bias voltage and a second bias voltage as the bias voltages,

The input signal is a first input signal, and a second input signal having an early rising timing and a late falling timing of a voltage with respect to the first input signal,

The output control unit includes:

A first inverter that receives the first high-voltage power supply voltage using its positive power supply terminal and supplies a voltage of a signal obtained by inverting a phase of the first input signal to a gate of the first transistor;

A second inverter that receives the second high-voltage power supply voltage using its negative-side power supply terminal and supplies a voltage of a signal obtained by inverting the phase of the second input signal to a gate of the second transistor; and

12. An output buffer circuit that outputs first to mth output signals obtained by amplifying first to mth input signals, M being an integer of 2 or more, the output buffer circuit comprising:

a bias unit for generating a bias voltage;

A drive setting unit that designates a voltage value of the bias voltage and generates a setting signal for setting the voltage value; and

First to Mth buffer sections for receiving the first to Mth input signals, respectively, and outputting the first to Mth output signals via respective output terminals,

The first to M-th buffer sections each include:

A first transistor of a first conductivity type that supplies a first high-voltage power supply voltage to the output terminal thereof when the first transistor is turned on in response to a voltage of the input signal received by the gate thereof;

A second transistor of a second conductivity type that supplies a second high-voltage power supply voltage lower than the first high-voltage power supply voltage to the output terminal of the second transistor when the second transistor is turned on in response to a voltage of the input signal received by the gate of the second transistor; and

An output control unit that, when the voltage of the input signal changes, changes the voltage of the gate of the transistor in the on state of the first transistor and the second transistor at a change speed corresponding to the voltage change of the input signal to switch the transistor in the on state to the off state, changes the voltage of the gate of the transistor in the off state of the first transistor and the second transistor at a change speed based on the current value controlled by the bias voltage to switch the transistor in the off state to the on state,

The offset portion is provided in common with each of the first to M-th buffer portions,

The bias unit includes a bias modulation unit that receives and operates a first low-voltage power supply voltage having a voltage value less than or equal to the first high-voltage power supply voltage and a second low-voltage power supply voltage having a voltage value greater than or equal to the second high-voltage power supply voltage, sets the voltage value of the bias voltage to a voltage value based on the set signal, and supplies the bias voltage having the voltage value set by the bias modulation unit to each of the first to M-th buffer units.

13. A display driver for driving a display panel corresponding to a video signal, the display panel comprising: a plurality of scanning lines arranged along a horizontal direction of a screen, and a plurality of data lines arranged to intersect the plurality of scanning lines, wherein the display driver includes:

A data driver for generating a plurality of driving signals based on the video signal and supplying the driving signals to the plurality of data lines; and

A scan driver for driving the plurality of scan lines at a timing corresponding to the plurality of scan timing signals,

The data driver includes a scan control signal output circuit outputting the plurality of scan timing signals,

The scan control signal output circuit includes the output buffer circuit of claim 12.

14. A display driver for driving a display panel of a passive matrix type corresponding to a video signal, the display panel comprising: a plurality of scanning lines arranged along a horizontal direction of a screen, and a plurality of data lines arranged to intersect the plurality of scanning lines, wherein the display driver includes:

a data driver including a first output buffer section that outputs a plurality of driving pulse signals having pulse widths corresponding to luminance levels of pixels shown by the video signal to a plurality of data lines; and

A scan driver including a second output buffer section outputting a plurality of scan pulse signals to the plurality of scan lines,

The first output buffer section and the second output buffer section each include the output buffer circuit of claim 12.

15. A display device includes: a display panel including a plurality of scanning lines arranged along a horizontal direction of a screen and a plurality of data lines arranged to intersect the plurality of scanning lines; and a display driver for driving the display panel in response to the video signal, wherein the display device is characterized in that,

The display driver has:

a scan driver driving a plurality of scan lines at a timing corresponding to a plurality of scan timing signals; and

A data driver for generating a plurality of driving signals based on the video signal and supplying the driving signals to the plurality of data lines, including a scan control signal output circuit for outputting the plurality of scan timing signals,

16. The output buffer circuit according to claim 12, wherein the output control section of at least one of the first to M-th buffer sections has a charge-discharge speed control section including a plurality of transistors connected in parallel to each other and receiving the bias voltage by their respective gates and generating the current value by a combined current of a current corresponding to the bias voltage,

The charge/discharge rate control unit receives a driving capability control signal, and activates or deactivates each of the plurality of transistors in accordance with the driving capability control signal, thereby changing the current value of the combined current.

17. The output buffer circuit according to claim 16, wherein the output control section includes:

A first node that supplies a voltage corresponding to the input signal as a first voltage to a gate of the first transistor; and

A second node for supplying a voltage corresponding to the input signal as a second voltage to a gate of the second transistor,

The charge/discharge rate control unit extracts the combined current corresponding to the bias voltage from the first node when the first transistor is in an on state, and supplies the combined current corresponding to the bias voltage to the second node when the second transistor is in an on state.

18. A data driver for driving a display panel corresponding to an image data signal, the display panel comprising: a first data line to an mth data line extending along a horizontal direction of a display screen and a plurality of gate lines extending along a vertical direction of the display screen, m being an integer of 2 or more; a scan driver receiving a gate timing signal and supplying a gate selection signal to each of the plurality of gate lines at a timing corresponding to the gate timing signal; and (m/j) multiplexers provided for each j data lines of the first to m-th data lines, each of the multiplexers having one input terminal and connecting each of the j data lines to the one input terminal in order in response to a data line selection signal, j being an integer of 2 or more, the data driver comprising:

a gradation voltage output unit that generates (m/j) gradation voltage signals having voltage values corresponding to luminance levels of the pixels based on the video data signals, and supplies the gradation voltage signals to the input terminals of the (m/j) multiplexers, respectively;

a drive setting unit that generates the drive capability control signal; and

The output buffer circuit of claim 16,

The output buffer circuit outputs a predetermined number of the first to M-th output signals from the output terminal as the gate timing signal, and outputs other output signals than the predetermined number of the first to M-th output signals from the output terminal as the data line selection signal,

In the semiconductor integrated circuit chip constituting the data driver, the bias section and the plurality of buffer sections are disposed at one end and the other end in the longitudinal direction of the semiconductor integrated circuit chip, respectively, and the drive setting section is disposed at a central section in the semiconductor integrated circuit chip.

19. A display device includes:

A display panel, the display panel comprising: a first data line to an mth data line extending along a horizontal direction of a display screen and a plurality of gate lines extending along a vertical direction of the display screen, m being an integer of 2 or more; a scan driver receiving a gate timing signal and supplying a gate selection signal to each of the plurality of gate lines at a timing corresponding to the gate timing signal; and (m/j) multiplexers provided for each j data lines of the first to m-th data lines, each of the multiplexers having one input terminal and connecting each of the j data lines to the one input terminal in order corresponding to a data line selection signal, j being an integer of 2 or more; and

A data driver for driving the display panel in response to the image data signal, wherein the display device is characterized in that,

The data driver includes:

a drive setting unit that generates the drive capability control signal; and

The output buffer circuit of claim 16,