CN117936569B - Semiconductor device and preparation method thereof - Google Patents

Abstract

The invention discloses a semiconductor device and a preparation method thereof. The semiconductor structure includes: the semiconductor device comprises a substrate, an epitaxial layer and a gate structure, wherein the gate structure comprises a doped III-V semiconductor layer and a gate; a field plate structure comprising a field plate and an etch stop layer; the contact through hole structure is positioned on one side of the second insulating layer, which is far away from the field plate structure, and comprises a first contact through hole, a second contact through hole and a third contact through hole which are arranged at intervals; the first contact exposes at least part of the etching barrier layer; exposing part of the epitaxial layer through the second contact through hole; exposing part of the epitaxial layer by the third contact through hole; the first contact through hole, the second contact through hole and the third contact through hole share the same mask plate and are synchronously formed through an etching process. According to the technical scheme provided by the embodiment of the invention, when the contact through holes correspondingly connected with the field plate, the source electrode and the drain electrode are prepared, the number of required masks is reduced, and the preparation cost of the semiconductor device is reduced.

Description

Semiconductor device and preparation method thereof

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof.

Background technique

The existing high electron mobility transistor (HEMT) requires a large number of masks when preparing contact holes corresponding to the field plate, the source and the drain, resulting in a high manufacturing cost of the semiconductor device.

Summary of the invention

The present invention provides a semiconductor device and a preparation method thereof, which can reduce the number of required masks when preparing contact through holes correspondingly connected to field plates, source electrodes and drain electrodes, thereby reducing the preparation cost of the semiconductor device.

According to one aspect of the present invention, there is provided a semiconductor device, comprising:

substrate;

an epitaxial layer, the epitaxial layer being located on one side of the substrate;

A gate structure, the gate structure comprising a doped III-V semiconductor layer and a gate, the doped III-V semiconductor layer is located on a side of the epitaxial layer away from the substrate, and the gate is located on a surface of the doped III-V semiconductor layer away from the epitaxial layer;

A first insulating layer, wherein the first insulating layer is located on a side of the gate away from the doped III-V semiconductor layer;

A field plate structure, the field plate structure comprising a field plate and an etch stop layer, the field plate being located on a side of the first insulating layer away from the gate structure, and the etch stop layer being located on a side of the field plate away from the first insulating layer;

a second insulating layer, wherein the second insulating layer is located on a side of the etching stop layer away from the field plate;

A contact through-hole structure, the contact through-hole structure is located on a side of the second insulating layer away from the field plate structure, the contact through-hole structure comprises a first contact through-hole, a second contact through-hole and a third contact through-hole arranged at intervals; the first contact through-hole penetrates the second insulating layer and exposes at least a portion of the etching barrier layer; the second contact through-hole penetrates the second insulating layer and the first insulating layer and exposes a portion of the epitaxial layer; the third contact through-hole penetrates the second insulating layer and the first insulating layer and exposes a portion of the epitaxial layer; the first contact through-hole, the second contact through-hole and the third contact through-hole share the same mask and are formed synchronously by an etching process;

A conductive filling layer is located in the first contact through hole, the second contact through hole and the third contact through hole.

Optionally, a surface of the second insulating layer away from the field plate structure is a plane;

and / or,

The semiconductor device also includes a field plate connecting electrode, a source electrode and a drain electrode;

The field plate connecting electrode is located on a surface of the second insulating layer away from the field plate structure, and the orthographic projection of the field plate connecting electrode on the substrate covers part or all of the orthographic projection of the first contact through hole on the substrate;

The source electrode is located on a surface of the second insulating layer away from the field plate structure, and the orthographic projection of the source electrode on the substrate covers part or all of the orthographic projection of the second contact through hole on the substrate;

The drain is located on a surface of the second insulating layer away from the field plate structure, and an orthographic projection of the drain on the substrate covers part or all of an orthographic projection of the third contact through hole on the substrate.

Optionally, the epitaxial layer includes a channel layer and a barrier layer;

The channel layer is located on one side of the substrate;

The barrier layer is located on a surface of the channel layer away from the substrate; the barrier layer comprises a semiconductor layer doped with aluminum atoms.

Optionally, the field plate includes a first sub-field plate and a second sub-field plate, the etch stop layer includes a first sub-etch stop layer and a second sub-etch stop layer; the field plate structure further includes a third insulating layer;

The first sub-field plate is located on a surface of the first insulating layer away from the gate structure;

The first sub-etching stop layer is located on a surface of the first sub-field plate away from the first insulating layer;

The third insulating layer is located on a surface of the first sub-etching stop layer away from the first sub-field plate;

The second sub-field plate is located on a surface of the third insulating layer away from the first sub-etching stop layer;

The second sub-etching stop layer is located on a surface of the second sub-field plate away from the third insulating layer;

The first contact via comprises a first sub-contact via and a second sub-contact via which are spaced apart from each other, wherein the first sub-contact via penetrates the second insulating layer and the third insulating layer and exposes at least a portion of the first sub-etching barrier layer; and the second sub-contact via penetrates the second insulating layer and exposes at least a portion of the second sub-etching barrier layer.

Optionally, the etch stop layer includes at least one of aluminum nitride, aluminum oxide and gallium aluminum nitride.

According to another aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

providing a substrate;

forming an epitaxial layer on one side of the substrate;

forming a doped III-V semiconductor layer on a side of the epitaxial layer away from the substrate;

forming a gate on a surface of the doped III-V semiconductor layer away from the substrate, wherein the doped III-V semiconductor layer and the gate constitute a gate structure;

forming a first insulating layer on a side of the gate away from the doped III-V semiconductor layer;

forming a field plate structure on a side of the first insulating layer away from the gate structure, wherein the field plate structure comprises a field plate and an etch stop layer, the field plate is located on a side of the first insulating layer away from the gate structure, and the etch stop layer is located on a side of the field plate away from the first insulating layer;

forming a second insulating layer on a side of the etch stop layer away from the field plate;

Sharing the same mask, a first contact hole, a second contact hole and a third contact hole that are spaced apart are simultaneously formed on a side of the second insulating layer away from the field plate structure by an etching process, wherein the first contact hole, the second contact hole and the third contact hole constitute a contact hole structure; the first contact hole penetrates the second insulating layer and exposes at least a portion of the etching barrier layer; the second contact hole penetrates the second insulating layer and the first insulating layer and exposes a portion of the epitaxial layer; the third contact hole penetrates the second insulating layer and the first insulating layer and exposes a portion of the epitaxial layer;

A conductive filling layer is formed in the first contact via, the second contact via, and the third contact via.

Optionally, before forming the contact through-hole structure on the side of the second insulating layer away from the field plate structure, the method further includes:

performing a planarization process on the second insulating layer so that a surface of the second insulating layer away from the field plate structure is a plane;

and / or,

After forming a contact through-hole structure on a side of the second insulating layer away from the field plate structure, the method further comprises:

forming a field plate connecting electrode on a surface of the second insulating layer away from the field plate structure, wherein an orthographic projection of the field plate connecting electrode on the substrate covers part or all of an orthographic projection of the first contact through hole on the substrate;

forming a source electrode on a surface of the second insulating layer away from the field plate structure, wherein an orthographic projection of the source electrode on the substrate covers part or all of an orthographic projection of the second contact through hole on the substrate;

A drain is formed on a surface of the second insulating layer away from the field plate structure, wherein an orthographic projection of the drain on the substrate covers a part or all of an orthographic projection of the third contact hole on the substrate.

Optionally, forming an epitaxial layer on one side of the substrate includes:

forming a channel layer on one side of the substrate;

A barrier layer is formed on a surface of the channel layer away from the substrate, wherein the barrier layer is a semiconductor layer doped with aluminum atoms.

Optionally, the field plate includes a first sub-field plate and a second sub-field plate, the etch stop layer includes a first sub-etch stop layer and a second sub-etch stop layer; the field plate structure further includes a third insulating layer;

Forming a field plate structure on a side of the first insulating layer away from the gate structure comprises:

forming a first subfield plate on a surface of the first insulating layer away from the gate structure;

forming a first sub-etching stop layer on a surface of the first sub-field plate away from the first insulating layer;

forming a third insulating layer on a surface of the first sub-etching stop layer away from the first sub-field plate;

forming a second sub-field plate on a surface of the third insulating layer away from the first sub-etching stop layer;

forming a second sub-etching stop layer on a surface of the second sub-field plate away from the third insulating layer;

Sharing the same mask, synchronously forming a first contact through hole, a second contact through hole and a third contact through hole arranged at intervals on a side of the second insulating layer away from the field plate structure by an etching process comprises:

Sharing the same mask, a first contact hole, a second contact hole and a third contact hole, which are spaced apart and include a first sub-contact hole and a second sub-contact hole, are simultaneously formed on a side of the second insulating layer away from the field plate structure through an etching process, wherein the first sub-contact hole and the second sub-contact hole are spaced apart, the first sub-contact hole penetrates the second insulating layer and the third insulating layer and exposes at least a portion of the first sub-etching barrier layer; the second sub-contact hole penetrates the second insulating layer and exposes at least a portion of the second sub-etching barrier layer.

Optionally, forming a field plate structure on a side of the first insulating layer away from the gate structure includes:

A field plate structure including a field plate and an etch stop layer is formed on a side of the first insulating layer away from the gate structure, wherein the etch stop layer includes at least one of aluminum nitride, aluminum oxide, and aluminum gallium nitride.

In the technical solution provided by the embodiment of the present invention, the first contact hole, the second contact hole and the third contact hole share the same mask and are formed synchronously through an etching process. Although the etching depths of the first contact hole, the second contact hole and the third contact hole are different, since the field plate surface is protected by an etching barrier layer, the field plate (the field plate material is, for example, titanium nitride) will not be etched through or a large amount of etching loss will not be caused. In addition, the above technical solution also realizes the use of a mask to synchronously etch the first contact hole that exposes at least part of the etching barrier layer, the second contact hole that exposes part of the epitaxial layer, and the third contact hole that exposes part of the epitaxial layer, thereby reducing the number of masks used, and setting an ohmic contact layer, simplifying the film structure of the semiconductor device, and reducing costs.

It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

FIG1 is a flow chart of a method for preparing a semiconductor device provided by the prior art;

Figures 2 to 12 are structural diagrams corresponding to the steps in Figure 1;

13 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

14 is a flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention;

15 to 23 are schematic diagrams of structures corresponding to the steps in FIG. 14 ;

FIG24 is a schematic diagram of the process including S207, before S207 and after S207 in FIG14;

FIG25 is a schematic diagram of the process included in S201 in FIG14;

FIG. 26 is a schematic diagram of the process included in S205 in FIG. 14 .

Detailed ways

In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or devices that are not clearly listed or inherent to these processes, methods, products or devices.

As described in the above background technology, in the existing semiconductor devices, a large number of masks are required when preparing contact holes corresponding to the field plates, the source and the drain, resulting in a large preparation cost of the semiconductor device. As shown in Figure 1 and Figures 2 to 12, the existing method for preparing a semiconductor device includes: S100, providing a substrate, forming an epitaxial layer, a gate structure and a first insulating layer on one side of the substrate, wherein the gate structure includes a doped III-V semiconductor layer and a gate. S101, forming a first field plate on the surface of the first insulating layer away from the gate structure. S102, forming a second insulating layer on the surface of the first field plate away from the first insulating layer. S103, forming a second field plate on the surface of the second insulating layer away from the first field plate. S104, forming a third insulating layer on the surface of the second field plate away from the second insulating layer. S105, forming a first contact hole and a second contact hole arranged at intervals, the first contact hole exposing the epitaxial layer, and the second contact hole exposing the epitaxial layer. S106, forming a first conductive filling layer on the surface of the third insulating layer away from the second field plate, and the first conductive filling layer extends to the first contact hole and the second contact hole. S107. Pattern the first conductive filling layer to expose part of the third insulating layer. S108. Form a fourth insulating layer, wherein the fourth insulating layer covers the third insulating layer and the first conductive filling layer. S109. Form a third contact through-hole, a fourth contact through-hole, a fifth contact through-hole and a sixth contact through-hole on a side of the fourth insulating layer away from the third insulating layer. S110. Form a second conductive filling layer in the third contact through-hole, the fourth contact through-hole, the fifth contact through-hole and the sixth contact through-hole. S111. Form a source, a drain, a first field plate connecting electrode and a second field plate connecting electrode, wherein the source covers the third contact through-hole, the drain covers the sixth contact through-hole, the first field plate connecting electrode covers the fourth contact through-hole, and the second field plate connecting electrode covers the fifth contact through-hole. In Figures 2 to 12, the reference numerals are as follows: 100-substrate, 101-epitaxial layer, 102-doped III-V semiconductor layer, 103-gate, 104-first insulating layer, 105-first field plate, 106-second insulating layer, 107-second field plate, 108-third insulating layer, 109-first conductive filling layer, 110-fourth insulating layer, T1-first contact hole, T2-second contact hole, CT1-third contact hole, CT2-fourth contact hole, CT3-fifth contact hole, CT4-sixth contact hole, 111-second conductive filling layer, 112-source, 113-first field plate connecting electrode, 114-second field plate connecting electrode, 115-drain.

As shown in Figures 2 to 12, in the preparation of the semiconductor device provided by the prior art, a layer of mask is required in the process of forming the first contact through hole T1 and the second contact through hole T2. A layer of mask is required in the process of patterning the first conductive filling layer 109. A layer of mask is required in the process of forming the third contact through hole CT1, the fourth contact through hole CT2, the fifth contact through hole CT3 and the sixth contact through hole CT4. Therefore, in the existing semiconductor device, a large number of mask plates are required when preparing the contact through holes corresponding to the field plate, the source 112 and the drain 115, resulting in a large preparation cost of the semiconductor device. Moreover, during the formation of the third contact through hole CT1, the fourth contact through hole CT2, the fifth contact through hole CT3 and the sixth contact through hole CT4, due to the different etching depths of the third contact through hole CT1, the fourth contact through hole CT2, the fifth contact through hole CT3 and the sixth contact through hole CT4, the synchronous stopping of the third contact through hole CT1, the fourth contact through hole CT2, the fifth contact through hole CT3 and the sixth contact through hole CT4 cannot be achieved, and during the formation of the fourth contact through hole CT2 and the fifth contact through hole CT3, it is easy to cause etching penetration of the field plate material (the field plate material is, for example, titanium nitride) or a large amount of etching loss.

In view of the above technical problems, the embodiments of the present invention provide the following technical solutions:

As shown in Figure 13, Figure 13 is a structural schematic diagram of a semiconductor device provided according to an embodiment of the present invention, the semiconductor device includes: a substrate 200; an epitaxial layer 201, the epitaxial layer 201 is located on one side of the substrate 200; a gate structure, the gate structure includes a doped III-V semiconductor layer 204 and a gate 205, the doped III-V semiconductor layer 204 is located on the side of the epitaxial layer 201 away from the substrate 200, and the gate 205 is located on the surface of the doped III-V semiconductor layer 204 away from the epitaxial layer 201; a first insulating layer 206, the first insulating layer 206 is located on the side of the gate 205 away from the doped III-V semiconductor layer 204; a field plate structure, the field plate structure includes a field plate 218 and an etch stop layer 219, the field plate 218 is located on the side of the first insulating layer 206 away from the gate structure, and the etch stop layer 219 is located on the side of the field plate 218 away from the first insulating layer 206; a second insulating layer 209, the second insulating layer 209 is located on the etching stop layer 219. The etching barrier layer 219 is on a side away from the field plate 218; the contact through-hole structure is located on a side of the second insulating layer 209 away from the field plate structure, and the contact through-hole structure includes a first contact through-hole 220, a second contact through-hole CT01 and a third contact through-hole CT04 arranged at intervals; the first contact through-hole 220 penetrates the second insulating layer 209 and exposes at least a portion of the etching barrier layer 219; the second contact through-hole CT01 penetrates the second insulating layer 209 and the first insulating layer 206 and exposes a portion of the epitaxial layer 201; the third contact through-hole CT04 penetrates the second insulating layer 209 and the first insulating layer 206 and exposes a portion of the epitaxial layer 201; the first contact through-hole 220, the second contact through-hole CT01 and the third contact through-hole CT04 share the same mask and are formed simultaneously through an etching process; a conductive filling layer 213, the conductive filling layer 213 is located in the first contact through-hole 220, the second contact through-hole CT01 and the third contact through-hole CT04.

In this embodiment, the field plate structure includes a field plate 218 and an etch stop layer 219, the field plate 218 includes a first sub-field plate 207 and a second sub-field plate 210, and the etch stop layer 219 includes a first sub-etch stop layer 208 and a second sub-etch stop layer 211; the field plate structure also includes a third insulating layer 212, and the third insulating layer 212 is used to insulate and space the first sub-field plate 207 and the second sub-field plate 210. The first contact through hole 220 includes a first sub-contact through hole CT02 and a second sub-contact through hole CT03.

In the technical solution provided by the embodiment of the present invention, the first contact hole 220, the second contact hole CT01 and the third contact hole CT04 share the same mask and are formed synchronously through the etching process. Although the etching depths of the first contact hole 220, the second contact hole CT01 and the third contact hole CT04 are different, since the surface of the field plate 218 is protected by the etching barrier layer 219, the etching penetration of the field plate 218 (the field plate material is, for example, titanium nitride) or a large amount of etching loss will not be caused. In addition, the above technical solution also realizes the use of a mask to simultaneously etch the first contact hole 220 that exposes at least part of the etching barrier layer 219, the second contact hole CT01 that exposes part of the epitaxial layer 201, and the third contact hole CT04 that exposes part of the epitaxial layer 201, thereby reducing the number of masks used, and setting an ohmic contact layer, simplifying the film structure of the semiconductor device, and reducing the cost.

Optionally, on the basis of the above technical solution, as shown in Figure 13, the surface of the second insulating layer 209 away from the field plate structure is a plane; and/or, the semiconductor device also includes a field plate connecting electrode 221, a source 214 and a drain 217; the field plate connecting electrode 221 is located on the surface of the second insulating layer 209 away from the field plate structure, and the orthographic projection of the field plate connecting electrode 221 on the substrate 200 covers part or all of the orthographic projection of the first contact hole 220 on the substrate 200; the source 214 is located on the surface of the second insulating layer 209 away from the field plate structure, and the orthographic projection of the source 214 on the substrate 200 covers part or all of the orthographic projection of the second contact hole CT01 on the substrate 200; the drain 217 is located on the surface of the second insulating layer 209 away from the field plate structure, and the orthographic projection of the drain 217 on the substrate 200 covers part or all of the orthographic projection of the third contact hole CT04 on the substrate 200.

Specifically, the surface of the second insulating layer 209 away from the field plate structure is planar, providing a smooth surface for the preparation of the first contact via 220, the second contact via CT01 and the third contact via CT04, the conductive filling layer 213, and the field plate connecting electrode 221, the source 214 and the drain 217, thereby improving the yield of the device.

The field plate connection electrode 221 is connected to the field plate 218 through the conductive filling layer 213. Optionally, in this embodiment, the field plate connection electrode 221 includes a first sub-field plate connection electrode 215 and a second sub-field plate connection electrode 216. The first sub-field plate connection electrode 215 is connected to the first sub-field plate 207 through the conductive filling layer 213. The second sub-field plate connection electrode 216 is connected to the second sub-field plate 210 through the conductive filling layer 213.

The source electrode 214 is connected to the barrier layer 203 in the epitaxial layer 201 through the conductive filling layer 213. The drain electrode 217 is connected to the barrier layer 203 in the epitaxial layer 201 through the conductive filling layer 213.

Optionally, based on the above technical solution, as shown in Figure 13, the epitaxial layer 201 includes a channel layer 202 and a barrier layer 203; the channel layer 202 is located on one side of the substrate 200; the barrier layer 203 is located on the surface of the channel layer 202 away from the substrate 200; the barrier layer 203 includes a semiconductor layer doped with aluminum atoms.

There is a large concentration of two-dimensional electron gas near the interface between the channel layer 202 and the barrier layer 203, which is used to improve the device performance. The barrier layer 203 includes a semiconductor layer doped with aluminum atoms, preferably AlGaN.

The barrier layer 203 includes a semiconductor layer doped with aluminum atoms. During the simultaneous etching of the first contact hole 220, the second contact hole CT01 and the third contact hole CT04, the aluminum atoms react with the F-containing etching gas to generate non-volatile substances as an etching barrier layer. Moreover, since the surface of the field plate 218 is protected by the etching barrier layer 219, the simultaneous etching of the first contact hole 220, the second contact hole CT01 and the third contact hole CT04 can be achieved, and over-etching of the field plate 218 and the barrier layer 203 can be avoided.

The doped III-V semiconductor layer 204 is used to deplete the two-dimensional electron gas on the surface of the barrier layer 203 below it, and can turn off the semiconductor device at a low voltage. The channel layer 202 includes one or more of GaN, AlGaN and InGaN, preferably GaN. The doped III-V semiconductor layer 204 includes p-type doped AlN or GaN, preferably p-type doped GaN.

Optionally, based on the above technical solution, as shown in FIG13, the field plate 218 includes a first sub-field plate 207 and a second sub-field plate 210, and the etch stop layer 219 includes a first sub-etch stop layer 208 and a second sub-etch stop layer 211; the field plate structure further includes a third insulating layer 212; the first sub-field plate 207 is located on a surface of the first insulating layer 206 away from the gate structure; the first sub-etch stop layer 208 is located on a surface of the first sub-field plate away from the first insulating layer 206; the third insulating layer 212 is located on a surface of the first sub-etch stop layer 208 away from the first sub-field plate 207; and the second sub-field The plate 210 is located on the surface of the third insulating layer 212 away from the first sub-etching blocking layer 208; the second sub-etching blocking layer 211 is located on the surface of the second sub-field plate 210 away from the third insulating layer 212; the first contact through hole 220 includes a first sub-contact through hole CT02 and a second sub-contact through hole CT03 that are spaced apart, the first sub-contact through hole CT02 penetrates the second insulating layer 209 and the third insulating layer 212, and exposes at least a portion of the first sub-etching blocking layer 208; the second sub-contact through hole CT03 penetrates the second insulating layer 209, and exposes at least a portion of the second sub-etching blocking layer 211.

Specifically, the first sub-contact hole CT02, the second sub-contact hole CT03, the second contact hole CT01 and the third contact hole CT04 share the same mask and are formed synchronously through an etching process. Although the etching depths of the first sub-contact hole CT02, the second sub-contact hole CT03, the second contact hole CT01 and the third contact hole CT04 are different, since the surfaces of the first sub-field plate 207 and the second sub-field plate 210 are protected by the etching barrier layer 219, the first sub-field plate 207 and the second sub-field plate 210 (the field plate material is, for example, titanium nitride) will not be etched through or a large amount of etching loss will not be caused. The barrier layer 203 includes a semiconductor layer doped with aluminum atoms. During the process of simultaneously etching the first sub-contact hole CT02, the second sub-contact hole CT03, the second contact hole CT01 and the third contact hole CT04, the aluminum atoms will react with the F-containing etching gas to generate a non-volatile substance as an etching barrier layer, thereby achieving simultaneous etching of the first contact hole 220, the second contact hole CT01 and the third contact hole CT04, and avoiding over-etching of the field plate 218 and the barrier layer 203.

Optionally, based on the above technical solution, as shown in FIG. 13 , the etch stop layer 219 includes at least one of aluminum nitride, aluminum oxide and aluminum gallium nitride.

The etching stop layer 219 includes at least one of aluminum nitride, aluminum oxide and aluminum gallium nitride. During the simultaneous etching of the first contact hole 220, the second contact hole CT01 and the third contact hole CT04, the aluminum atoms react with the F-containing etching gas to generate non-volatile substances as an etching stop layer. Since the barrier layer 203 includes a semiconductor layer doped with aluminum atoms, the first contact hole 220, the second contact hole CT01 and the third contact hole CT04 can be simultaneously etched, and over-etching of the field plate 218 and the barrier layer 203 can be avoided.

The embodiment of the present invention also provides a method for preparing a semiconductor device. As shown in FIG14 , FIG14 is a flow chart of a method for preparing a semiconductor device provided according to an embodiment of the present invention, and the method for preparing a semiconductor device includes the following steps:

S200 , providing a substrate.

As shown in Fig. 15, a substrate 200 is provided. The substrate 200 may be a silicon substrate or a semiconductor material such as sapphire.

S201 , forming an epitaxial layer on one side of the substrate.

As shown in FIG15 , an epitaxial layer 201 is formed on one side of a substrate 200. In the process of forming the epitaxial layer 201, a channel layer 202 is first formed on one side of the substrate 200, and then a barrier layer 203 is formed on a surface of the channel layer 202 away from the substrate 200. A large concentration of two-dimensional electron gas exists near the interface between the channel layer 202 and the barrier layer 203, which is used to improve device performance.

S202 , forming a doped III-V semiconductor layer on a side of the epitaxial layer away from the substrate.

As shown in FIG15 , a doped III-V semiconductor layer 204 is formed on the side of the epitaxial layer 201 away from the substrate 200. The doped III-V semiconductor layer 204 is used to deplete the two-dimensional electron gas on the surface of the barrier layer 203 below it, and can shut down the semiconductor device at a low voltage. The channel layer 202 includes one or more of GaN, AlGaN and InGaN, preferably GaN. The doped III-V semiconductor layer 204 includes p-type doped AlN or GaN, preferably p-type doped GaN. The barrier layer 203 includes a semiconductor layer doped with aluminum atoms, preferably AlGaN.

S203 , forming a gate on a surface of the doped III-V semiconductor layer away from the substrate.

As shown in FIG. 15 , a gate 205 is formed on a surface of the doped III-V semiconductor layer 204 away from the substrate 200 , wherein the doped III-V semiconductor layer 204 and the gate 205 constitute a gate structure.

S204 , forming a first insulating layer on a side of the gate away from the doped III-V semiconductor layer.

As shown in Fig. 15, a first insulating layer 206 is formed on a side of the gate 205 away from the doped III-V semiconductor layer 204. The first insulating layer 206 is used to insulate the gate 205 and the field plate structure.

S205 , forming a field plate structure on a side of the first insulating layer away from the gate structure.

As shown in Figures 15 to 19, a field plate structure is formed on the side of the first insulating layer 206 away from the gate structure, wherein the field plate structure includes a field plate 218 and an etch barrier layer 219, the field plate 218 is located on the side of the first insulating layer 206 away from the gate structure, and the etch barrier layer 219 is located on the side of the field plate 218 away from the first insulating layer 206.

The field plate 218 includes a first sub-field plate 207 and a second sub-field plate 210, and the etch stop layer 219 includes a first sub-etch stop layer 208 and a second sub-etch stop layer 211; the field plate structure also includes a third insulating layer 212, and the third insulating layer 212 is used to insulate and space the first sub-field plate 207 and the second sub-field plate 210. The first contact through hole 220 includes a first sub-contact through hole CT02 and a second sub-contact through hole CT03.

S206 , forming a second insulating layer on a side of the etch stop layer away from the field plate.

As shown in Fig. 20, a second insulating layer 209 is formed on a side of the etch stop layer 219 away from the field plate. As shown in Fig. 21, the second insulating layer 209 may also be planarized.

S207 , using the same mask, synchronously forming a first contact through hole, a second contact through hole, and a third contact through hole that are spaced apart on a side of the second insulating layer away from the field plate structure through an etching process.

As shown in FIG22, the same mask is used to simultaneously form the first contact through hole 220, the second contact through hole CT01 and the third contact through hole CT04 which are spaced apart on the side of the second insulating layer 209 away from the field plate structure through an etching process. The first contact through hole 220, the second contact through hole CT01 and the third contact through hole CT04 constitute a contact through hole structure; the first contact through hole 220 penetrates the second insulating layer 209 and exposes at least part of the etching stop layer 219; the second contact through hole CT01 penetrates the second insulating layer 209 and the first insulating layer 206 and exposes part of the epitaxial layer 201; the third contact through hole CT04 penetrates the second insulating layer 209 and the first insulating layer 206 and exposes part of the epitaxial layer 201.

The first contact via 220 includes a first sub-contact via CT02 and a second sub-contact via CT03 .

S208 , forming a conductive filling layer in the first contact via, the second contact via, and the third contact via.

As shown in FIG. 23 , a conductive filling layer 213 is formed in the first contact via 220 , the second contact via CT01 , and the third contact via CT04 .

In the technical solution provided by the embodiment of the present invention, the first contact hole 220, the second contact hole CT01 and the third contact hole CT04 share the same mask and are formed synchronously through the etching process. Although the etching depths of the first contact hole 220, the second contact hole CT01 and the third contact hole CT04 are different, since the surface of the field plate 218 is protected by the etching barrier layer 219, the etching penetration of the field plate 218 (the field plate material is, for example, titanium nitride) or a large amount of etching loss will not be caused. In addition, the above technical solution also realizes the use of a mask to simultaneously etch the first contact hole 220 that exposes at least part of the etching barrier layer 219, the second contact hole CT01 that exposes part of the epitaxial layer 201, and the third contact hole CT04 that exposes part of the epitaxial layer 201, thereby reducing the number of masks used, and setting an ohmic contact layer, simplifying the film structure of the semiconductor device, and reducing the cost.

Optionally, based on the above technical solution, as shown in FIG. 24 , FIG. 24 is a schematic diagram of the process included in S207, before S207 and after S207 in FIG. 14 , S207 further includes, before forming a contact through-hole structure on a side of the second insulating layer away from the field plate structure:

S207a, performing a planarization process on the second insulating layer to make the surface of the second insulating layer away from the field plate structure into a plane.

As shown in FIG. 21 , the second insulating layer 209 is planarized so that the surface of the second insulating layer 209 away from the field plate structure is flat.

Specifically, the surface of the second insulating layer 209 away from the field plate structure is planar, providing a smooth surface for the preparation of the first contact via 220, the second contact via CT01 and the third contact via CT04, the conductive filling layer 213, and the field plate connecting electrode 221, the source 214 and the drain 217, thereby improving the yield of the device.

and / or,

S207 further includes, after forming a contact through-hole structure on a side of the second insulating layer away from the field plate structure:

S207b, forming a field plate connecting electrode on a surface of the second insulating layer away from the field plate structure.

As shown in FIG13 , a field plate connecting electrode 221 is formed on a surface of the second insulating layer 209 away from the field plate structure, wherein the orthographic projection of the field plate connecting electrode 221 on the substrate 200 covers part or all of the orthographic projection of the first contact through hole 220 on the substrate 200 .

S207c, forming a source electrode on a surface of the second insulating layer away from the field plate structure.

As shown in FIG. 13 , a source electrode 214 is formed on a surface of the second insulating layer 209 away from the field plate structure, wherein the orthographic projection of the source electrode 214 on the substrate 200 covers part or all of the orthographic projection of the second contact hole CT01 on the substrate 200 .

S207d, forming a drain on a surface of the second insulating layer away from the field plate structure.

As shown in FIG. 13 , a drain 217 is formed on a surface of the second insulating layer 209 away from the field plate structure, wherein the orthographic projection of the drain 217 on the substrate 200 covers part or all of the orthographic projection of the third contact hole CT04 on the substrate 200 .

The field plate connection electrode 221 is connected to the field plate 218 through the conductive filling layer 213. Optionally, in the present embodiment, the field plate connection electrode 221 includes a first sub-field plate connection electrode 215 and a second sub-field plate connection electrode 216. The first sub-field plate connection electrode 215 is connected to the first sub-field plate 207 through the conductive filling layer 213. The second sub-field plate connection electrode 216 is connected to the second sub-field plate 210 through the conductive filling layer 213. The source 214 is connected to the barrier layer 203 in the epitaxial layer 201 through the conductive filling layer 213. The drain 217 is connected to the barrier layer 203 in the epitaxial layer 201 through the conductive filling layer 213.

Optionally, based on the above technical solution, as shown in FIG. 25 , FIG. 25 is a schematic diagram of the process included in S201 in FIG. 14 , where S201 forms an epitaxial layer on one side of the substrate and includes:

S201a, forming a channel layer on one side of the substrate.

As shown in FIG. 15 , a channel layer 202 is formed on one side of a substrate 200 .

S201b, forming a barrier layer on a surface of the channel layer away from the substrate, wherein the barrier layer is a semiconductor layer doped with aluminum atoms.

As shown in FIG. 15 , a barrier layer 203 is formed on a surface of the channel layer 202 away from the substrate 200 , wherein the barrier layer 203 is a semiconductor layer doped with aluminum atoms.

There is a large concentration of two-dimensional electron gas near the interface between the channel layer 202 and the barrier layer 203, which is used to improve the device performance. The barrier layer 203 includes a semiconductor layer doped with aluminum atoms, preferably AlGaN.

The barrier layer 203 includes a semiconductor layer doped with aluminum atoms. During the simultaneous etching of the first contact hole 220, the second contact hole CT01 and the third contact hole CT04, the aluminum atoms react with the F-containing etching gas to generate non-volatile substances as an etching barrier layer. Moreover, since the surface of the field plate 218 is protected by the etching barrier layer 219, the simultaneous etching of the first contact hole 220, the second contact hole CT01 and the third contact hole CT04 can be achieved, and over-etching of the field plate 218 and the barrier layer 203 can be avoided.

Among them, the doped III-V semiconductor layer 204 is used to deplete the two-dimensional electron gas on the surface of the barrier layer 203 below it, and the semiconductor device can be turned off at a low voltage. The channel layer 202 includes one or more of GaN, AlGaN and InGaN, preferably GaN. The doped III-V semiconductor layer 204 includes p-type doped AlN or GaN, preferably p-type doped GaN. Optionally, based on the above technical solution, the field plate 218 includes a first sub-field plate 207 and a second sub-field plate 210, and the etch stop layer 219 includes a first sub-etch stop layer 208 and a second sub-etch stop layer 211; the field plate structure also includes a third insulating layer 212.

As shown in FIG. 26 , FIG. 26 is a schematic diagram of the process included in S205 in FIG. 14 , where S205 forms a field plate structure on a side of the first insulating layer away from the gate structure, including:

S205a, forming a first subfield plate on a surface of the first insulating layer away from the gate structure.

As shown in FIG. 15 , a first subfield plate 207 is formed on a surface of the first insulating layer 206 away from the gate structure.

S205b, forming a first sub-etching stop layer on a surface of the first sub-field plate away from the first insulating layer.

As shown in FIG. 16 , a first sub-etching stop layer 208 is formed on a surface of the first sub-field plate away from the first insulating layer 206 .

S205c, forming a third insulating layer on a surface of the first sub-etching stop layer away from the first sub-field plate.

As shown in FIG. 17 , a third insulating layer 212 is formed on a surface of the first sub-etching stop layer 208 away from the first sub-field plate 207 .

S205d, forming a second sub-field plate on a surface of the third insulating layer away from the first sub-etching stop layer.

As shown in FIG. 18 , a second sub-field plate 210 is formed on a surface of the third insulating layer 212 away from the first sub-etching stop layer 208 .

S205e, forming a second sub-etching stop layer on a surface of the second sub-field plate away from the third insulating layer.

As shown in Fig. 18, a second sub-etching stop layer 211 is formed on a surface of the second sub-field plate 210 away from the third insulating layer 212. As shown in Fig. 19, the second sub-field plate 210 and the second sub-etching stop layer 211 are patterned.

Optionally, based on the above technical solution, S207 shares the same mask, and synchronously forms the first contact through hole, the second contact through hole and the third contact through hole which are spaced apart on the side of the second insulating layer away from the field plate structure by an etching process, including:

Sharing the same mask, a first contact through hole, a second contact through hole and a third contact through hole, which are arranged at intervals, are simultaneously formed on a side of the second insulating layer away from the field plate structure by an etching process. The first contact through hole, the second contact through hole and the third contact through hole are included in the first sub-contact through hole and the second sub-contact through hole.

As shown in FIG23, the same mask is used to simultaneously form the first contact through hole 220, the second contact through hole CT01 and the third contact through hole CT04, which are arranged at intervals, on the side of the second insulating layer 209 away from the field plate structure by etching. The first sub-contact through hole CT02 and the second sub-contact through hole CT03 are arranged at intervals, the first sub-contact through hole CT02 penetrates the second insulating layer 209 and the third insulating layer 212, and exposes at least a portion of the first sub-etching stop layer 208; the second sub-contact through hole CT03 penetrates the second insulating layer 209, and exposes at least a portion of the second sub-etching stop layer 211.

Specifically, the first sub-contact hole CT02, the second sub-contact hole CT03, the second contact hole CT01 and the third contact hole CT04 share the same mask and are formed synchronously through an etching process. Although the etching depths of the first sub-contact hole CT02, the second sub-contact hole CT03, the second contact hole CT01 and the third contact hole CT04 are different, since the surfaces of the first sub-field plate 207 and the second sub-field plate 210 are protected by the etching barrier layer 219, the first sub-field plate 207 and the second sub-field plate 210 (the field plate material is, for example, titanium nitride) will not be etched through or a large amount of etching loss will not be caused. The barrier layer 203 includes a semiconductor layer doped with aluminum atoms. During the process of simultaneously etching the first sub-contact hole CT02, the second sub-contact hole CT03, the second contact hole CT01 and the third contact hole CT04, the aluminum atoms will react with the F-containing etching gas to generate non-volatile substances as an etching barrier layer, thereby achieving simultaneous etching of the first contact hole 220, the second contact hole CT01 and the third contact hole CT04, and avoiding over-etching of the field plate 218 and the barrier layer 203.

Optionally, based on the above technical solution, S205 forming a field plate structure on a side of the first insulating layer 206 away from the gate structure includes:

As shown in FIG. 19 , a field plate structure including a field plate 218 and an etch stop layer 219 is formed on a side of the first insulating layer 206 away from the gate structure, wherein the etch stop layer 219 includes at least one of aluminum nitride, aluminum oxide, and aluminum gallium nitride.

Specifically, the etching barrier layer 219 includes at least one of aluminum nitride, aluminum oxide and aluminum gallium nitride. During the simultaneous etching of the first contact hole 220, the second contact hole CT01 and the third contact hole CT04, the aluminum atoms react with the F-containing etching gas to generate non-volatile substances as an etching barrier layer. Since the barrier layer 203 includes a semiconductor layer doped with aluminum atoms, the simultaneous etching of the first contact hole 220, the second contact hole CT01 and the third contact hole CT04 can be achieved, and over-etching of the field plate 218 and the barrier layer 203 can be avoided.

It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (6)

1. A semiconductor device, comprising: substrate; an epitaxial layer, the epitaxial layer being located on one side of the substrate; A gate structure, the gate structure comprising a doped III-V semiconductor layer and a gate, the doped III-V semiconductor layer is located on a side of the epitaxial layer away from the substrate, and the gate is located on a surface of the doped III-V semiconductor layer away from the epitaxial layer; A first insulating layer, wherein the first insulating layer is located on a side of the gate away from the doped III-V semiconductor layer; A field plate structure, the field plate structure comprising a field plate and an etch stop layer, the field plate being located on a side of the first insulating layer away from the gate structure, and the etch stop layer being located on a side of the field plate away from the first insulating layer; A second insulating layer, the second insulating layer is located on a side of the etching stop layer away from the field plate; a surface of the second insulating layer away from the field plate structure is a plane; A contact through-hole structure, the contact through-hole structure is located on a side of the second insulating layer away from the field plate structure, the contact through-hole structure comprises a first contact through-hole, a second contact through-hole and a third contact through-hole arranged at intervals; the first contact through-hole penetrates the second insulating layer and exposes at least a portion of the etching barrier layer; the second contact through-hole penetrates the second insulating layer and the first insulating layer and exposes a portion of the epitaxial layer; the third contact through-hole penetrates the second insulating layer and the first insulating layer and exposes a portion of the epitaxial layer; the first contact through-hole, the second contact through-hole and the third contact through-hole share the same mask and are formed synchronously by an etching process; A conductive filling layer, wherein the conductive filling layer is located in the first contact through hole, the second contact through hole and the third contact through hole; The epitaxial layer includes a channel layer and a barrier layer; the channel layer is located on one side of the substrate; the barrier layer is located on a surface of the channel layer away from the substrate; the barrier layer includes a semiconductor layer doped with aluminum atoms; The etch stop layer includes at least one of aluminum nitride, aluminum oxide, and gallium aluminum nitride. 2. The semiconductor device according to claim 1, wherein: The semiconductor device also includes a field plate connecting electrode, a source electrode and a drain electrode; The field plate connecting electrode is located on a surface of the second insulating layer away from the field plate structure, and the orthographic projection of the field plate connecting electrode on the substrate covers part or all of the orthographic projection of the first contact through hole on the substrate; The source electrode is located on a surface of the second insulating layer away from the field plate structure, and the orthographic projection of the source electrode on the substrate covers part or all of the orthographic projection of the second contact through hole on the substrate; The drain is located on a surface of the second insulating layer away from the field plate structure, and an orthographic projection of the drain on the substrate covers part or all of an orthographic projection of the third contact through hole on the substrate. 3. The semiconductor device according to claim 1, characterized in that the field plate comprises a first sub-field plate and a second sub-field plate, the etch stop layer comprises a first sub-etch stop layer and a second sub-etch stop layer; and the field plate structure further comprises a third insulating layer; The first sub-field plate is located on a surface of the first insulating layer away from the gate structure; The first sub-etching stop layer is located on a surface of the first sub-field plate away from the first insulating layer; The third insulating layer is located on a surface of the first sub-etching stop layer away from the first sub-field plate; The second sub-field plate is located on a surface of the third insulating layer away from the first sub-etching stop layer; The second sub-etching stop layer is located on a surface of the second sub-field plate away from the third insulating layer; The first contact via comprises a first sub-contact via and a second sub-contact via which are spaced apart from each other, wherein the first sub-contact via penetrates the second insulating layer and the third insulating layer and exposes at least a portion of the first sub-etching barrier layer; and the second sub-contact via penetrates the second insulating layer and exposes at least a portion of the second sub-etching barrier layer. 4. A method for preparing a semiconductor device, comprising: providing a substrate; forming an epitaxial layer on one side of the substrate; forming a doped III-V semiconductor layer on a side of the epitaxial layer away from the substrate; forming a gate on a surface of the doped III-V semiconductor layer away from the substrate, wherein the doped III-V semiconductor layer and the gate constitute a gate structure; forming a first insulating layer on a side of the gate away from the doped III-V semiconductor layer; forming a field plate structure on a side of the first insulating layer away from the gate structure, wherein the field plate structure comprises a field plate and an etch stop layer, the field plate is located on a side of the first insulating layer away from the gate structure, and the etch stop layer is located on a side of the field plate away from the first insulating layer; forming a second insulating layer on a side of the etch stop layer away from the field plate; performing a planarization process on the second insulating layer so that a surface of the second insulating layer away from the field plate structure is a plane; Sharing the same mask, a first contact hole, a second contact hole and a third contact hole that are spaced apart are simultaneously formed on a side of the second insulating layer away from the field plate structure by an etching process, wherein the first contact hole, the second contact hole and the third contact hole constitute a contact hole structure; the first contact hole penetrates the second insulating layer and exposes at least a portion of the etching barrier layer; the second contact hole penetrates the second insulating layer and the first insulating layer and exposes a portion of the epitaxial layer; the third contact hole penetrates the second insulating layer and the first insulating layer and exposes a portion of the epitaxial layer; forming a conductive filling layer in the first contact via, the second contact via, and the third contact via; Wherein, forming an epitaxial layer on one side of the substrate comprises: forming a channel layer on one side of the substrate; forming a barrier layer on a surface of the channel layer away from the substrate, wherein the barrier layer is a semiconductor layer doped with aluminum atoms; Among them, forming a field plate structure on a side of the first insulating layer away from the gate structure includes: forming a field plate structure including a field plate and an etch stop layer on a side of the first insulating layer away from the gate structure, wherein the etch stop layer includes at least one of aluminum nitride, aluminum oxide and aluminum gallium nitride. 5. The method for preparing a semiconductor device according to claim 4, characterized in that: After forming a contact through-hole structure on a side of the second insulating layer away from the field plate structure, the method further comprises: forming a field plate connecting electrode on a surface of the second insulating layer away from the field plate structure, wherein an orthographic projection of the field plate connecting electrode on the substrate covers part or all of an orthographic projection of the first contact through hole on the substrate; forming a source electrode on a surface of the second insulating layer away from the field plate structure, wherein an orthographic projection of the source electrode on the substrate covers part or all of an orthographic projection of the second contact through hole on the substrate; A drain is formed on a surface of the second insulating layer away from the field plate structure, wherein an orthographic projection of the drain on the substrate covers a part or all of an orthographic projection of the third contact hole on the substrate. 6. The method for preparing a semiconductor device according to claim 4, characterized in that the field plate comprises a first sub-field plate and a second sub-field plate, the etch stop layer comprises a first sub-etch stop layer and a second sub-etch stop layer; the field plate structure further comprises a third insulating layer; Forming a field plate structure on a side of the first insulating layer away from the gate structure comprises: forming a first subfield plate on a surface of the first insulating layer away from the gate structure; forming a first sub-etching stop layer on a surface of the first sub-field plate away from the first insulating layer; forming a third insulating layer on a surface of the first sub-etching stop layer away from the first sub-field plate; forming a second sub-field plate on a surface of the third insulating layer away from the first sub-etching stop layer; forming a second sub-etching stop layer on a surface of the second sub-field plate away from the third insulating layer; Sharing the same mask, synchronously forming a first contact through hole, a second contact through hole and a third contact through hole arranged at intervals on a side of the second insulating layer away from the field plate structure by an etching process comprises: Sharing the same mask, a first contact hole, a second contact hole and a third contact hole, which are spaced apart and include a first sub-contact hole and a second sub-contact hole, are simultaneously formed on a side of the second insulating layer away from the field plate structure through an etching process, wherein the first sub-contact hole and the second sub-contact hole are spaced apart, the first sub-contact hole penetrates the second insulating layer and the third insulating layer and exposes at least a portion of the first sub-etching barrier layer; the second sub-contact hole penetrates the second insulating layer and exposes at least a portion of the second sub-etching barrier layer.