CN117935874A - Memory refresh parameter determination, memory refresh method, device, medium and equipment - Google Patents
Memory refresh parameter determination, memory refresh method, device, medium and equipment Download PDFInfo
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- G11C11/40607—Refresh operations in memory devices with an internal cache or data buffer
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Abstract
The disclosure provides a memory refresh parameter determination method, a memory refresh device, a medium and equipment, and relates to the technical field of semiconductors. The memory refresh parameter determining method is used for determining a time ratio between a data holding time length of a memory unit and a reference data holding time length of a reference memory unit for each memory unit in a semiconductor to be tested; the reference memory cell refers to a memory cell with the shortest data retention time in the semiconductor to be tested; determining a target refresh interval duration of each memory unit according to the ratio of the reference refresh interval duration of the reference memory unit to the time for each memory unit; and determining a target refresh amount of the memory unit in the target refresh interval duration according to the ratio of the reference refresh amount of the reference memory unit to the memory data in the reference refresh interval duration and the time for each memory unit. The technical problem of larger power consumption of the existing DRAM chip in the prior art is solved, and the technical effect of reducing the power consumption of the DRAM chip is achieved.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a memory refresh parameter determination method, a memory refresh device, a medium and equipment.
Background
The basic structure of a DRAM (Dynamic Random Access Memory ) chip generally includes 1 transistor and 1 capacitor, the capacitor is prone to leakage during operation, and the data retention time is inversely proportional to the memory refresh interval time, so to ensure the integrity of data, the capacitor needs to be periodically charged, and this charging process is called memory refresh.
Due to the influence of factors such as physical layout and production process, the data storage time of different memory units is different, and the maximum time difference can reach more than 50%. For this situation, at present, most of the memory cells in the DRAM chip are refreshed based on the shortest data storage duration, which results in that the memory cells with longer data storage duration also need to be refreshed based on the shortest refresh interval duration. That is, the refresh times of the memory cells with longer data retention time in a unit time are more, thereby greatly increasing the power consumption of the DRAM chip.
Therefore, the current DRAM chip consumes more power.
Disclosure of Invention
The disclosure provides a memory refresh parameter determination method, a memory refresh device, a medium and a device, so as to reduce the power consumption of a DRAM chip.
In a first aspect, an embodiment of the present disclosure provides a method for determining a memory refresh parameter, including:
For each memory cell in the semiconductor to be tested, determining a time ratio between a data retention time of the memory cell and a reference data retention time of a reference memory cell; the reference memory cell refers to a memory cell with the shortest data retention time in the semiconductor to be tested;
determining a target refresh interval duration of each memory unit according to the ratio of the reference refresh interval duration of the reference memory unit to the time for each memory unit;
And determining a target refresh amount of the memory unit in the target refresh interval duration according to the ratio of the reference refresh amount of the reference memory unit to the memory data in the reference refresh interval duration and the time for each memory unit.
In an alternative embodiment of the present disclosure, before determining, for each memory cell in the semiconductor to be tested, a time ratio between a data retention period of the memory cell and a reference data retention period of a reference memory cell, the memory refresh parameter determining method further includes:
acquiring the data retention time length of each memory unit in the semiconductor to be tested in a data retention test;
and determining the memory cell corresponding to the minimum value in each data holding time period as a reference memory cell.
In an alternative embodiment of the present disclosure, acquiring a data retention time period in a data retention test of each memory cell in a semiconductor under test includes:
Performing mass production test on the semiconductor to be tested to obtain a test result of the semiconductor to be tested;
and extracting the data retention time length of each memory unit from the test result.
In an alternative embodiment of the present disclosure, after determining, for each memory cell in the semiconductor to be tested, a time ratio between a data retention period of the memory cell and a reference data retention period of a reference memory cell, the memory refresh parameter determining method further includes:
storing the corresponding time ratio of each memory unit in a preset memory module in the semiconductor to be tested.
In an optional embodiment of the disclosure, the memory refresh parameter determining method further includes:
and storing the target refresh rate corresponding to each memory cell in a preset memory module in the semiconductor to be tested.
In an alternative embodiment of the present disclosure, the preset memory module is a readable register in the semiconductor under test.
In an alternative embodiment of the present disclosure, for each memory cell, determining a target refresh interval duration of the memory cell according to a reference refresh interval duration to time ratio of the reference memory cell includes:
and calculating the ratio of the reference refresh interval duration of the reference memory unit to the corresponding time ratio of the memory unit for each memory unit to obtain the target refresh interval duration of the memory unit.
In an alternative embodiment of the present disclosure, for each memory cell, determining a target refresh amount of the memory cell in a target refresh interval duration according to a ratio of a reference refresh amount of the reference memory cell to time of memory data in the reference refresh interval duration includes:
determining a reference refresh amount of the memory data in a reference refresh interval duration of the reference memory unit;
And calculating the ratio between the reference refresh rate and the time ratio corresponding to the memory unit for each memory unit to obtain the target refresh rate of the memory unit in the target refresh interval duration.
In an alternative embodiment of the present disclosure, the reference refresh amount is the number of refresh units for each of the data units in the memory unit during the reference refresh interval.
In an alternative embodiment of the present disclosure, the semiconductor under test is a dynamic random access memory.
In a second aspect, an embodiment of the present disclosure provides a memory refresh method, including:
acquiring a target refresh interval duration of each memory cell in a semiconductor to be tested and a target refresh amount in the target refresh interval duration; the target refresh interval duration and the target refresh amount are determined according to the memory refresh parameter determining method according to any one of the above;
and controlling each corresponding memory unit in the semiconductor to be tested to carry out memory refreshing based on the target refresh interval duration and the target refresh amount.
In a third aspect, an embodiment of the present disclosure provides a memory refresh parameter determining apparatus, including:
A first determining module, configured to determine, for each memory cell in the semiconductor to be tested, a time ratio between a data retention period of the memory cell and a reference data retention period of a reference memory cell; the reference memory cell refers to a memory cell with the shortest data retention time in the semiconductor to be tested;
The second determining module is used for determining the target refresh interval duration of the memory unit according to the ratio of the reference refresh interval duration of the reference memory unit to the time for each memory unit;
And the third determining module is used for determining the target refresh amount of the memory unit in the target refresh interval duration according to the ratio of the reference refresh amount of the reference memory unit to the memory data in the reference refresh interval duration and the time for each memory unit.
In a fourth aspect, an embodiment of the present disclosure provides a memory refresh apparatus, including:
The acquisition module is used for acquiring the target refresh interval duration of each memory unit in the semiconductor to be tested and the target refresh amount in the target refresh interval duration; the target refresh interval duration and the target refresh amount are determined according to the memory refresh parameter determining method according to any one of the above;
and the control module is used for controlling each memory unit corresponding to the semiconductor to be tested to carry out memory refreshing based on the target refresh interval duration and the target refresh amount.
In a fifth aspect, one embodiment of the present disclosure provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method as above.
In a sixth aspect, an embodiment of the present disclosure provides an electronic device, including: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the method as above via execution of the executable instructions.
The technical scheme of the present disclosure has the following beneficial effects:
According to the memory refresh parameter determining method, the time ratio between the data holding time length of the memory unit and the reference data holding time length of the reference memory unit is determined for each memory unit in the semiconductor to be tested, and according to the first aspect, the target refresh interval time length of each memory unit is determined according to the reference refresh interval time length and the time ratio of the reference memory unit, so that the situation that the refresh interval time length with the longest time in each memory unit is uniformly used in a traditional mode is avoided, the integral refresh interval time length is shorter, and the memory refresh efficiency is higher; each memory unit is provided with a target refresh interval duration which is adapted to the corresponding data retention duration so as to ensure normal data refresh;
in a second aspect, according to the embodiment of the disclosure, the target refresh rate of the memory unit in the target refresh interval duration is determined according to the ratio of the reference refresh rate of the reference memory unit to the memory data in the reference refresh interval duration, so that the unified use of the maximum refresh rate in the traditional mode is avoided, the refresh rate is reduced, and the power consumption of memory refresh is further reduced.
Therefore, the embodiment of the disclosure greatly reduces the power consumption of the memory refresh while improving the efficiency of the memory refresh, thereby solving the technical problem that the power consumption of the existing DRAM chip is larger and achieving the technical effect of reducing the power consumption of the DRAM chip.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely some embodiments of the present disclosure and that other drawings may be derived from these drawings without undue effort.
Fig. 1 (a) shows a schematic structural diagram of a DRAM chip in the present exemplary embodiment;
fig. 1 (b) is a schematic diagram showing a structure of a memory cell in a DRAM chip according to the present exemplary embodiment;
fig. 2 is a flowchart showing a memory refresh parameter determination method in the present exemplary embodiment;
fig. 3 is a diagram showing a correspondence relationship between a data retention period and a time ratio in a memory refresh parameter determination method according to the present exemplary embodiment;
fig. 4 is a flowchart showing a memory refresh parameter determination method in the present exemplary embodiment;
fig. 5 is a flowchart showing a memory refresh parameter determination method in the present exemplary embodiment;
Fig. 6 is a flowchart showing a memory refresh parameter determination method in the present exemplary embodiment;
fig. 7 is a flowchart showing a memory refresh method in the present exemplary embodiment;
fig. 8 is a schematic diagram showing a configuration of a memory refresh parameter determination device according to the present exemplary embodiment;
Fig. 9 is a schematic diagram showing a structure of a memory refresh device in the present exemplary embodiment;
Fig. 10 shows a schematic structural diagram of an electronic device in the present exemplary embodiment.
Detailed Description
Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present disclosure. However, those skilled in the art will recognize that the aspects of the present disclosure may be practiced with one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.
The flow diagrams depicted in the figures are exemplary only and not necessarily all steps are included. For example, some steps may be decomposed, and some steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
In the related art, the basic structure of a DRAM (Dynamic Random Access Memory ) chip generally includes 1 transistor and 1 capacitor, and the capacitor is prone to leakage during operation, so that the capacitor needs to be periodically charged to ensure the integrity of data, and this charging process is called memory refresh. Referring to fig. 1 (a) and 1 (b), the memory array of the DRAM chip 10 is currently formed by a plurality of banks Group/banks (memory cell combinations/memory cells), for example, each memory cell 110 in fig. 1 (a) is placed in a DRAM chip according to a certain order, each memory cell 110 includes a plurality of data cells, for example, 7×7 data cells in fig. 1 (b) (here, only an example is not enough to limit the number and arrangement of the data cells), and the CPU (central processing unit, memory processor) needs to refresh each memory cell 110 every tRFCpb (refresh interval duration), and each memory cell is the same refresh interval duration to perform the memory refresh. Due to the influence of factors such as physical layout and production process, the refresh interval duration of different memory units is not only the same, but also the maximum time difference of more than 50 percent can be achieved. For this situation, at present, most of the memory cells in the DRAM chip are refreshed based on the shortest refresh interval duration, which results in that the memory cells with longer refresh interval duration need to be refreshed based on the shortest refresh interval duration. That is, the refresh times of the memory cells with longer refresh interval duration in unit time are more, thereby greatly increasing the power consumption of the DRAM chip. Therefore, the current DRAM chip consumes more power.
In view of the foregoing, embodiments of the present disclosure provide a memory refresh parameter determining method for reducing power consumption of a DRAM chip. The following briefly describes an application environment of a memory refresh parameter determining method provided by an embodiment of the present disclosure:
The memory refresh parameter determining method provided by the embodiment of the disclosure is applied to a control device, which may be a CPU inside a DRAM chip, or may be independent of other control devices, or control chips except the DRAM chip, and the embodiment of the disclosure is not specifically limited and may be set arbitrarily according to practical situations.
The method for determining the memory refresh parameters is applied to the control device to determine the memory refresh parameters of the memory cells in the semiconductor to be tested. The semiconductor to be tested may be any semiconductor that needs to perform memory refresh, such as a DRAM chip, and embodiments of the present disclosure are not limited in detail. Referring to fig. 2, the memory refresh parameter determining method provided in the embodiment of the present disclosure includes the following steps 201 to 203:
Step 201, determining, for each memory cell in the semiconductor to be tested, a time ratio between a data holding duration of the memory cell and a reference data holding duration of a reference memory cell.
The data Retention period (Retention time) refers to a period of time during which the capacitor in the memory cell can be maintained without leakage, and one memory cell corresponds to one data Retention period, for example, 10 seconds, 20 seconds, 30 seconds, etc. The reference memory cell refers to a memory cell with the shortest data retention time in the semiconductor to be tested. For example, referring to fig. 3, fig. 3 is a graph of data retention time lengths of memory cells in a batch of DDR 4SDRAM (Double Data Rate Fourth Synchronous Dynamic Random Access Memory, fourth generation DDR SDRAM), where the abscissa is the reference number of different memory cells from BANK0 to BANK7, and the ordinate is the data retention time length of each memory cell, and as can be seen in fig. 3, the data retention time length of BANK3 is the shortest, 30 seconds, that is, the BANK3 is determined as a reference memory cell, and the corresponding reference data retention time length is 30 seconds. Then, respectively calculating the ratio of the data retention time length to 30 seconds of each memory unit to respectively obtain the corresponding time ratio of each memory unit, as shown in the following table (1):
Watch (1)
Step 202, determining, for each memory cell, a target refresh interval duration of the memory cell according to a ratio of a reference refresh interval duration of the reference memory cell to time.
The refresh interval duration refers to the time between two memory refreshes of the memory unit, and the reference refresh interval duration corresponds to the time between two memory refreshes of the reference memory unit. The target refresh interval duration of each memory cell may be obtained by calculating the ratio, the product, or the weighted product of the reference refresh interval duration and each time ratio, respectively.
Continuing with the above example, for example, the reference refresh interval duration of the reference memory cell BANK3 is 90 ns, and the target refresh interval durations respectively corresponding to BANKs 0 to BANK7 are as follows in table (2):
watch (2)
As can be seen from the above table (2), the target refresh interval duration of the memory cells is inversely related to the data retention duration, the shorter the data retention duration is, the longer the target refresh interval duration is, the shorter the data retention duration is, and the target refresh interval durations of different memory cells are different, so that the refresh interval duration of each memory cell is shorter than the interval time of uniformly using the longest refresh interval duration (for example, 90 nanoseconds of BANK3 in the above example) in the conventional manner, and the refresh efficiency is improved.
Step 203, for each memory cell, determining a target refresh rate of the memory cell in the target refresh interval duration according to a ratio of a reference refresh rate of the reference memory cell to the memory data in the reference refresh interval duration.
The refresh rate in the embodiments of the present disclosure refers to the amount of refreshing memory data in one refresh interval period of a memory cell, and may be represented by a specific data size, for example, 3M, 5M, or the like, or may be represented by a data cell, for example, 1 row, 2 rows, or the like, which is not specifically limited in the embodiments of the present disclosure. Correspondingly, the reference refresh amount is the amount of refreshing the memory data in the reference memory unit within a refresh interval duration. The target refresh rate of each memory cell may be obtained by calculating the ratio, product or weighted product of the reference refresh rate and each time ratio, respectively.
Continuing with the above example, for example, the reference refresh rate of the reference memory cell BANK3 is 4.0 rows, and the target refresh rates respectively corresponding to BANKs 0 to BANK7 are as follows in table (3):
Watch (3)
As can be seen from the above table (3), the target refresh rate of the memory unit is inversely related to the data retention period, the shorter the data retention period is, the larger the target refresh rate is, conversely, the longer the data retention period is, the smaller the target refresh rate is, the target refresh rates of different memory units are different, the refresh interval period of each memory unit is equal to the maximum refresh rate (for example, refresh rate 4 of BANK3 in the above example) in a unified manner, the refresh rate is reduced, and the power consumption of memory refresh is further reduced.
According to the memory refresh parameter determining method provided by the embodiment of the disclosure, for each memory unit in a semiconductor to be tested, the time ratio between the data holding time length of the memory unit and the reference data holding time length of the reference memory unit is determined, and according to the first aspect, the target refresh time length of each memory unit is determined according to the reference refresh time length and the time ratio of the reference memory unit, so that the problem that the refresh time length with the longest time in each memory unit is uniformly used in a traditional mode is avoided, the overall refresh time length is shorter, and the memory refresh efficiency is higher; each memory unit is provided with a target refresh interval duration which is adapted to the corresponding data retention duration so as to ensure normal data refresh;
in a second aspect, according to the embodiment of the present disclosure, the target refresh rate of the memory unit in the target refresh interval duration is determined according to the ratio of the reference refresh rate of the reference memory unit to the memory data in the reference refresh interval duration, which avoids unified use of the maximum refresh rate (e.g., refresh rate 4 of BANK3 in the above example) in the conventional manner, and reduces the refresh rate, thereby further reducing the power consumption of memory refresh.
Therefore, the embodiment of the disclosure greatly reduces the power consumption of the memory refresh while improving the efficiency of the memory refresh, thereby solving the technical problem that the power consumption of the existing DRAM chip is larger and achieving the technical effect of reducing the power consumption of the DRAM chip.
Referring to fig. 4, in an alternative embodiment of the present disclosure, before determining, for each memory cell in the semiconductor to be tested, the time ratio between the data retention period of the memory cell and the reference data retention period of the reference memory cell in step 201, the memory refresh parameter determining method further includes the following steps 401 to 402:
Step 401, acquiring a data retention time length of each memory unit in the semiconductor to be tested in a data retention test.
The data retention test refers to a test of data retention time length of each memory unit in a semiconductor to be tested, for example, by continuously testing data written in the memory unit, taking a data writing time or a test starting time as a starting time, taking a first group of data losing time or other set number of data losing times as a termination time, and the time length between the starting time and the termination time is the data retention time length and is used for representing the data retention capability of the memory unit.
Step 402, determining the memory cell corresponding to the minimum value in each data holding duration as the reference memory cell.
Continuing with the example above, as can be seen in fig. 3, for example, the data retention period of BANK3 is the shortest, 30 seconds, i.e., BANK3 is determined as the reference memory cell, and the corresponding reference data retention period is 30 seconds.
The data retention time length in the embodiment of the disclosure is obtained based on the data retention test, rather than being obtained according to empirical fitting, the obtained reference memory unit is based on actual production, and the target refresh interval time length and the target refresh amount of each memory unit obtained based on the reference memory unit are determined to be more reliable.
Referring to fig. 5, in an alternative embodiment of the present disclosure, the step 401 of obtaining the data retention time of each memory cell in the semiconductor to be tested in the data retention test includes the following steps 501-502:
And step 501, performing mass production test on the semiconductor to be tested to obtain a test result of the semiconductor to be tested.
Mass production testing (Automatic Test Equipment, ATE for short) of chips to detect the integrity of integrated circuit functions includes, but is not limited to: the method comprises the steps of data holding time of a memory unit, whether an open circuit or a short circuit exists in a chip pin, logic functions, direct current and voltage parameters of a device, quality and signal time sequence parameters of an alternating current output signal, functions and performances of embedded flash and the like.
Step 502, extracting the data holding duration of each memory unit from the test result.
According to the embodiment of the disclosure, the data retention test does not need to be independently carried out, the data retention test can be newly added while the mass production test is carried out, the data retention test is synchronously carried out with other projects, the required data retention time is extracted from the test result after the test is finished, and the test time and the test cost are saved.
In an alternative embodiment of the present disclosure, after determining, in the step 201, a time ratio between a data retention period of a memory cell and a reference data retention period of a reference memory cell for each memory cell in the semiconductor to be tested, the memory refresh parameter determining method further includes the following step a:
and step A, storing the time ratio corresponding to each memory unit in a preset memory module in the semiconductor to be tested.
The preset memory module may be a memory module in a semiconductor to be tested, and may be specifically selected or set according to actual situations, which is not limited herein. And storing the corresponding time ratio of each memory unit in the preset storage module so as to facilitate the reading of the control equipment and further improve the convenience and efficiency of determining the memory refresh parameters.
In an optional embodiment of the disclosure, the memory refresh parameter determining method further includes the following step B:
and B, storing the target refresh rate corresponding to each memory cell in a preset memory module in the semiconductor to be tested.
In the same way as in the step a, the preset memory module may be a memory module in the semiconductor to be tested, and may be specifically selected or set according to the actual situation, which is not limited in any way. And storing the target refresh rate corresponding to each memory unit in the preset memory module so as to facilitate the reading of the control equipment and further improve the convenience and efficiency of determining the memory refresh parameters.
In an alternative embodiment of the present disclosure, the reference refresh amount is a number of refresh units for each data unit in the memory units during a reference refresh interval. The data unit refers to a storage form of memory data in a memory unit, for example, 1 line, 2 lines, 3 lines, etc. may be one data unit, or 10KB, 20KB, 30KB, etc. may be one data unit, or 10 characters, 20 characters, 30 characters, etc. may be one data unit. The refresh amount is measured by the data unit, so that the calculation amount is smaller compared with the calculation amount for calculating the memory data in real time, the calculation resource can be saved, and the efficiency of determining the memory refresh parameters is further improved.
In an alternative embodiment of the present disclosure, the semiconductor under test is a dynamic random access memory. Namely, the semiconductor to be tested is a DRAM chip, and the target refresh interval duration of each memory unit and the target refresh amount in the target refresh interval duration are determined when the memory refresh is performed in the DRAM chip based on the memory refresh parameter determining method provided by the embodiment of the present disclosure, so that the efficiency of the memory refresh of the DRAM chip can be greatly improved, and the power consumption of the memory refresh can be reduced.
In an alternative embodiment of the present disclosure, the predetermined memory module is a readable register in the semiconductor to be tested.
The readable register refers to a mode register (e.g., MR register) of the readability of the semiconductor to be tested, for example, in the DRAM chip, and the mode register of the readability can be read and accessed by a control device, for example, a CPU of the DRAM chip, so that the time ratio of each stored memory unit, the target refresh interval duration, the target refresh amount, etc. can be conveniently obtained, and the efficiency and convenience of the memory refresh and the overall performance of the DRAM chip are improved.
In an optional embodiment of the present disclosure, the step 202 of determining, for each memory cell, a target refresh interval duration of the memory cell according to a ratio of a reference refresh interval duration of the reference memory cell to a time, includes the following step C:
And C, calculating the ratio of the reference refresh interval duration of the reference memory unit to the corresponding time ratio of the memory unit for each memory unit to obtain the target refresh interval duration of the memory unit.
That is, the present embodiment can calculate the target refresh interval duration of the memory cell by the following formula (1):
tRFi＝tRF0/(RTi/RT0) (1)
In formula (1), tRF i represents the target refresh interval duration of the i-th memory cell, tRF 0 represents the reference refresh interval duration of the reference memory cell, RT i represents the data retention duration of the i-th memory cell, RT 0 represents the reference data retention duration of the reference memory cell, and (RT i/RT0) represents the time ratio of the i-th memory cell.
The target refresh interval duration of the memory unit is obtained directly by calculating the ratio between the reference refresh interval duration of the reference memory unit and the time ratio corresponding to the memory unit, the calculation mode is simple, the efficiency is higher, and the efficiency of determining the memory refresh parameters in the embodiment of the disclosure can be further improved.
Referring to fig. 6, in an alternative embodiment of the present disclosure, the step 203 of determining, for each memory cell, a target refresh amount of the memory cell in the target refresh interval duration according to a ratio of a reference refresh amount of the reference memory cell to a time of the memory data in the reference refresh interval duration includes the following steps 601-602:
step 601, determining a reference refresh amount of the memory data in the reference refresh interval duration of the reference memory cell.
For example, the reference refresh amount of the reference memory cell is 4 in the reference refresh interval duration.
Step 602, calculating, for each memory cell, a ratio between the reference refresh rate and a time ratio corresponding to the memory cell, to obtain a target refresh rate of the memory cell within a target refresh interval duration.
That is, the present embodiment can calculate the target refresh rate of the memory cell by the following formula (2):
Ri＝R0/(RTi/RT0) (2)
In the formula (2), R i represents the target refresh rate of the i-th memory cell, R 0 represents the reference refresh rate of the reference memory cell, RT i represents the data holding period of the i-th memory cell, RT 0 represents the reference data holding period of the reference memory cell, and (RT i/RT0) represents the time ratio of the i-th memory cell.
According to the method, the target refresh rate of the memory unit in the target refresh interval duration is obtained directly through calculating the ratio between the reference refresh rate and the time ratio corresponding to the memory unit, the calculation mode is simple, the efficiency is higher, and the efficiency of determining the memory refresh parameters in the embodiment of the disclosure can be further improved.
Referring to fig. 7, an embodiment of the present disclosure provides a memory refresh method, which includes steps 701 to 702 as follows:
Step 701, obtaining a target refresh interval duration of each memory cell in the semiconductor to be tested, and a target refresh amount in the target refresh interval duration.
The target refresh interval duration and the target refresh amount are determined according to the memory refresh parameter determining method according to any one of the above;
The beneficial effects of the memory refresh parameter determination method are described in detail in the above embodiments, and are not described herein.
Step 702, controlling each corresponding memory unit in the semiconductor to be tested to perform memory refresh based on the target refresh interval duration and the target refresh amount.
According to the embodiment of the disclosure, the target refresh interval duration of each memory unit in the semiconductor to be tested and the target refresh amount in the target refresh interval duration are determined firstly based on the memory refresh parameter determining method, and then the memory refresh of each corresponding memory unit in the semiconductor to be tested is controlled based on the target refresh interval duration and the target refresh amount; each memory unit is provided with a target refresh interval duration which is adapted to the corresponding data retention duration so as to ensure normal data refresh; in the second aspect, the unified use of the maximum refresh rate (e.g., refresh rate 4 of BANK3 in the above example) in the conventional manner can be avoided, and the refresh rate is reduced, thereby further reducing the power consumption of memory refresh. Therefore, the embodiment of the disclosure greatly reduces the power consumption of the memory refresh while improving the efficiency of the memory refresh, thereby solving the technical problem that the power consumption of the existing DRAM chip is larger and achieving the technical effect of reducing the power consumption of the DRAM chip.
Referring to fig. 8, in order to implement the above-mentioned memory refresh parameter determination method, in one embodiment of the present disclosure, a memory refresh parameter determination device 800 is provided. Fig. 8 shows a schematic architecture diagram of a memory refresh parameter determination device 800, the memory refresh parameter determination device 800 comprising: a first determination module 810, a second determination module 820, and a third determination module 830, wherein:
The first determining module 810 is configured to determine, for each memory cell in the semiconductor to be tested, a time ratio between a data retention period of the memory cell and a reference data retention period of a reference memory cell; the reference memory cell refers to a memory cell with the shortest data retention time in the semiconductor to be tested;
The second determining module 820 is configured to determine, for each memory cell, a target refresh interval duration of the memory cell according to a ratio of a reference refresh interval duration of the reference memory cell to a time;
The third determining module 830 is configured to determine, for each memory cell, a target refresh amount of the memory cell in the target refresh interval duration according to a ratio of a reference refresh amount of the reference memory cell to time of the memory data in the reference refresh interval duration.
In an alternative embodiment, the first determining module 810 is further configured to obtain a data retention time period of each memory cell in the semiconductor under test during the data retention test; and determining the memory cell corresponding to the minimum value in each data holding time period as a reference memory cell.
In an alternative embodiment, the first determining module 810 is specifically configured to perform a mass production test on the semiconductor to be tested to obtain a test result of the semiconductor to be tested; and extracting the data retention time length of each memory unit from the test result.
In an alternative embodiment, the first determining module 810 is further configured to store the time ratio corresponding to each memory cell in a preset memory module in the semiconductor under test.
In an alternative embodiment, the third determining module 830 is further configured to store the target refresh amount corresponding to each memory cell in a preset memory module in the semiconductor to be tested.
In an alternative embodiment, the predetermined memory module is a readable register in the semiconductor under test.
In an alternative embodiment, the second determining module 820 is specifically configured to calculate, for each memory cell, a ratio between a reference refresh interval duration of the reference memory cell and a time ratio corresponding to the memory cell, to obtain a target refresh interval duration of the memory cell.
In an alternative embodiment, the third determining module 830 is specifically configured to determine a reference refresh amount of the memory data in the reference refresh interval duration of the reference memory cell; and calculating the ratio between the reference refresh rate and the time ratio corresponding to the memory unit for each memory unit to obtain the target refresh rate of the memory unit in the target refresh interval duration.
In an alternative embodiment, the reference refresh amount is the number of refresh units for each of the data cells in the memory cell during the reference refresh interval.
In an alternative embodiment, the semiconductor under test is a dynamic random access memory.
Referring to fig. 9, in order to implement the above memory refresh method, in one embodiment of the disclosure, a memory refresh apparatus 900 is provided. Fig. 9 shows a schematic architecture diagram of a memory refresh apparatus 900, the memory refresh apparatus 900 comprising: an acquisition module 910 and a control module 920, wherein:
The acquiring module 910 is configured to acquire a target refresh interval duration of each memory cell in the semiconductor to be tested, and a target refresh amount within the target refresh interval duration; the target refresh interval duration and the target refresh amount are determined according to the memory refresh parameter determining method according to any one of the above;
The control module 920 is configured to control each corresponding memory unit in the semiconductor to be tested to perform memory refresh based on the target refresh interval duration and the target refresh amount.
Exemplary embodiments of the present disclosure also provide a computer readable storage medium, which may be implemented in the form of a program product comprising program code for causing an electronic device to carry out the steps according to the various exemplary embodiments of the disclosure as described in the above section of the "exemplary method" when the program product is run on the electronic device. In one embodiment, the program product may be implemented as a portable compact disc read only memory (CD-ROM) and includes program code and may be run on an electronic device, such as a personal computer. However, the program product of the present disclosure is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The computer readable signal medium may include a data signal propagated in baseband or as part of a carrier wave with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Program code for carrying out operations of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider). In the embodiments of the present disclosure, the program code stored in the computer readable storage medium may implement any step of the above memory refresh parameter determination method or the memory refresh method when executed.
Referring to fig. 10, the exemplary embodiment of the present disclosure further provides an electronic device 1000, which may be a background server of the information platform. The electronic device 1000 is described below with reference to fig. 10. It should be understood that the electronic device 1000 shown in fig. 10 is merely an example and should not be construed to limit the functionality and scope of use of embodiments of the present disclosure in any way.
As shown in fig. 10, the electronic device 1000 is embodied in the form of a general purpose computing device. Components of electronic device 1000 may include, but are not limited to: at least one processing unit 1010, at least one memory unit 1020, and a bus 1030 that connects the various system components, including the memory unit 1020 and the processing unit 1010.
Wherein the storage unit stores program code that is executable by the processing unit 1010 such that the processing unit 1010 performs steps according to various exemplary embodiments of the present invention described in the above section of the "exemplary method" of the present specification. For example, the processing unit 1010 may perform the method steps shown in fig. 2, etc.
The memory unit 1020 may include volatile memory units such as a random access memory unit (RAM) 1021 and/or a cache memory unit 1022, and may further include a read only memory unit (ROM) 1023.
Storage unit 1020 may also include a program/utility 1024 having a set (at least one) of program modules 1025, such program modules 1025 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.
Bus 1030 may include a data bus, an address bus, and a control bus.
The electronic device 1000 may also communicate with one or more external devices 2000 (e.g., keyboard, pointing device, bluetooth device, etc.) via input/output (I/O) interface 1040. Electronic device 1000 can also communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, e.g., the Internet, through network adapter 1050. As shown, network adapter 1050 communicates with other modules of electronic device 1000 via bus 1030. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with the electronic device 1000, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.
In the embodiments of the present disclosure, any step of the above memory refresh parameter determination method or the memory refresh method may be implemented when the program code stored in the electronic device is executed.
It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with exemplary embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.
Those skilled in the art will appreciate that the various aspects of the present disclosure may be implemented as a system, method, or program product. Accordingly, various aspects of the disclosure may be embodied in the following forms, namely: an entirely hardware embodiment, an entirely software embodiment (including firmware, micro-code, etc.) or an embodiment combining hardware and software aspects may be referred to herein as a "circuit," module "or" system. Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (15)
1. A memory refresh parameter determination method, comprising:
For each memory cell in a semiconductor to be tested, determining a time ratio between a data retention time length of the memory cell and a reference data retention time length of a reference memory cell; the reference memory cell is a memory cell with the shortest data retention time in the semiconductor to be tested;
for each memory unit, determining a target refresh interval duration of the memory unit according to a ratio of a reference refresh interval duration of the reference memory unit to the time;
And determining a target refresh amount of the memory unit in the target refresh interval duration according to a ratio of the reference refresh amount of the reference memory unit to the memory data in the reference refresh interval duration and the time for each memory unit.
2. The memory refresh parameter determination method of claim 1, wherein prior to said determining a time ratio between a data retention period of the memory cell and a reference data retention period of a reference memory cell for each memory cell in a semiconductor under test, the method further comprises:
Acquiring the data retention time length of each memory unit in the semiconductor to be tested in a data retention test;
And determining the memory unit corresponding to the minimum value in each data holding time period as the reference memory unit.
3. The method of claim 2, wherein the obtaining the data retention time period of each memory cell in the semiconductor under test during the data retention test comprises:
Performing mass production test on the semiconductor to be tested to obtain a test result of the semiconductor to be tested;
And extracting the data retention time length of each memory unit from the test result.
4. The memory refresh parameter determination method of claim 1, wherein after the time ratio between the data retention period of the memory cell and the reference data retention period of the reference memory cell is determined for each memory cell in the semiconductor under test, the method further comprises:
And storing the time ratio corresponding to each memory unit in a preset memory module in the semiconductor to be tested.
5. The memory refresh parameter determination method of claim 1, further comprising:
and storing the target refreshing quantity corresponding to each memory unit in a preset storage module in the semiconductor to be tested.
6. The method according to claim 4 or 5, wherein the predetermined memory module is a readable register in the semiconductor under test.
7. The method of claim 1, wherein determining, for each of the memory cells, a target refresh interval duration for the memory cell based on a ratio of a reference refresh interval duration for the reference memory cell to the time comprises:
and calculating a ratio between the reference refresh interval duration of the reference memory unit and the time ratio corresponding to the memory unit for each memory unit to obtain the target refresh interval duration of the memory unit.
8. The memory refresh parameter determining method according to claim 1, wherein the determining, for each of the memory cells, the target refresh amount of the memory cell in the target refresh interval duration according to a ratio of a reference refresh amount of the reference memory cell to the memory data in the reference refresh interval duration, includes:
determining the reference refresh amount of the memory data in the reference refresh interval duration of the reference memory unit;
and calculating the ratio between the reference refresh rate and the time ratio corresponding to the memory unit for each memory unit to obtain the target refresh rate of the memory unit in the target refresh interval duration.
9. The memory refresh parameter determination method of claim 1, wherein the reference refresh amount is a number of refresh units for each of the memory units within the reference refresh interval duration.
10. The method of claim 1, wherein the semiconductor under test is a dynamic random access memory.
11. A memory refresh method, comprising:
Acquiring a target refresh interval duration of each memory unit in a semiconductor to be tested and a target refresh amount in the target refresh interval duration; wherein the target refresh interval duration and the target refresh amount are determined according to the memory refresh parameter determination method according to any one of claims 1 to 10;
And controlling each corresponding memory unit in the semiconductor to be tested to carry out memory refreshing based on the target refresh interval duration and the target refresh amount.
12. A memory refresh parameter determination device, the device comprising:
A first determining module, configured to determine, for each memory cell in a semiconductor to be tested, a time ratio between a data retention period of the memory cell and a reference data retention period of a reference memory cell; the reference memory cell is a memory cell with the shortest data retention time in the semiconductor to be tested;
A second determining module, configured to determine, for each of the memory units, a target refresh interval duration of the memory unit according to a ratio of a reference refresh interval duration of the reference memory unit to the time;
And a third determining module, configured to determine, for each memory cell, a target refresh amount of the memory cell in the target refresh interval duration according to a ratio of a reference refresh amount of the reference memory cell to memory data in the reference refresh interval duration to the time.
13. A memory refresh apparatus, the apparatus comprising:
The acquisition module is used for acquiring the target refresh interval duration of each memory unit in the semiconductor to be tested and the target refresh amount in the target refresh interval duration; wherein the target refresh interval duration and the target refresh amount are determined according to the memory refresh parameter determination method according to any one of claims 1 to 10;
and the control module is used for controlling the memory units corresponding to the semiconductor to be tested to carry out memory refreshing based on the target refresh interval duration and the target refresh amount.
14. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the method of any one of claims 1 to 11.
15. An electronic device, comprising:
A processor; and
A memory for storing executable instructions of the processor;
Wherein the processor is configured to perform the method of any one of claims 1 to 11 via execution of the executable instructions.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN202211269164.5A CN117935874A (en) | 2022-10-17 | 2022-10-17 | Memory refresh parameter determination, memory refresh method, device, medium and equipment |
| PCT/CN2022/129356 WO2024082343A1 (en) | 2022-10-17 | 2022-11-02 | Memory refresh parameter determination method and apparatus, memory refresh method and apparatus, and medium and device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211269164.5A CN117935874A (en) | 2022-10-17 | 2022-10-17 | Memory refresh parameter determination, memory refresh method, device, medium and equipment |
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| US7990795B2 (en) * | 2009-02-19 | 2011-08-02 | Freescale Semiconductor, Inc. | Dynamic random access memory (DRAM) refresh |
| CN102194513B (en) * | 2010-03-11 | 2013-07-31 | 复旦大学 | Circuit, method and memory for automatically adjusting refresh frequency of memory |
| CN105280215B (en) * | 2014-06-09 | 2018-01-23 | 华为技术有限公司 | Dynamic random access memory DRAM method for refreshing, equipment and system |
| KR20180069177A (en) * | 2016-12-14 | 2018-06-25 | 에스케이하이닉스 주식회사 | Memroy device and operating method for memory device |
| US10991414B2 (en) * | 2019-04-12 | 2021-04-27 | Western Digital Technologies, Inc. | Granular refresh rate control for memory devices based on bit position |
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