CN117930926A - Low dropout voltage regulator, clock generation circuit and memory device - Google Patents

Abstract

A Low Dropout (LDO) regulator is configured to generate first through nth output voltages, where n is a natural number greater than or equal to 2, and each of the first through nth output voltages corresponds to a reference voltage. The LDO voltage stabilizer comprises: an amplifier configured to generate an error voltage based on the reference voltage and a first output voltage among the first to nth output voltages; a trimming control circuit configured to generate first to n-1 th trimming signals based on the first to n-th output voltages; and an output buffer circuit configured to generate first to nth output voltages based on the error voltage and the first to nth trimming signals.

Description

Low dropout regulator, clock generation circuit and memory device

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Korean Patent Application No. 10-2022-0137764 filed on October 24, 2022, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2022-0186388 filed on December 27, 2022, in the Korean Intellectual Property Office, the disclosures of each of which are incorporated herein by reference in their entirety.

Technical Field

The inventive concept relates to a low dropout (LDO) regulator, and more particularly, to an LDO regulator configured to generate an output voltage based on a trimming signal.

Background technique

As technology advances, multiple chips for performing various operations are equipped in one electronic device. In this case, in order to operate the chips included in the electronic device with accurate timing, the input of an accurate clock signal is expected or required. For example, modules such as dual in-line memory modules (DIMMs) each include multiple dynamic random access memory (DRAM) chips, and the accurate operation of each DRAM chip expects or requires the input of an accurate clock signal.

The clock generation circuit can generate a clock signal based on the applied voltage. In this case, a power conversion circuit such as an LDO regulator can be used to adjust the level of the voltage applied to the clock generation circuit. In this case, the LDO regulator can apply multiple output voltages to the clock generation circuit through an output buffer. However, the voltage applied to the clock generation circuit may change due to reasons such as current consumption and internal resistance caused by the lines included in the output buffer. When the voltage applied to the clock generation circuit changes, a clock skew (clock skew) between multiple clock signals generated by the clock generation circuit will occur. Clock skew may be the cause of electronic equipment failures such as communication errors. Therefore, it is desirable or necessary to develop a method for solving such problems.

Summary of the invention

The inventive concept provides a low dropout (LDO) regulator that can apply a specific voltage to a clock generating circuit.

According to one aspect of the inventive concept, a low dropout (LDO) regulator is configured to generate first to nth output voltages, wherein n is a natural number greater than or equal to 2, and each of the first to nth output voltages corresponds to a reference voltage. The LDO regulator includes: an amplifier configured to generate an error voltage based on the reference voltage and the first output voltage among the first to nth output voltages; a trimming control circuit configured to generate first to n-1th trimming signals based on the first to nth output voltages; and an output buffer circuit configured to generate the first to nth output voltages based on the error voltage and the first to n-1th trimming signals.

According to another aspect of the inventive concept, a clock generation circuit includes: a low dropout (LDO) regulator configured to generate a plurality of output voltages, each of the plurality of output voltages corresponding to a reference voltage; and a clock oscillation circuit configured to generate a plurality of clock signals based on the plurality of output voltages. The LDO regulator includes: an amplifier configured to generate an error voltage based on the reference voltage and a first output voltage among the plurality of output voltages; a trimming control circuit configured to generate a plurality of trimming signals based on the plurality of output voltages; and an output buffer circuit configured to generate the plurality of output voltages based on the error voltage and the plurality of trimming signals.

According to another aspect of the inventive concept, a memory device includes: a clock generation circuit configured to generate a plurality of clock signals; and a plurality of dynamic random access memory (DRAM) chips configured to operate based on the plurality of clock signals. The clock generation circuit includes: a low dropout (LDO) regulator configured to generate a plurality of output voltages, each of the plurality of output voltages corresponding to a reference voltage; and a clock oscillation circuit configured to generate the plurality of clock signals based on the plurality of output voltages. The LDO regulator includes: an amplifier configured to generate an error voltage based on the reference voltage and a first output voltage among the plurality of output voltages; a trimming control circuit configured to generate a plurality of trimming signals based on the plurality of output voltages; and an output buffer circuit configured to generate the plurality of output voltages based on the error voltage and the plurality of trimming signals.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG1 is a block diagram illustrating a clock generation circuit according to an example embodiment;

2 is a circuit diagram illustrating a low dropout (LDO) regulator according to an example embodiment;

3 is a circuit diagram showing a detailed configuration of a trimming control circuit of an LDO regulator according to an example embodiment;

FIG4 is a circuit diagram showing an example embodiment of a flipped voltage follower (FVF) buffer of an LDO regulator;

FIG5 is a circuit diagram showing another example embodiment of a FVF buffer of an LDO regulator;

6 is a timing diagram showing voltages and signals of a trimming control circuit of an LDO regulator according to an example embodiment;

7 is a flow chart illustrating an operating method of an LDO regulator according to an example embodiment;

8 is a flow chart illustrating an operating method of a trimming control circuit of an LDO regulator according to an example embodiment;

FIG. 9 is a block diagram illustrating a memory device according to example embodiments.

Detailed ways

Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a clock generating circuit 10 according to an example embodiment.

1 , a clock generating circuit 10 according to an example embodiment may include a low dropout (LDO) regulator 100 and a clock oscillation circuit 200 .

The clock generation circuit 10 may generate a plurality of clock signals CLK ₁ to CLK _n . The number of the clock signals CLK ₁ to CLK _n may be n (where n is a natural number 2 or greater), and the plurality of clock signals CLK ₁ to CLK _n may include a first clock signal CLK ₁ to an nth clock signal CLK _n . The clock generation circuit 10 may output the generated plurality of clock signals CLK ₁ to CLK _n to other devices (e.g., a dynamic random access memory (DRAM) chip). In some example embodiments, the plurality of clock signals CLK ₁ to CLK _n generated by the clock generation circuit 10 may be used as signals serving as standards for operations in other devices. Therefore, it is desirable that the clock generation circuit 10 generates a plurality of clock signals CLK ₁ to CLK _n without errors such as clock skew.

The LDO regulator 100 may generate a plurality of output voltages V _O1 to V _On corresponding to a reference voltage V _REF . The number of the output voltages V _O1 to V _On may be n, which is equal to the number of clock signals CLK ₁ to CLK _n , and the plurality of output voltages V _O1 to V _On may include first to nth output voltages V _On . For example, the LDO regulator 100 may generate a plurality _{of output voltages V O1 to} V _On having the same or substantially the same level as the reference voltage V _REF .

The LDO regulator 100 may include an amplifier 110 , a trim control circuit 120 , and an output buffer circuit 130 .

The amplifier 110 may generate an error voltage E _O based on a reference voltage V _REF and a first output voltage V _O1 . The amplifier 110 may amplify a difference between the reference voltage V _REF and the first output voltage V _O1 to generate the error voltage E _O. For example, the amplifier 110 may subtract the reference voltage V _REF from the first output voltage V _O1 , and may amplify the subtraction result at a desired (or predetermined) ratio to generate the error voltage E _O.

The amplifier 110 may receive a first output voltage V _O1 from an output buffer circuit 130 described below. In some example embodiments, the first output voltage V _O1 may be a voltage generated by the output buffer circuit 130 at a previous stage.

The reference voltage V _REF may be a voltage corresponding to a voltage to be generated by the LDO regulator 100 . In an example embodiment, the reference voltage V _REF may be a voltage received from an external host device. In another example embodiment, the reference voltage V _REF may be a voltage stored in the LDO regulator 100 .

The trimming control circuit 120 may generate a plurality of trimming signals TRM ₁ to TRM _n-1 based on the plurality of output voltages V _O1 to V _On .

The trimming control circuit 120 may receive a plurality of output voltages V _O1 to V _On from an output buffer circuit 130 described below. In some example embodiments, each of the plurality of output voltages V _O1 to V _On may be a voltage generated by the output buffer circuit 130 at a previous stage.

The plurality of trim signals TRM ₁ to TRM _n-1 may be used to generate a plurality of output voltages V _O1 to V _On in the output buffer circuit 130 described below. In example embodiments, each of the plurality of trim signals TRM ₁ to TRM _n-1 may be a signal for performing control so that levels of the plurality of output voltages V _O1 to V _On in the output buffer circuit 130 are maintained equal or substantially equal to each other.

The number of the plurality of trimming signals TRM ₁ to TRM _n-1 may be n-1 less than the number of the output voltages _{V O1} to V _On by 1, and may include first to n-1th trimming signals TRM _n-1 . In some example embodiments, the first trimming signal TRM ₁ may be a signal for performing control so that the level of the first output voltage V _O1 and the level of the second output voltage V _O2 are maintained equal to each other. In addition, the k-1th trimming signal TRM _k-1 (where k is a natural number greater than or equal to 2 and less than or equal to n) may be a signal for performing control so that the level of the first output voltage V _O1 and the level of the kth output voltage V _Ok are maintained equal to or substantially equal to each other. In addition, the n-1th trimming signal TRM _n-1 may be a signal for performing control so that the level of the first output voltage V _O1 and the level of the nth output voltage V _On are maintained equal to each other.

A more detailed structure and operation of the trimming control circuit 120 will be described below with reference to FIG. 3 .

The output buffer circuit 130 may generate a plurality of output voltages V _O1 to V _On based on the error voltage _EO and the plurality of trimming signals _TRM1 to TRMn _-1 . A more detailed structure and operation of the output buffer circuit 130 will be described below with reference to FIG.

The clock oscillation circuit 200 may generate a plurality of clock signals _CLK1 to _{CLKn based} on a plurality of output voltages V _O1 to V _On . The clock oscillation circuit 200 may include a plurality of oscillators, and may respectively generate a plurality of clock signals _CLK1 to _CLKn based on a plurality of output voltages V O1 to V _On by using the plurality of oscillators. In some example embodiments, the number of oscillators may be equal to the number of output voltages V _O1 to V _On , and the kth oscillator may generate the kth clock signal CLKk based on the kth output voltage V _Ok .

FIG. 2 is a circuit diagram illustrating an LDO regulator 100 according to an example embodiment.

2 , an LDO regulator 100 according to example embodiments may include an amplifier 110 , a trimming control circuit 120 , and an output buffer circuit 130 .

The amplifier 110 may generate an error voltage E _O based on a reference voltage V _REF and a first output voltage V _O1 . In example embodiments, the amplifier 110 may be an error amplifier.

The trimming control circuit 120 may generate a plurality of trimming signals _TRM1 to TRMn _-1 based on the plurality of output voltages V _O1 to V _On . A more detailed structure and operation of the trimming control circuit 120 will be described below with reference to FIG.

The output buffer circuit 130 may generate a plurality of output voltages V _O1 to V _On based on the error voltage _EO and a plurality of trimming signals TRM ₁ to TRM _n−1 .

The output buffer circuit 130 may include a plurality of flipped voltage follower (FVF) buffers _FVF1 to _FVFn .

2 , the output buffer circuit 130 is illustrated as including a plurality of power delivery network (PDN) resistors _RPDN , but each of the plurality of PDN resistors _RPDN may not be a resistor actually connected between elements in the output buffer circuit 130, and may be an internal resistor caused by a line included in the output buffer circuit 130. Due to the plurality of PDN resistors _RPDN , when the plurality of FVF buffers _FVF1 to _FVFn are implemented to be equal or substantially equal to each other and the same error voltage _EO is received, voltages having different levels may be output.

Furthermore, in FIG. 2 , a plurality of oscillators 210_1 to 210 — n included in the output buffer circuit 130 are illustrated, and in some example embodiments, the plurality of oscillators 210_1 to 210 — n may be elements included in the clock oscillation circuit 200 of FIG. 1 .

A plurality of FVF buffers _FVF1 to _FVFn may generate a plurality of output voltages V _O1 to V _On based on the error voltage _EO and a plurality of trimming signals _TRM1 to TRMn _-1 . The number of FVF buffers _FVF1 to _FVFn may be n which is equal to the number of output voltages V _O1 to V _On and may include first to nth FVF buffers _FVF1 to _FVFn .

A plurality of FVF buffers _FVF1 to _FVFn may receive the error voltage _EO output from the amplifier 110. At this time, the first FVF buffer _FVF1 may not receive the plurality of trimming signals _TRM1 to TRMn _-1 . This may be because the plurality of output voltages _V01 to _VOn are controlled to be equal to or substantially equal to the level of the first output voltage _V01 . In addition, the second FVF buffer _FVF2 to the nth FVF buffer _FVFn may receive the first trimming signal _TRM1 to the n-1th trimming signal TRMn _-1 . For example, the kth FVF buffer _FVFk may receive the k-1th trimming signal TRMk _-1 .

The first FVF buffer _FVF1 may generate a first output voltage V _O1 based on the error voltage _EO .

The second to nth FVF buffers _FVF2 to _FVFn may generate second to nth output voltages _V02 to _VOn based on the error voltage _EO and the first to n-1th trimming signals _TRM1 to TRMn _-1 . For example, the kth FVF buffer _FVFk may generate a kth output voltage _VOk based on the error voltage _EO and the k-1th trimming signal TRMk _-1 .

In example embodiments, the second FVF buffer FVF ₂ to the nth FVF buffer FVF _n may respectively control bias currents based on the first trimming signal TRM ₁ to the n-1th trimming signal TRM _n-1 , and may generate second output voltages V _O2 to the nth output voltage V _On based on the controlled bias currents. An example embodiment in which the second FVF buffer FVF ₂ to the nth FVF buffer FVF _n controls the bias current will be described in more detail below with reference to FIG.

In an example embodiment, the second FVF buffer FVF ₂ to the nth FVF buffer FVF _n may respectively control connections between a plurality of target switching elements based on the first trimming signal TRM ₁ to the n-1th trimming signal TRM _n-1 , and may generate a second output voltage V _O2 to an nth output voltage V _On based on voltages of the plurality of target switching elements. An example embodiment in which the second FVF buffer FVF ₂ to the nth FVF buffer FVF _n controls connections between a plurality of target switching elements will be described in more detail below with reference to FIG.

FIG. 3 is a circuit diagram illustrating a detailed configuration of the trimming control circuit 120 of the LDO regulator according to an example embodiment.

3 , the trimming control circuit 120 according to an embodiment may include a multiplexer (MUX) 121, a comparison circuit 122, and a trimming signal generator 123. According to an example embodiment, the trimming control circuit 120 may further include a low pass filter (LPF) 124.

The multiplexer 121 may output one of the second output voltage V _O2 to the nth output voltage V _On based on the selection signal SEL.

The selection signal SEL may be a signal for driving the multiplexer 121 in the trimming control circuit 120. In example embodiments, the selection signal SEL may be preset so that the multiplexer 121 alternately selects the second output voltage V _O2 to the nth output voltage V _On .

The multiplexer 121 may sequentially output the second output voltage V _O2 to the nth output voltage V _On based on the selection signal SEL. For example, the multiplexer 121 may sequentially output the second output voltage V _O2 , the third output voltage V _O3 , and the fourth output voltage V _O4 based on the selection signal SEL.

The comparison circuit 122 may compare the first output voltage V _O1 with the k-th output voltage V _Ok output by the multiplexer 121 to output comparison signals COM ₁ and COM _2. In example embodiments, the comparison signals COM ₁ and COM ₂ may include a first comparison signal COM ₁ and a second comparison signal COM _2. The comparison circuit 122 may output a result obtained by determining whether the k-th output voltage V _Ok output by the multiplexer 121 is within a desired (or predetermined) reference error range with respect to the first output voltage V _O1 as the comparison signals COM ₁ and COM ₂ .

The comparison circuit 122 may include a first power source 122_1 , a second power source 122_2 , a first comparator 122_3 , and a second comparator 122_4 .

The first power supply 122_1 may sum the first output voltage V _O1 and the offset voltage V _OFS to output an up voltage V _UP .

In more detail, the first power supply 122_1 may be a power element having a level of an offset voltage V _OFS . The offset voltage V _OFS may be set to a value corresponding to half of a reference error range. The first power supply 122_1 may receive a first output voltage V _O1 through a negative terminal. In addition, the first power supply 122_1 may output an upper voltage V _UP having a level of the sum of the first output voltage V _O1 and the offset voltage V _OFS through a positive terminal. At this time, the positive terminal of the first power supply 122_1 may be connected to a first comparator 122_3 described below.

The second power supply 122_2 may subtract the offset voltage V _OFS from the first output voltage V _O1 to output the lower voltage V _DN .

In more detail, the second power supply 122_2 may be a power element having a level of an offset voltage V _OFS . In some example embodiments, the second power supply 122_2 may be a power element having a voltage level that is the same or substantially the same as a voltage level of the first power supply 122_1. The second power supply 122_2 may receive the first output voltage V _O1 through a positive terminal. In addition, the second power supply 122_2 may output a lower voltage V _DN through a negative terminal, the lower voltage V _DN having a level obtained by subtracting the offset voltage V _OFS from the first output voltage V _O1 . At this time, the negative terminal of the second power supply 122_2 may be connected to a second comparator 122_4 described below.

The first comparator 122_3 may compare the upper voltage V _UP with the kth output voltage V _Ok to generate a first comparison signal COM _1. The first comparison signal COM ₁ may be a signal indicating a result obtained by determining whether the kth output voltage V _Ok is greater than an upper limit of a reference error range. For example, the first comparator 122_3 may subtract the upper voltage V _UP from the kth output voltage V _Ok , and may generate the first comparison signal COM ₁ based on whether the subtraction result has a positive value.

When the kth output voltage V _Ok is greater than the upper voltage V _UP , the first comparator 122_3 may output a first comparison signal COM ₁ having a first value (e.g., logic 1). On the other hand, when the kth output voltage V _Ok is less than or equal to the upper voltage V _UP , the first comparator 122_3 may output a first comparison signal COM ₁ having a second value (e.g., logic 0).

The second comparator 122_4 may compare the lower voltage V _DN with the kth output voltage V _Ok to generate a second comparison signal COM ₂ . The second comparison signal COM ₂ may be a signal indicating a result obtained by determining whether the kth output voltage V _Ok is greater than a lower limit of a reference error range. For example, the second comparator 122_4 may subtract the lower voltage V _DN from the kth output voltage V _Ok , and may generate the second comparison signal COM ₂ based on whether the subtraction result has a positive value.

When the kth output voltage V _Ok is less than the lower voltage V _DN , the second comparator 122_4 may output a second comparison signal COM ₂ having a third value (e.g., logic 1). On the other hand, when the kth output voltage V _Ok is greater than or equal to the lower voltage V _DN , the second comparator 122_4 may output a second comparison signal COM ₂ having a fourth value (e.g., logic 0).

The trimming signal generator 123 may generate a (k-1)th trimming signal TRM _k-1 based on the selection signal SEL and the comparison signals COM ₁ and COM ₂ .

In an example embodiment, when the first comparison signal _COM1 has the first value, the trim signal generator 123 may generate the k-1th trim signal TRM _k-1 for performing control to reduce the k-th output voltage V _Ok . Since the case where the first comparison signal _COM1 has the first value indicates that the k-th output voltage V _Ok is greater than the upper limit of the reference error range, the trim signal generator 123 may generate the k-1th trim signal TRM _k-1 for performing control to reduce the k-th output voltage V _Ok .

In an example embodiment, when the second comparison signal COM ₂ has the third value, the trim signal generator 123 may generate the k-1th trim signal TRM _k-1 for performing control to increase the k-th output voltage V _Ok . Since the case where the second comparison signal COM ₂ has the third value indicates that the k-th output voltage V _Ok is less than the lower limit of the reference error range, the trim signal generator 123 may generate the k-1th trim signal TRM _k-1 for performing control to increase the k-th output voltage V _Ok .

In an example embodiment, when the first comparison signal COM ₁ has the second value and the second comparison signal COM ₂ has the fourth value, the trim signal generator 123 may generate the k-1th trim signal TRM _k-1 for performing control to completely maintain the k-th output voltage V _Ok . Since the case where the first comparison signal COM ₁ has the second value and the second comparison signal COM ₂ has the fourth value indicates that the k-th output voltage V _Ok is within the reference error range, the trim signal generator 123 may generate the k-1th trim signal TRM _k-1 for performing control to completely maintain the k-th output voltage V _Ok .

The trimming signal generator 123 may receive the same selection signal SEL simultaneously with the multiplexer 121. For example, when the selection signal for allowing the k-th output voltage V _Ok to be output is input to the multiplexer 121, the trimming signal generator 123 may receive the same selection signal SEL simultaneously or substantially simultaneously, and thus may generate the k-1-th trimming signal TRM _k-1 for performing control so that the levels of the first output voltage V _O1 and the k-th output voltage V _Ok are maintained to be equal to each other. Therefore, the trimming signal generator 123 may sequentially generate the first trimming signal TRM ₁ to the n-1-th trimming signal TRM _n-1 based on the selection signal SEL. For example, the trimming signal generator 123 may sequentially output the first trimming signal TRM ₁ , the second trimming signal TRM ₂ , and the third trimming signal TRM ₃ based on the selection signal SEL.

The low pass filter 124 may remove noise included in the first output voltage V _O1 and may input the first output voltage V _O1 from which the noise is removed. The low pass filter 124 may receive the first output voltage V _O1 . The low pass filter 124 may remove high frequency noise included in the received first output voltage V _O1 . The low pass filter 124 may output the first output voltage V _O1 from which the noise is removed to the comparison circuit 122.

FIG. 4 is a circuit diagram illustrating an embodiment of a FVF buffer of the LDO regulator 100 according to an example embodiment.

4 , an example of circuit implementation of the second through nth FVF buffers FVF ₂ through FVF _n included in the output buffer circuit 130 included in the LDO regulator 100 according to example embodiments can be seen.

In the example embodiment of FIG. 4 , the kth FVF buffer FVF _k may include a current source I _S , a first switching element N1, a second switching element N2, a third switching element N3, a fourth switching element P1, a fifth switching element P2, and a sixth switching element P3.

The current source _IS can supply a bias current to the first switching element N1. Therefore, the first current _I1 can be applied to one end of the first switching element N1. The first switching element N1 and the second switching element N2 can be used as a current mirror. Therefore, a second current _I2 having a desired (or predetermined) ratio with the first current _I1 can flow in the second switching element N2.

The third switching element N3 may operate based on the input voltage V _N3 .

The third current _I3 which is the same as the output current may flow in the fifth switching element P2. At this time, the fourth switching element P1 and the fifth switching element P2 may function as a current mirror. Therefore, the fourth current _I4 which has a desired (or predetermined) ratio with the third current _I3 may flow in the fourth switching element P1.

The error voltage _EO may be input to the gate terminal of the sixth switching element P3. The voltage input to the gate terminal of the sixth switching element P3 may increase the gate-source voltage _VGS , and thus a kth output voltage _VOk may be generated.

In some example embodiments, the kth output voltage V _Ok may be expressed as in Equation 1 below.

[Equation 1]

In Equation 1, B/A may represent a current ratio between the first switching element N1 and the second switching element N2, and C/D may represent a current ratio between the fourth switching element P1 and the fifth switching element P2. In addition, β _P3 may represent a current gain of the sixth switching element P3, W _P3 may represent a width of the sixth switching element P3, L _P3 may represent a length of the sixth switching element P3, and V _THP3 may represent a threshold voltage of the sixth switching element P3.

4, the k-1th trimming signal TRM _k-1 may be applied to the current source _IS . At this time, the current source _IS may adjust the bias current based on the k-1th trimming signal TRM _k-1 . The bias current of the current source _IS may be the first current _I1 and may be applied to one end of the first switching element N1.

When the k-1th trimming signal TRM _k-1 is a signal for performing control to increase the k-th output voltage V _Ok , the current source I _S may increase the bias current. Therefore, the first current I ₁ may increase. In some example embodiments, as in Equation 1, the k-th output voltage V _Ok may be proportional to the first current I ₁ , and thus the k-th output voltage V _Ok may increase.

When the k-1th trimming signal TRM _k-1 is a signal for performing control to reduce the k-th output voltage V _Ok , the current source I _S may reduce the bias current. Therefore, the first current I ₁ may be reduced. In some example embodiments, as in Equation 1, the k-th output voltage V _Ok may be proportional to the first current I ₁ , and thus the k-th output voltage V _Ok may be reduced.

When the k-1th trimming signal TRM _k-1 is a signal for performing control to completely maintain the kth output voltage V _Ok , the current source I _S can completely maintain the bias current. Therefore, the first current I ₁ can be completely maintained, and the kth output voltage V _Ok can be completely maintained.

As described above, the LDO regulator 100 according to the example embodiment may generate a plurality of trimming signals TRM ₁ to TRM _n-1 (generated by the trimming control circuit 120) based on the plurality of output voltages V _O1 to V _On , and may adjust the bias current based on the current source _IS included in the second FVF buffer FVF ₂ to the nth FVF buffer FVF _n of the output buffer circuit 130 according to the plurality of trimming signals TRM ₁ to TRM _n-1 to control the constant level of the second FVF buffer FVF ₂ to the nth FVF buffer FVF _n . Therefore, by applying the constant plurality of output voltages V _O1 to V _On to the clock oscillation circuit 200, the occurrence of clock skew between the plurality of clock signals CLK ₁ to CLK _n generated by the clock generation circuit 10 may be reduced or prevented.

FIG. 5 is a circuit diagram illustrating another embodiment of a FVF buffer of the LDO regulator 100 according to example embodiments.

5, another example of a circuit implementation of the second FVF buffer _FVF2 to the nth FVF buffer _FVFn included in the output buffer circuit 130 included in the LDO regulator 100 according to the example embodiment can be seen. The example of the circuit implementation shown in FIG5 may be similar to the example of the circuit implementation shown in FIG4, and thus the differences therebetween will be mainly described.

In the example embodiment of FIG. 5 , unlike the embodiment of FIG. 4 , the k-1th trimming signal TRM _k-1 may be applied to the sixth switching element P3 instead of the current source I _S . Each FVF buffer may include a plurality of target switching elements connected in parallel to each other. In some example embodiments, the sixth switching element P3 may include a plurality of target switching elements connected in parallel to each other.

The connection between the plurality of target switching elements may be controlled based on the k-1th trimming signal TRM k _-1 . At this time, the connection between the plurality of target switching elements may be controlled to adjust the number of target switching elements operating based on the k-1th trimming signal TRM _k-1 .

When the k-1th trimming signal TRM _k-1 is a signal for performing control to increase the k-th output voltage V _Ok , the number of target switching elements operating among the plurality of target switching elements may be reduced. Therefore, the width _WP3 of the sixth switching element P3 may be reduced. In some example embodiments, as in Equation 1, the k-th output voltage V _Ok may be inversely proportional to the width _WP3 of the sixth switching element P3, and thus the k-th output voltage V _Ok may be increased.

When the k-1th trimming signal TRM _k-1 is a signal for performing control to reduce the k-th output voltage V _Ok , the number of target switching elements operating among the plurality of target switching elements may increase. Therefore, the width _WP3 of the sixth switching element P3 may increase. In some example embodiments, as in Equation 1, the k-th output voltage V _Ok may be inversely proportional to the width _WP3 of the sixth switching element P3, and thus the k-th output voltage V _Ok may decrease.

When the k-1th trimming signal TRM _k-1 is a signal for performing control to completely maintain the kth output voltage V _Ok , the number of target switching elements operating among the plurality of target switching elements may be maintained the same or substantially the same. Therefore, the kth output voltage V _Ok may be completely maintained.

As described above, the LDO regulator 100 according to the example embodiment may generate a plurality of trimming signals TRM ₁ to TRM _n-1 (generated by the trimming control circuit 120) based on the plurality of output voltages V _O1 to V _On , and may adjust the number of target switching elements operating among a plurality of target switching elements included in the second FVF buffer FVF ₂ to the nth FVF buffer FVF _n of the output buffer circuit 130 based on the plurality of trimming signals TRM ₁ to TRM _n- 1 to control the constant level of the plurality of output voltages V _O1 to V _On . Therefore, by applying the constant plurality of output voltages V _O1 to V _On to the clock oscillation circuit 200, the occurrence of clock skew between the plurality of clock signals CLK ₁ to CLK _n generated by the clock generation circuit 10 may be prevented.

FIG. 6 is a timing diagram illustrating voltages and signals of a trim control circuit of the LDO regulator 100 according to an example embodiment.

6 , in the LDO regulator 100 according to example embodiments, a timing diagram showing changes in first to fourth output voltages V _O1 to V _O4 , selection signals SEL2 to SEL4 , comparison signals (e.g., first and second comparison signals) COM ₁ and COM ₂ , and first to third trimming signals TRM ₁ to TRM ₃ can be seen.

Here, the selection signals SEL2 to SEL4 may include a second selection signal SEL2 allowing the multiplexer 121 to output the second output voltage V _O2 , a third selection signal SEL3 allowing the multiplexer 121 to output the third output voltage V _O3 , and a fourth selection signal SEL4 allowing the multiplexer 121 to output the fourth output voltage V _O4 .

At the first time T1, the second selection signal SEL2 may be activated. At this time, the second output voltage V _O2 may be greater than the first output voltage V _O1 by the value of the offset voltage V _OFS or more, so the first comparison signal COM ₁ may have the first value. Therefore, it can be seen that the value of the first trimming signal TRM ₁ decreases, so the second output voltage V _O2 decreases. In addition, the second FVF buffer FVF ₂ may output the second output voltage V _O2 that is decreased based on the first trimming signal TRM ₁ .

At the second time T2, the third selection signal SEL3 may be activated. At this time, the third output voltage V _O3 may be lower than the first output voltage V _O1 by the value of the offset voltage V _OFS or more, so the second comparison signal COM ₂ may have a third value. Therefore, it can be seen that the value of the second trimming signal TRM ₂ increases, so the third output voltage V _O3 increases. In addition, the third FVF buffer FVF ₃ may output the third output voltage V _O3 increased based on the second trimming signal TRM ₂ .

At the third time T3, the fourth selection signal SEL4 may be activated. At this time, because the fourth output voltage V _O4 is within the reference error range relative to the first output voltage V _O1 , the first comparison signal COM ₁ may have the second value, and the second comparison signal COM ₂ may have the fourth value. Therefore, it can be seen that the value of the third trimming signal TRM ₃ is maintained, and thus the fourth output voltage V _O4 is maintained. In addition, the fourth FVF buffer FVF ₄ may output the fourth output voltage V _O4 maintained based on the third trimming signal TRM ₃ .

At the fourth time T4, the second selection signal SEL2 may be activated. At this time, the second output voltage V _O2 may be reduced at the first time T1, so the second output voltage V _O2 may be within the reference error range relative to the first output voltage V _O1 . Therefore, the first comparison signal COM ₁ may have the second value, and the second comparison signal COM ₂ may have the fourth value. Therefore, it can be seen that the value of the first trimming signal TRM ₁ is maintained, so the second output voltage V _O2 is maintained. In addition, the second FVF buffer FVF ₂ may output the second output voltage V _O2 maintained based on the first trimming signal TRM ₁ .

At the fifth time T5, the third selection signal SEL3 may be activated. At this time, even if the third output voltage V _O3 may increase at the second time T2, the third output voltage V _O3 may be lower than the first output voltage V _O1 by the value of the offset voltage V _OFS or more, so the second comparison signal COM ₂ may have a third value. Therefore, it can be seen that the value of the second trimming signal TRM ₂ increases, so the third output voltage V _O3 increases. In addition, the third FVF buffer FVF ₃ may output the third output voltage V _O3 increased based on the second trimming signal TRM ₂ .

At the sixth time T6, the fourth selection signal SEL4 may be activated. Similar to the third time T3, the fourth output voltage V _O4 may be within the reference error range relative to the first output voltage V _O1 , and thus the fourth output voltage V _O4 may be controlled to be equal to or substantially equal to the fourth output voltage V _O4 at the third time T3, thereby the same or substantially the same fourth output voltage V _O4 may be output.

At the seventh time T7, the second selection signal SEL2 may be activated. Similar to the fourth time T4, the second output voltage V _O2 may be within the reference error range relative to the first output voltage V _O1 , and thus the second output voltage V _O2 may be controlled to be equal to or substantially equal to the second output voltage V _O2 at the fourth time T4, thereby the same or substantially the same second output voltage V _O2 may be output.

At the eighth time T8, the third selection signal SEL3 may be activated. At this time, the fifth output voltage V _O3 may increase at the fifth time T5, so the third output voltage V _O3 may be within the reference error range relative to the first output voltage V _O1 . Therefore, the first comparison signal COM ₁ may have the second value, and the second comparison signal COM ₂ may have the fourth value. Therefore, it can be seen that the value of the second trimming signal TRM ₂ is maintained, and thus the third output voltage V _O3 is maintained. In addition, the third FVF buffer FVF ₃ may output the third output voltage V _O3 maintained based on the second trimming signal TRM ₂ .

As described above, the LDO regulator 100 according to the example embodiment can sequentially output the second output voltage V _O2 to the nth output voltage V _On by using the multiplexer 121, sequentially generate the first trimming signal TRM ₁ to the n-1th trimming signal TRM _n-1 , and sequentially adjust the second output voltage V _O2 to the nth output voltage V _On . Therefore, the voltage difference between the plurality of output voltages V _O1 to V _On can be adjusted within the reference error range, and thus the occurrence of clock skew between the plurality of clock signals CLK ₁ to CLK _n generated by the clock generation circuit 10 can be reduced or prevented.

FIG. 7 is a flowchart illustrating an operating method of an LDO regulator according to example embodiments.

7 , in operation S710 , the LDO regulator 100 may generate an error voltage E _O . The LDO regulator 100 may generate the error voltage E _O by amplifying a difference between the first output voltage V _O1 and the reference voltage V _REF using the amplifier 110 .

In operation S720, the LDO regulator 100 may generate first to n-1th trimming signals TRM ₁ to TRM _n-1 . The LDO regulator 100 may generate the first to n-1th trimming signals TRM _n-1 based on the plurality of output voltages _{V O1} to V _On by using the trimming control circuit 120. The trimming control circuit 120 may sequentially generate each of the first to n-1th trimming signals TRM n-1. A method _of generating each of the first to n- _1th trimming signals TRM _{n -1} will be described in more detail below with reference to FIG. 8 .

FIG. 8 is a flowchart illustrating an operating method of a trimming control circuit of an LDO regulator according to example embodiments.

8 , in operation S810 , the trimming control circuit 120 may output a kth output voltage V _Ok based on a selection signal SEL. The trimming control circuit 120 may output a kth output voltage V _Ok , which is one of the second to nth output voltages V _O2 to _{V On ,} through the multiplexer 121 based on the selection signal SEL.

In operation S820, the trimming control circuit 120 may output comparison signals _COM1 and _COM2 . The trimming control circuit 120 may determine whether the kth output voltage V _Ok is within a reference error range with respect to the first output voltage V _O1 , and may output comparison signals _COM1 and _COM2 indicating the comparison result.

In operation S830 , the trimming control circuit 120 may generate a k−1th trimming signal TRM _k-1 based on the selection signal SEL and the comparison signals COM ₁ and COM _2. The trimming control circuit 120 may generate a k−1th trimming signal TRM k-1 corresponding to the selection signal SEL based on the comparison signals COM ₁ and COM ₂ by using the trimming signal generator ₁₂₃ .

Returning to FIG. 7 , in step S730, the LDO regulator 100 may generate the first output voltage V _O1 to the nth output voltage V _On . The LDO regulator 100 may generate the first output voltage V _O1 to the nth output voltage V _On by using the output buffer circuit 130. At this time, the output buffer circuit 130 may generate the first output voltage V O1 to the nth output voltage V _On by using a plurality of FVF buffers FVF ₁ to FVF _n based on the error voltage _EO and the first trimming signal _{TRM 1} to the n-1th trimming signal TRM _n-1 .

FIG. 9 is a block diagram illustrating a memory device 1 according to example embodiments.

9 , a memory device 1 according to example embodiments may include a clock generation circuit 10 and a plurality of DRAM chips (eg, first to fourth DRAM chips) 21 to 24 .

The clock generation circuit 10 may operate similarly to the clock generation circuit 10 described above with reference to FIGS. 1 to 8 .

The first clock signal _CLK1 generated by the clock generation circuit 10 may be applied to the first DRAM chip 21. The second clock signal _CLK2 generated by the clock generation circuit 10 may be applied to the second DRAM chip 22. The third clock signal _CLK3 generated by the clock generation circuit 10 may be applied to the third DRAM chip 23. The fourth clock signal _CLK4 generated by the clock generation circuit 10 may be applied to the fourth DRAM chip 24.

The plurality of DRAM chips 21 to 24 included in the memory device 1 can operate based on the plurality of clock signals CLK ₁ to CLK ₄ generated by the clock generation circuit 10 described above with reference to FIGS. 1 to 8 , and thus can reduce or prevent the occurrence of clock skew between the plurality of clock signals CLK ₁ to CLK _4. Therefore, a malfunction of the memory device 1 caused by the clock skew can be reduced or prevented.

In the above, some example embodiments have been described in the drawings and the specification. The example embodiments have been described by using the terms described herein, but this is only used to describe the inventive concept and is not used to limit the meaning or scope of the inventive concept. Therefore, it can be understood by those skilled in the art that various modifications and other example embodiments can be implemented according to the inventive concept.

One or more elements disclosed above may be included in or implemented in one or more processing circuits, such as hardware including logic circuits; hardware/software combinations (such as processors that execute software); or combinations thereof. For example, the processing circuits may more specifically include, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FGPA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and the like.

While the inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the inventive concepts.

Claims (20)

1. An LDO regulator, the LDO regulator being configured to generate a first output voltage to an nth output voltage, wherein n is a natural number greater than or equal to 2, and each of the first output voltage to the nth output voltage corresponds to a reference voltage, the LDO regulator being a low dropout regulator, and comprising: an amplifier configured to generate an error voltage based on the reference voltage and the first output voltage among the first to nth output voltages; a trimming control circuit configured to generate first to n-1 th trimming signals based on the first to n th output voltages; and An output buffer circuit is configured to generate the first to nth output voltages based on the error voltage and the first to n-1th trimming signals. 2 . The LDO regulator according to claim 1 , wherein the amplifier is configured to amplify a difference between the first output voltage and the reference voltage to generate the error voltage. 3. The LDO regulator according to claim 1, wherein the trimming control circuit comprises: a multiplexer configured to: output the first output voltage to the second output voltage to the kth output voltage among the nth output voltages based on a selection signal, wherein k is a natural number greater than or equal to 2 and less than or equal to n; a comparison circuit, the comparison circuit being configured to: compare the first output voltage with the kth output voltage output by the multiplexer to output a comparison signal; and A trimming signal generator is configured to generate a k-1th trimming signal from among the first to the n-1th trimming signals based on the selection signal and the comparison signal. 4 . The LDO regulator of claim 3 , wherein the trim control circuit further comprises a low pass filter configured to remove noise from the first output voltage and supply the first output voltage from which the noise is removed to the comparison circuit. 5. The LDO regulator according to claim 3, wherein: The multiplexer is configured to sequentially output the second output voltage to the nth output voltage based on the selection signal, and The trimming signal generator is further configured to sequentially generate the first to n-1 th trimming signals based on the selection signal. 6. The LDO regulator according to claim 3, wherein the comparison circuit comprises: a first power supply configured to: add an offset voltage to the first output voltage to output an upper voltage; a second power supply configured to: subtract the offset voltage from the first output voltage to output a lower voltage; a first comparator configured to compare the upper voltage with the kth output voltage among the first to nth output voltages to generate a first comparison signal; and A second comparator is configured to compare the lower voltage with the kth output voltage to generate a second comparison signal. 7. The LDO regulator according to claim 6, wherein: The first comparator is configured to: output the first comparison signal having a first value when the kth output voltage is greater than the upper voltage, and output the first comparison signal having a second value when the kth output voltage is less than or equal to the upper voltage, and The second comparator is configured to output the second comparison signal having a third value when the kth output voltage is less than the lower voltage, and to output the second comparison signal having a fourth value when the kth output voltage is greater than or equal to the lower voltage. 8. The LDO regulator according to claim 7, wherein the trim signal generator is configured to: when the first comparison signal has the first value, generating the k-1th trimming signal for performing control to reduce the kth output voltage, When the second comparison signal has the third value, generating the k-1th trimming signal for performing control to increase the kth output voltage, and When the first comparison signal has the second value and the second comparison signal has the fourth value, the k-1th trimming signal is generated to perform control to maintain the kth output voltage. 9. The LDO regulator according to claim 1, wherein the output buffer circuit is configured as follows: controlling a bias current based on the first to the (n-1)th trimming signals, and The first to nth output voltages are generated based on the bias current. 10. The LDO regulator according to claim 1, wherein the output buffer circuit is configured as follows: controlling connections between a plurality of target switching elements based on the first to the (n-1)th trimming signals, and The first to nth output voltages are generated based on voltages of the plurality of target switching elements. 11. The LDO regulator according to claim 1, wherein the output buffer circuit comprises: a first FVF buffer configured to generate the first output voltage based on the error voltage, the FVF being a flip voltage follower; and Second to nth FVF buffers are configured to generate the second to nth output voltages based on the error voltage and the first to n-1th trimming signals. 12. The LDO regulator of claim 11, wherein each of the second to the nth FVF buffers comprises a current source configured to adjust a bias current based on a corresponding one of the first to the n-1th trimming signals. 13. The LDO regulator according to claim 11, wherein: Each of the second to nth FVF buffers includes a plurality of target switching elements connected in parallel to each other, and Connections between the plurality of target switching elements are controlled based on the first to n-1th trimming signals. 14. A clock generation circuit, the clock generation circuit comprising: An LDO regulator, namely a low dropout regulator, configured to generate a plurality of output voltages, each of the plurality of output voltages corresponding to a reference voltage; and a clock oscillation circuit configured to: generate a plurality of clock signals based on the plurality of output voltages; Wherein, the LDO regulator comprises: an amplifier configured to generate an error voltage based on the reference voltage and a first output voltage of the plurality of output voltages, a trimming control circuit configured to generate a plurality of trimming signals based on the plurality of output voltages, and An output buffer circuit is configured to generate the plurality of output voltages based on the error voltage and the plurality of trimming signals. 15. The clock generation circuit according to claim 14, wherein the trimming control circuit comprises: a multiplexer configured to: output a second output voltage among the plurality of output voltages to a kth output voltage among the nth output voltages based on a selection signal, wherein k is a natural number greater than or equal to 2 and less than or equal to n; a comparison circuit, the comparison circuit being configured to: compare the first output voltage with the kth output voltage output by the multiplexer to output a comparison signal; and A trimming signal generator is configured to generate a (k-1)th trimming signal among the plurality of trimming signals based on the selection signal and the comparison signal. 16. The clock generation circuit according to claim 15, wherein: The multiplexer is configured to sequentially output the second output voltage to the nth output voltage based on the selection signal, and The trimming signal generator is configured to sequentially generate the plurality of trimming signals based on the selection signal. 17. The clock generation circuit according to claim 15, wherein the comparison circuit comprises: a first power supply configured to: add an offset voltage to the first output voltage to output an upper voltage; a second power supply configured to: subtract the offset voltage from the first output voltage to output a lower voltage; a first comparator configured to compare the upper voltage with the kth output voltage among the plurality of output voltages to generate a first comparison signal; and A second comparator is configured to compare the lower voltage with the kth output voltage to generate a second comparison signal. 18. The clock generation circuit according to claim 14, wherein the output buffer circuit is configured to: controlling a bias current based on the plurality of trim signals, and The plurality of output voltages are generated based on the bias current. 19. The clock generation circuit according to claim 14, wherein the output buffer circuit is configured as: controlling connections between a plurality of target switching elements based on the plurality of trimming signals, and The plurality of output voltages are generated based on the voltages of the plurality of target switching elements. 20. A storage device, comprising: a clock generation circuit configured to generate a plurality of clock signals; and a plurality of dynamic random access memory chips, wherein the plurality of dynamic random access memory chips are configured to operate based on the plurality of clock signals, Wherein, the clock generation circuit comprises: an LDO regulator, the LDO regulator being a low dropout regulator and the LDO regulator being configured to generate a plurality of output voltages, each of the plurality of output voltages corresponding to a reference voltage; and a clock oscillation circuit configured to generate the plurality of clock signals based on the plurality of output voltages, and The LDO regulator comprises: an amplifier configured to generate an error voltage based on the reference voltage and a first output voltage of the plurality of output voltages, a trimming control circuit configured to generate a plurality of trimming signals based on the plurality of output voltages, and An output buffer circuit is configured to generate the plurality of output voltages based on the error voltage and the plurality of trimming signals.