CN117851313B

CN117851313B - A DMA control system suitable for on-chip network architecture chips

Info

Publication number: CN117851313B
Application number: CN202311693914.6A
Authority: CN
Inventors: 李雪原; 汪杨; 韩昊东; 陈松; 康一
Original assignee: Institute of Artificial Intelligence of Hefei Comprehensive National Science Center
Current assignee: Institute of Artificial Intelligence of Hefei Comprehensive National Science Center
Priority date: 2023-12-08
Filing date: 2023-12-08
Publication date: 2024-12-24
Anticipated expiration: 2043-12-08
Also published as: CN117851313A

Abstract

The invention relates to the field of integrated circuit chip design, in particular to a DMA control system suitable for a network-on-chip architecture chip. The system comprises a central processor module serving as a core processor, a central processor configuration module for configuring PL end register parameters, an interrupt management module, a data management module for managing data, a data channel arbitration module for establishing a data transmission channel, a network-on-chip architecture chip writing module for writing data into a network-on-chip architecture chip, a network-on-chip architecture chip output data unpacking module for receiving data output by the network-on-chip architecture chip and unpacking and shunting, and a data small-sized data processing module for storing and processing the data output by the network-on-chip architecture chip, wherein the length of the data does not exceed a threshold value. According to the invention, by optimizing the data transmission channel and the data caching strategy, the high-efficiency data interaction between the network-on-chip architecture chip and the FPGA chip can be realized, and the overall efficiency of the system is greatly improved.

Description

DMA control system suitable for network architecture chip on chip

Technical Field

The invention relates to the field of integrated circuit chip design, in particular to a DMA control system suitable for a network-on-chip architecture chip.

Background

The network on chip is a technology for implementing IP (intellectual property) core interconnection and communication by using the concept of an interconnection network for complex system on chip design, but with the development of semiconductor technology, the complexity and integration of the system on chip are continuously improved, and the conventional bus communication architecture cannot meet the communication requirement. In this case, the network architecture on chip has become a preferred scheme for implementing communication between the cores on chip. Because the DMA (direct memory access) control system does not need the intervention of a CPU (central processing unit), the access to the memory is completed, and the efficiency of data transmission is improved. The technology has wide application in the fields of communication, computers, high-performance computing, embedded systems and the like, and plays an important role in improving the comprehensive performance and response speed of the processor.

Currently, in order to achieve efficient data interaction between a network-on-chip architecture chip and an FPGA chip, an FPGA-based DMA control system may be employed. The system utilizes the parallel processing capability and flexibility of the FPGA, and can quickly and efficiently transmit data after the CPU carries out initialized task information configuration on the DMA control system.

However, current FPGA-based DMA control systems have limited scheduling and management capabilities for data, reducing the overall efficiency of the system.

Disclosure of Invention

In order to solve the above problems, the present invention provides a DMA control system suitable for a network-on-chip architecture chip.

The system comprises:

When reading or transmitting data to the network-on-chip architecture chip, the central processing unit module enables a data sender to be matched with a data receiver by transmitting an instruction to the central processing unit configuration module, establishes a data transmission channel, and judges whether the data reading is completed or not according to an interrupt signal of the interrupt management module;

the central processing unit configuration module is used for configuring parameters of the PL end register, and sending an instruction through the central processing unit module so as to realize control and information interaction with the PL end designation module;

the interruption management module is used for managing interruption sent by the PL terminal to the central processing unit module;

The data management module is used for storing data required by the operation of the network-on-chip architecture chip and data output by the network-on-chip architecture chip, and providing an access interface for controlling the stored data;

The data channel arbitration module is used for matching a read data request of a data receiver and a write data request of a data sender so that the data sender and the data receiver establish a data transmission channel;

The on-chip network architecture chip writing module is used for sending a read request to the data channel arbitration module according to the instruction of the central processing unit configuration module, and writing data into the on-chip network architecture chip after a data transmission channel is established with a data sender;

the on-chip network architecture chip output data unpacking module is used for receiving the data packets or the network interface information packets output by the on-chip network architecture chip, unpacking and then shunting;

and the small data processing module is used for storing and processing data with the data length which is output by the network-on-chip architecture chip and does not exceed a threshold value.

Further, the data management module includes:

The PS end data management module is used for storing data required by the operation of the network architecture chip on the chip in the DDR of the PS end and controlling the read-write operation of the data;

The PL end data management module is used for storing the data with the data length exceeding the threshold value output by the network-on-chip architecture chip in the DDR of the PL end and controlling the read-write operation of the data;

Further, the PS-side data management module includes:

PSDDR for storing data required by the operation of the network-on-chip architecture chip;

PSDDR controller for managing and controlling the data read-write operations of PSDDR;

the MM2S PS sends a write request to the data channel arbitration module as a data sending direction according to an instruction of the CPU configuration module, and after a data transmission channel is established with a data receiving party, data is read from PSDDR through PSDDR controller for transmission;

S2MM PS, according to the instruction of the CPU configuration module, sends a read request to the data channel arbitration module as a data receiving direction, and after establishing a data transmission channel with a data sender, writes data into PSDDR through PSDDR controller.

Further, the PL-side data management module includes:

PL DDR, is used for storing the data that the data length that the network architecture chip on the chip outputs exceeds the threshold value;

PL DDR controller for managing and controlling the data read/write operations of the PL DDR;

MM2S PL, according to the instruction of the CPU configuration module, as the data transmission direction data channel arbitration module to send the write request, after establishing the data transmission channel with the data receiver, read the data from PL DDR through PL DDR controller to transmit;

s2MM PL, according to the instruction of the CPU configuration module, sends the read request as the data receiving direction data channel arbitration module, and after establishing the data transmission channel with the data sender, writes the data into PL DDR through PL DDR controller.

Further, the small-sized data processing module includes:

The Bram is used for caching data with the data length which is output by the decompressed network-on-chip architecture chip and does not exceed a threshold value;

and the Read Result sends a write request to the data channel arbitration module according to the instruction of the CPU configuration module, and reads data stored in the Bram for transmission after establishing a data transmission channel with a data receiver.

Further, the network interface information packet message field transmitted in the system comprises node address, type, storage unit address, length and command;

node address, which represents the address of a certain destination node of the network-on-chip architecture chip;

The type is the type of the data packet, and the type is three types of data, control and synchronization;

Memory cell address, which is the address of the memory cell in a node;

length is the size of the information packet of the network interface;

And the command represents the command content carried by the network interface information packet.

Further, the data sender and the data receiver are determined by the central processing unit module according to the data transmission direction, the data type and the data length.

One or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:

the invention provides a DMA control system suitable for a chip with a network-on-chip architecture, which improves the scheduling and management capacity of data by optimizing a data transmission channel and a data caching strategy, can realize high-efficiency data interaction between the chip with the network-on-chip architecture and an FPGA chip, and greatly improves the overall efficiency of the system.

Drawings

FIG. 1 is a hierarchical diagram of a DMA control system architecture according to an embodiment of the present invention;

FIG. 2 is a block diagram of a DMA control system according to an embodiment of the present invention;

Fig. 3 is a message format of a network interface packet of a network architecture chip on a chip according to an embodiment of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the drawings and detailed embodiments, and before the technical solutions of the embodiments of the present invention are described in detail, the terms and terms involved will be explained, and in the present specification, the components with the same names or the same reference numerals represent similar or identical structures, and are only limited for illustrative purposes.

Some terms in the present invention are explained as follows:

ARM is totally called ADVANCED RISC MACHINE and is a processor architecture, and the ARM architecture adopts a concise and efficient instruction set to execute and aims to improve the performance and the efficiency of the processor.

FPGA-collectively referred to as Field Programmable GATE ARRAY, field programmable gate array, unlike fixed function integrated circuits, allows a user to program to configure their internal logic gates and wiring to implement a specific digital circuit function.

DMA is totally called Direct Memory Access, namely direct memory access, namely, the access to the memory can be completed under the condition of not being interfered by CPU, and the data transmission rate and the system efficiency are improved.

The PS end is called Processing System, namely the processor system end, which is the part of the SOC related to the ARM core processor and is used for processing conventional software calculation tasks and peripheral interaction.

And the PL end is totally called Programmable Logic, namely a programmable logic end comprises a programmable logic unit and programmable input and output resources, and the PL end and the PS end work cooperatively to provide flexibility and reconfigurability for the system.

The API library, the generic Application Programming Interface library, is a collection of predefined functions and routines, and is designed to provide a standardized interface for the developer to easily integrate existing functions without having to go deep into the underlying implementation details.

DDR, which is commonly referred to as Double Data Rate, is a memory technology for increasing the Data Rate of a memory module, and herein, DDR refers to a memory using this technology.

The invention provides a DMA control system suitable for a network-on-chip architecture chip, which is constructed based on a chip integrated with an FPGA and an ARM core processor.

The DMA control system may be divided into four layers according to a hierarchical structure of a system architecture, as shown in fig. 1. The hardware system comprises a hardware system, a hardware device, a control module, a kernel driving layer, a hardware device, a hardware system register, a memory allocation map, a hardware system register configuration, an interrupt system and an exception handling system, wherein the uppermost layer is a user application layer and is responsible for main functions and logics required by a user, the second layer is a client driving layer and provides an API library for the user application layer to call, the control module is mainly divided into two aspects, one control module is used for controlling the execution of the hardware system by transmitting control parameters, the other control module is used for transmitting data required to be processed into the hardware system, the hardware system realizes corresponding functions, the third layer is a kernel driving layer and is a main logic layer of driving hardware, the hardware device is used for realizing the registration, the memory allocation map, the hardware system register configuration, the interrupt system and the exception handling system, the hardware feedback information is monitored and processed, and the like, driving and the control of the bottom hardware is generally not required to be modified except for modifying the logic of the bottom FPGA end. Of the four layers, only the user application layer and the client driver layer are visible to the user.

In order to realize the driving and control of each hardware module, the invention provides a set of configurable, customizable and extensible software system API library as a software part, which comprises a control module and a data transmission module, wherein the two software modules can be selectively called through an upper application program to realize corresponding functions.

The control driving module is used for sending a network interface information packet and acquiring the state of bottom hardware, such as initializing the state of a network architecture chip on a chip, configuring parameters and execution flow of tasks, starting the chip to execute the tasks, acquiring the execution states of different tasks and the like.

The data transmission driving module is used for transmitting data, such as data to be processed to the network-on-chip architecture chip.

DMA control system module

As shown in fig. 2, the DMA control system is divided into the following modules according to the module functions:

1. The central processing unit module, i.e. ARM in fig. 2, is used as a control center of the whole system and is responsible for executing programs, managing system resources and controlling the work of other modules. When reading or transmitting data to the network-on-chip architecture chip, the central processing unit module makes the data sender and the data receiver match by transmitting an instruction to the central processing unit configuration module, establishes a data transmission channel, and judges whether the data reading is completed or not according to the interrupt signal of the interrupt management module. The data sender and the data receiver are specifically determined by the central processing unit module according to the data transmission direction, the data type and the data length.

2. The central processing unit configuration module, namely Config in FIG. 2, is used for configuring parameters of the PL end register, and sends instructions through the ARM core processor to realize control and information interaction with the PL end assignment module.

3. The interrupt management module, IRQ MANAGE in fig. 2, is configured to manage the interrupt sent from the PL end to the central processing unit module, so that the ARM core processor can grasp the working states of the modules.

4. The data channel arbitration module, namely Connect in fig. 2, is configured to match a read data request of the data receiver with a write data request of the data sender, so that the data sender and the data receiver establish a data transmission channel.

And the PS end data management module is used for storing data required by the operation of the network-on-chip architecture chip in the DDR of the PS end and controlling the read-write operation of the data. The PS end data management module comprises the following submodules:

PSDDR DDR connected to PS end, which is used for storing data.

PSDDR controller the data read-write operation for managing and controlling PSDDR specifically comprises providing a standard interface of PS DDR, optimizing PSDDR memory performance through reasonable data read-write strategy, improving data read-write speed, reducing delay and error processing.

And the MM2S PS is a logic module for reading data from PSDDR, and the logic module is used for sending a write request to the data channel arbitration module as a data sending direction according to an instruction of the CPU configuration module, and reading data from PSDDR through PSDDR controller for transmission after establishing a data transmission channel with a data receiving party.

And S2MM PS, namely writing data into the DDR of the PS end, wherein the logic module is used as a data receiving direction data channel arbitration module to send a read request according to the instruction of the CPU configuration module, and after establishing a data transmission channel with a data sender, the logic module writes data into PSDDR through PSDDR controller.

And the PL end data management module is used for storing a large amount of data, namely, the output data is stored into DDR of the PL end and the read-write operation of the DDR is controlled under the condition that the data length output by the network-on-chip architecture chip exceeds a threshold value. The PL terminal data management module comprises the following submodules:

PL DDR, DDR connected to PL end, is used to store great amount of data output by network on chip.

PL DDR controller the data read-write operation for managing and controlling the PL DDR specifically comprises providing a standard interface of the PL DDR, optimizing the performance of the PL DDR memory through a reasonable data read-write strategy, improving the speed of data read-write, reducing delay and carrying out error processing.

And the MM2S PL is used for reading data from the PL DDR, sending a write request to the data channel arbitration module as a data sending direction according to an instruction of the central processing unit configuration module, establishing a data transmission channel with a data receiving party, and reading the data from the PL DDR through PL DDR controller for transmission.

And S2MM PL, namely a logic module for writing data into the PL DDR, wherein the logic module is used as a data receiving direction data channel arbitration module for sending a read request according to an instruction of a central processing unit configuration module, and after a data transmission channel is established with a data sender, the logic module writes data into the PL DDR through PL DDR controller.

7. The network-on-chip architecture chip writing module, i.e. Req Data in fig. 2, is configured to send a Data packet and a network interface packet to the network-on-chip architecture chip. And the Req Data is used as a Data receiving direction Data channel arbitration module to send a read request according to an instruction of the CPU configuration module, and after establishing a Data transmission channel with a Data sender, the Req Data writes Data into the network architecture chip on chip, wherein the type of the written Data comprises a Data packet and a network interface information packet.

8. The on-chip network architecture chip output Data unpacking module, that is, the Resp Data in fig. 2, is used for receiving the Data packet or the network interface information packet output by the on-chip network architecture chip, unpacking and then shunting.

9. The small data processing module is used for storing and processing a small amount of data, namely, when the length of the data output by the network architecture chip on the chip does not exceed a threshold value, the data can be cached into the Bram first, and the small data processing module comprises the following submodules:

And the Bram is used for caching the data with the data length which is output by the decompressed network-on-chip architecture chip and does not exceed a threshold value.

And the Read Result is used for sending a write request to the data channel arbitration module as a data sending direction according to the instruction of the CPU configuration module, and reading data stored in the Bram for transmission after establishing a data transmission channel with a data receiving party.

DMA control system workflow

The specific workflow of the DMA control system provided by the present invention is explained with reference to fig. 2 as follows:

The ARM core processor firstly starts a DMA read Data function in a Data transmission drive to transmit a Data packet from PSDDR to a network-on-chip architecture chip, and the steps are that the ARM core processor configures a read Data instruction containing read PSDDR head address and burst length information to a Config module through an S_ AXIL bus, the Config module outputs the read Data instruction sent by ARM to an MM2S PS module, the MM2S PS module reads PSDDR Data according to the instruction through PSDDR controller, the ARM core processor configures an MM2S PS module and a Req Data module through the Config module, the MM2S PS module is used as a Data sender to generate a write request, and the Req Data module is used as a Data receiver to generate a read request. The Connect module matches the read request of the Data receiver with the write request of the Data sender, the write request of the MM2S PS module is matched with the read request of the Req Data module, the MM2S PS module and the Req Data module establish a Data transmission channel, the Data packet is written into the network architecture chip on chip through the Req Data module, and after the Data packet is completely written into the network architecture chip on chip, the IRQ MANAGE interrupt management module sends an interrupt vector to the ARM core processor to indicate that the DMA Data reading process is completed.

The ARM core processor also needs to start a control driver to transmit a network interface information packet into the network architecture chip on a chip, wherein the message format of the network interface information packet is shown in figure 3, and the network interface information packet consists of five parts, namely a node address, a type, a storage unit address, a length and a command.

The node address is an address of a certain destination node of the network-on-chip architecture chip, and the network-on-chip architecture chip consists of a plurality of nodes, and each node corresponds to one address.

The type is data, control (ctrl) and synchronization (sync), for data type data packet, the network-on-chip architecture chip converts the data packet into multi-segment packet for transmission, and for sync and ctrl type data packet, the network-on-chip architecture chip converts the data packet into single-segment packet for transmission.

Memory cell addresses, which are addresses representing memory cells in a certain node, and a plurality of memory cells are arranged in each node, and each memory cell corresponds to one address.

Length is the unit byte representing the size of the network interface packet.

Commands representing the content of commands carried by the network interface packet, such as start commands, stop commands, read commands, write commands, refresh commands, etc.

The network interface information packet format is determined according to the network architecture chip on chip, and the DMA system can generate different network interface information packets by changing the control drive of the ARM core processor so as to meet the requirements of the network architecture chip on chip.

After the network-on-chip architecture chip receives the data packet and the network interface packet, the ARM core processor outputs some data packets and network interface packets, and the ARM core processor starts a DMA data writing function in the data transmission drive to transmit data from the network-on-chip architecture chip to PSDDR or PL DDR. The Data are unpacked by a Resp Data module, and the Resp Data module selects different paths to store the Data according to the size of the returned Data packet. The specific cases are as follows:

When the returned data length does not exceed the threshold value, the returned data is cached in the Bram module, then the ARM core processor configures a Read Result module and an S2MM PS module through the Config module, the Read Result module is used as a data sender to generate a write request, the S2MM PS module is used as a data receiver to generate a Read request, after the Connect module is matched with the write request of the Read Result module and the Read request of the S2MM PS module, the Read Result module and the S2MM PS module can establish a data transmission channel, the Read Result module reads the data stored in the Bram module and transmits the data to the S2MM PS module, the S2MM PS module writes the data into the PSDDR module through PSDDR controller, and the post-processing of the PS end and the like are waited.

When the returned data length exceeds the threshold value, the PL DDR module needs to be increased to store the data, and the data can be directly written into the PL DDR through the S2MM PL module through a high priority channel. When the ARM core processor needs to process data in the PL DDR, the ARM core processor configures an MM2S PL module and an S2MM PS module through a Config module, the MM2S PL module serves as a data sender to generate a write request, the S2MM PS module serves as a data receiver to generate a read request, the Connect module is matched with the write request of the MM2S PL module and the read request of the S2MM PS module, the MM2S PL module and the S2MM PS module can establish a data transmission channel, the MM2S PL module reads data from the PL DDR through PL DDR controller and transmits the data to the S2MM PS module, and the S2MM PS module writes the data into PSDDR through PSDDR controller. Thus, the data in the PL DDR module is transmitted to the PSDDR module, and the post-processing operation of the PS end and the like are waited.

After all the data packets are written into the DDR from the chip of the network-on-chip architecture, the IRQ MANAGE interrupt management module sends an interrupt vector to the ARM core processor, which indicates that the DMA data writing process is completed. The ARM core processor also needs to start control drive to acquire the state of the bottom hardware, such as the working state of the nodes in the network-on-chip architecture chip, and the like.

The above embodiments are merely illustrative of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention, and various modifications and improvements made by those skilled in the art to the technical solution of the present invention should fall within the protection scope defined by the claims of the present invention without departing from the design spirit of the present invention.

Claims

1. A DMA control system for a network-on-chip architecture chip, comprising:

the central processing unit configuration module is used for configuring parameters of the PL end register, receiving an instruction sent by the central processing unit module and realizing control and information interaction with the PL end designated module;

2. The DMA control system of claim 1, wherein the data management module comprises:

the PL end data management module is used for storing the data with the data length exceeding the threshold value output by the network-on-chip architecture chip in the DDR of the PL end and controlling the read-write operation of the data.

3. The DMA control system according to claim 2, wherein the PS-side data management module comprises:

4. The DMA control system of claim 2, wherein the PL-side data management module comprises:

5. A DMA control system adapted for use with a network-on-chip architecture chip as recited in claim 1, wherein said small data processing module comprises:

6. The DMA control system according to claim 1, wherein the network interface packet message field transmitted in the system comprises node address, type, memory location address, length, command;

Memory cell address, which is the address of the memory cell in a node;

length is the size of the information packet of the network interface;

7. The DMA control system according to claim 1, wherein the data sender and the data receiver are determined by a central processing unit module according to a data transmission direction, a data type and a data length.