CN117845296A - Novel integrated circuit process - Google Patents

Abstract

The invention relates to the technical field of gold electroplated layers, in particular to a novel integrated circuit process, which comprises the following steps: determining a significant factor through a pulse experiment; optimizing pulse electroplating parameters according to a reaction curved surface method and a significant factor; according to the optimized pulse plating parameters, the plating time is shortened through multistage pulse plating. The novel integrated circuit process of the invention uses a reaction curved surface method to perform parameter optimization through significant factors, and prepares the gold plating layer with the hardness increased from 81Hv to 88Hv by using the lead-free (thallium-containing) electroplating liquid medicine, thereby improving the hardness of the gold plating layer and expanding the application range on the premise of ensuring the productivity.

Description

New integrated circuit technology

Technical Field

The invention relates to the technical field of gold electroplating layers, in particular to a novel integrated circuit process.

Background technique

Gold bump plating is widely used in the field of driver IC packaging, such as COG (Chip on glass) and COF (Chip on film) packaging, in which the hot pressing process of the package pins is closely related to the hardness of the gold plating layer.

Currently, the industry mainly uses potassium gold cyanide (PGC/Potassium Gold Cyanide) series of solutions for electroplating gold bumps, combined with hardness adjusters containing thallium and lead. The hardness of the coating obtained by the solution containing thallium after annealing is about 50~70 Vickers (Hv), while the hardness of the coating obtained by the solution containing lead after annealing is about 80~100 Vickers (Hv), which are respectively suitable for the hardness required for hot pressing during packaging of different products.

However, the hardness requirements of electroplated gold bumps are getting higher and higher. Many products require a hardness of about 90 Vickers (Hv), while the hardness of the traditional gold plating layer with potassium cyanide solution is only 50~70 Vickers (Hv), which obviously cannot meet the use requirements. Due to the increasing popularity of green environmental awareness, and the fact that some products with more stringent requirements must not contain lead, the use of lead-containing solutions has been greatly restricted. Therefore, a process that can improve the hardness of the gold electroplating layer is urgently needed.

Summary of the invention

The object of the present invention is to provide a novel integrated circuit process to solve the problems raised in the above background technology.

The technical solution of the present invention is: a new integrated circuit process, which specifically includes the following steps:

Through pulse experiments, significant factors are determined;

According to the response surface method and significant factors, the pulse plating parameters were optimized;

According to the optimized pulse plating parameters, the plating time is shortened through multi-stage pulse plating.

Furthermore, the significant factors are determined as follows:

According to a plurality of different sets of pulse parameter data which are relatively set, a pulse waveform diagram corresponding to each set is obtained;

Matching each of the pulse waveform diagrams with an actual appearance picture;

Performing variance analysis on the matching results to determine the actual appearance pictures that are screened out;

The pulse parameter data corresponding to the screened actual appearance picture is compared with the remaining pulse parameter data to determine that the significant factors are the power-off time and the reverse time.

Furthermore, the pulse parameter data in the pulse experiment includes but is not limited to forward time, power-off time, reverse time and reverse current data.

Furthermore, the pulse plating parameters are optimized as follows:

According to the significant factors, multiple groups of different comparison data are set;

Obtain a waveform graph corresponding to a response surface methodology experiment corresponding to each group of the data;

Compare the waveform graph corresponding to the response surface method experiment with the multi-stage electroplating results corresponding to each group of data to determine the comparison result corresponding to the maximum hardness. The comparison result corresponding to the maximum hardness is the optimal result, and the pulse plating parameters corresponding to the optimal result are the optimal pulse plating parameters.

Furthermore, the electroplating time is shortened as follows:

Obtaining the forward time, reverse time, power-off time, forward current and reverse current corresponding to the optimized pulse electroplating parameters;

Determining the DC time and AC time corresponding to the optimized pulse plating parameters according to the forward time, reverse time, power-off time, forward current and reverse current;

The DC time and AC time are gradually shortened, and the shortest electroplating time is determined through the current waveform.

The present invention provides a novel integrated circuit process by improvement, which has the following improvements and advantages compared with the prior art:

The novel integrated circuit process of the present invention uses the response surface method to optimize parameters through significant factors, and uses lead-free (thallium-containing) electroplating solution to produce a gold plating layer with a hardness increased from 81Hv to 88Hv, thereby improving the hardness of the gold plating layer and expanding the scope of application while ensuring production capacity.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be further explained below in conjunction with the accompanying drawings and embodiments:

FIG1 is a schematic diagram of a novel integrated circuit process of the present invention;

FIG2 is a matching comparison diagram between the pulse waveform diagram of the present invention and the actual appearance picture;

FIG3 is a waveform diagram corresponding to each group of data response surface method experiments of the present invention;

FIG4 is a waveform diagram corresponding to the response surface method experiment of the present invention;

FIG. 5 is a waveform diagram corresponding to the response surface method experiment of the present invention after shortening the time.

Detailed ways

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

It should be noted that, in the description of the present invention, the terms "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc. indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

It should be noted that like reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined or described in one drawing, it will not require further detailed discussion and description in the description of the subsequent drawings.

Referring to FIG. 1 , this embodiment provides a novel integrated circuit process, which specifically includes the following steps:

Step S1: Determine the significant factors through pulse experiment. The details are as follows:

Step S1.1: According to the relatively set multiple groups of different pulse parameter data, obtain the pulse waveform diagram corresponding to each group. It is worth noting that the pulse parameter data in the pulse experiment includes but is not limited to forward time, power-off time, reverse time and reverse current data.

Specifically, the multiple groups of pulse parameter data in this embodiment are shown in Table 1 below, specifically:

Table 1

Serial number Reverse current/A Forward time/ms Reverse time/ms Power off time/ms Thickness μm Hardness Hv Roughness μm 1 0.0007 200 50 50 18.01 60.30 6.68 2 0.0007 200 50 200 16.68 90.94 1.45 3 0.0007 1000 50 50 19.41 78.48 4.80 4 0.0007 1000 50 200 22.75 111.12 6.96 5 0.0007 1000 100 50 19.48 93.78 5.48 6 0.0007 200 100 50 18.45 88.36 1.78 7 0.0007 1000 100 200 22.94 82.32 9.89 8 0.0007 200 100 200 16.53 90.34 2.34

Step S1.2: Match each pulse waveform diagram with the actual appearance picture. Referring to FIG2 , FIG2 is a matching comparison diagram between each pulse waveform diagram and the actual appearance picture.

Step S1.3: Perform variance analysis on the matching results to determine the actual appearance pictures that have been screened out.

Step S1.4: Compare the pulse parameter data corresponding to the screened actual appearance picture with the remaining pulse parameter data, and determine that the significant factors are the power-off time and the reverse time. It is worth noting that in the process of pulse experiment, according to the current data, there are four influencing factors, namely: forward time, power-off time, reverse time and reverse current data. The confirmation of the influencing factors has been disclosed in the existing technical data, and will not be repeated in this embodiment.

Specifically, it can be seen from the experimental results in Figure 2 that the coatings in Run 2 and Run 6 are normal, and the coatings corresponding to the remaining other data are all burnt. According to the comparative data in Table 1, the significant factors are the power-off time and the reverse time.

Step S2: According to the response surface method and significant factors, the pulse plating parameters are optimized. The details are as follows:

Step S2.1: According to the significant factors determined in step S1.4, namely, the power-off time and the reverse time, a plurality of different sets of comparison data are set. The specific comparison data are as described in Table 2 below, specifically:

Table 2

Serial number Forward time/s Reverse time/s Power off time/s 1 0.60 0.14 0.16 2 1.00 0.14 0.03 3 0.60 0.03 0.30 4 1.00 0.14 0.30 5 1.00 0.03 0.16 6 1.00 0.25 0.16 7 0.20 0.03 0.16 8 0.60 0.14 0.16 9 0.20 0.14 0.30 10 0.60 0.03 0.03 11 0.20 0.25 0.16 12 0.60 0.25 0.30 13 0.20 0.14 0.03 14 0.60 0.14 0.16 15 0.60 0.25 0.03 16 0.60 0.14 0.16 17 0.60 0.14 0.16

Step S2.2: Obtain a waveform diagram corresponding to the response surface methodology experiment corresponding to each set of data. Referring to FIG3 , FIG3 is a waveform diagram corresponding to the response surface methodology experiment corresponding to each set of data.

Step S2.3: Compare the waveform graph corresponding to the response surface method experiment with the multi-stage electroplating results corresponding to each set of data to determine the comparison result corresponding to the maximum hardness. The comparison result corresponding to the maximum hardness is the optimal result, and the pulse electroplating parameters corresponding to the optimal result are the optimal pulse electroplating parameters.

Step S3: According to the optimized pulse plating parameters, the plating time is shortened by multi-stage pulse plating. The details are as follows:

Step S3.1: Obtain the forward time, reverse time, power-off time, forward current and reverse current corresponding to the optimized pulse plating parameters obtained in step S2.3.

Step S3.2: Determine the DC time and AC time corresponding to the optimized pulse plating parameters according to the forward time, reverse time, power-off time, forward current and reverse current.

Step S3.3: gradually shorten the DC time and AC time, and determine the shortest electroplating time through the current waveform.

In this embodiment, direct current is used as an example for specific explanation. Referring to Figures 4 and 5, Figure 4 shows the time corresponding to the time when the time is not shortened, and Figure 5 shows the time corresponding to the time after the time is shortened. As can be seen from Figure 4, the electroplating time corresponding to the response surface method experiment is 4745s, which is 1375s higher than the normal direct current electroplating time of 3370s, about 41%, and thus cannot meet the actual production capacity demand. However, as can be seen from Figure 5, the optimal time is shortened by 1160s, which is significantly reduced, and the hardness can reach 88.52Hv, so that not only the time is reduced, but also the hardness is improved.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims (4)

1. A novel integrated circuit process, characterized in that it specifically includes the following steps: Through pulse experiments, significant factors are determined; According to the response surface method and significant factors, the pulse plating parameters were optimized; According to the optimized pulse plating parameters, the plating time is shortened through multi-stage pulse plating. 2. The novel integrated circuit process according to claim 1, characterized in that the significant factor is determined as follows: According to a plurality of different sets of pulse parameter data which are relatively set, a pulse waveform diagram corresponding to each set is obtained; Matching each of the pulse waveform diagrams with an actual appearance picture; Performing variance analysis on the matching results to determine the actual appearance pictures that are screened out; The pulse parameter data corresponding to the screened actual appearance picture is compared with the remaining pulse parameter data to determine that the significant factors are the power-off time and the reverse time. 3. The novel integrated circuit process according to claim 1 is characterized in that the pulse plating parameters are optimized as follows: According to the significant factors, multiple groups of different comparison data are set; Obtain a waveform graph corresponding to a response surface methodology experiment corresponding to each group of the data; Compare the waveform graph corresponding to the response surface method experiment with the multi-stage electroplating results corresponding to each group of data to determine the comparison result corresponding to the maximum hardness. The comparison result corresponding to the maximum hardness is the optimal result, and the pulse plating parameters corresponding to the optimal result are the optimal pulse plating parameters. 4. The novel integrated circuit process according to claim 1 is characterized in that the electroplating time is shortened as follows: Obtaining the forward time, reverse time, power-off time, forward current and reverse current corresponding to the optimized pulse electroplating parameters; Determining the DC time and AC time corresponding to the optimized pulse plating parameters according to the forward time, reverse time, power-off time, forward current and reverse current; The DC time and AC time are gradually shortened, and the shortest electroplating time is determined through the current waveform.