CN117832208A - A trench capacitor and a method for forming the same - Google Patents

Abstract

The invention discloses a trench capacitor and a forming method thereof, wherein the trench capacitor is a double-trench capacitor and is provided with a semiconductor substrate, a first trench formed on the surface of the semiconductor substrate, a second trench formed on the surface of the semiconductor substrate, a conductive layer and a dielectric layer which are alternately stacked in the first trench, and a conductive layer and a dielectric layer which are alternately stacked in the second trench; the first grooves and the second grooves are staggered, the second grooves take a first layer structure in the adjacent first grooves as a side wall, and the conducting layers and the dielectric layers in the first grooves are alternately continuous with the conducting layers and the dielectric layers in the second grooves. The space utilization rate is greatly improved, and the capacitance density can be increased to 2 to 3 times of the original capacitance density.

Description

A trench capacitor and a method for forming the same

Technical Field

The present invention relates to the field of semiconductor manufacturing, and in particular to a trench capacitor and a method for forming the same.

Background technique

Terminal products are developing in the direction of high efficiency, low cost, low power consumption and small area. The usage of capacitor components in a single system is increasing, which in turn pushes capacitors towards miniaturization, ultra-thinness and large capacity. At the same time, the application end has higher requirements for the stability and high frequency of capacitors. Compared with multilayer ceramic capacitors, MLCC has problems such as high-frequency performance loss and poor reliability in harsh working conditions. Silicon-based capacitors have higher stability, higher reliability, higher self-resonant frequency, lower ESR and ESL, lower insertion loss and more flexible packaging methods. They are the first choice for high-end capacitor devices in the future. In order to reduce the size of the capacitor, it can be achieved by increasing the capacitance density of the capacitor. The capacitance density refers to the capacitance of the capacitor per unit projected area.

Silicon-based capacitors usually use deep trench structures, high-K dielectric materials, or thinner dielectric layers to achieve high capacitance density. However, the continuous improvement of the material K value is constrained by physical limits, and the thickness of the dielectric layer needs to balance capacitance density and withstand voltage. Therefore, in the context of reducing chip area and chip thickness, further increasing the effective area of capacitors is the direction of future capacitor development.

In a deep trench capacitor structure, the trench sidewalls can be used to attach a conductive layer or a dielectric layer, thereby increasing the effective area of the capacitor. However, when the trench is completely filled, the trench sidewalls only serve as a support for the capacitor and do not contribute to the capacitance value. Therefore, if the trench sidewall area is converted into a capacitor structure, the capacitance density can be further increased.

Summary of the invention

The invention provides a trench capacitor and a method for forming the same.

A trench capacitor, which is a double trench capacitor, comprises a semiconductor substrate, a first trench formed on the surface of the semiconductor substrate, a second trench formed on the surface of the semiconductor substrate, a conductive layer and a dielectric layer alternately stacked in the first trench, and a dielectric layer and a conductive layer alternately stacked in the second trench; the first trench is staggered with the second trench, the second trench uses the first layer structure in the adjacent first trench as a side wall, and the conductive layer and the dielectric layer in the first trench are alternately continuous with the conductive layer and the dielectric layer in the second trench.

The first trench and the second trench have the same depth.

A method for forming a trench capacitor, the method comprising:

1) Providing a semiconductor substrate;

2) forming a barrier layer on the surface of the semiconductor substrate;

3) forming a first trench on the surface of the semiconductor substrate, wherein the first trench is located on both sides of the barrier layer;

4) forming a first barrier layer in the first trench, on the barrier layer and on the surface of the semiconductor substrate, and alternately stacking a conductive layer and a dielectric layer on the first barrier layer n times to form a first stacking structure; in this process, controlling the first layer structure on the surface of the semiconductor substrate to be higher than the barrier layer and the second layer structure to be lower than the barrier layer;

5) forming a polishing buffer layer on the first stacked structure, performing a chemical mechanical polishing process, and stopping at the barrier layer;

6) performing a polysilicon etch-back process and forming an isolation layer on the first stacked structure and the barrier layer;

7) removing the insulating layer and the barrier layer in the second trench region to form a second trench on the surface of the semiconductor substrate;

8) alternately stacking dielectric layers and conductive layers m times on the bottom of the second trench and the insulating layer to form a second stacking structure; in this process, the conductive layers and dielectric layers in the second trench are controlled to alternate continuously with the conductive layers and dielectric layers in the first trench;

9) patterning the conductive layer to expose the conductive contact area;

10) Forming sidewalls and metal silicide;

11) Forming an interlayer dielectric layer and contact plugs.

The first stacking structure closes the first groove; and the second stacking structure closes the second groove.

The technical advantages of the present invention are as follows: the conductive layer and the dielectric layer in the first deep trench and the second deep trench are designed to be alternating and continuous, which greatly improves the space utilization rate, and the capacitance density can be increased to 2 to 3 times of the original, which adapts to the development direction of large-capacity capacitors.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings show only preferred embodiments. Various features in the drawings are not drawn to scale and the sizes of various features may be changed arbitrarily. These are not considered to be limitations of the present invention.

FIG. 1 is a schematic diagram of forming a barrier layer according to an embodiment of the present application.

FIG. 2 is a schematic diagram of forming a first deep trench according to an embodiment of the present application.

FIG. 3 is a schematic diagram of a first deep trench after filling according to an embodiment of the present application.

FIG. 4 is a schematic diagram of an embodiment of the present application after chemical mechanical polishing.

FIG. 5 is a schematic diagram of an embodiment of the present application after an etch-back process.

FIG. 6 is a schematic diagram of forming a second deep trench according to an embodiment of the present application.

FIG. 7 is a schematic diagram of a second deep trench after filling according to an embodiment of the present application.

FIG. 8 is a schematic diagram of a conductive layer after patterning according to an embodiment of the present application.

FIG. 9 is a schematic diagram after forming a contact plug according to an embodiment of the present application.

Detailed ways

In order to make the content and technical advantages of the present invention more clear and understandable, the content of the present invention will be described more clearly and completely in conjunction with the drawings in the embodiments. It should be understood that the present invention is not limited to some specific embodiments, that is, some of the specific embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, general replacements known to those skilled in the art are also included in the protection scope of the present invention.

Figures 1 to 9 are cross-sectional views of a trench capacitor manufacturing process according to a preferred embodiment of the present invention. As shown in the figure, the manufacturing method of the present invention includes the following steps:

1 , a semiconductor substrate 100 is provided, and the semiconductor substrate 100 is made of semiconductor-related materials such as silicon (Si), germanium (Ge), silicon germanium (GeSi), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC), etc. The structure of the semiconductor substrate 100 can be one of single crystal, polycrystalline, and amorphous, and the structure of the semiconductor substrate 100 can have or not have an epitaxial layer.

Preferably, in a specific embodiment of the present application, the semiconductor substrate 100 is a silicon substrate.

In some embodiments, a barrier layer 101 is deposited on the semiconductor substrate 100. The material of the barrier layer 101 is, for example, silicon nitride. The thickness of the barrier layer 101 is between 200 nm and 400 nm. The barrier layer 101 is formed by, for example, plasma enhanced chemical vapor deposition (PECVD). Next, the barrier layer 101 is patterned, including but not limited to photolithography and etching processes, to remove the barrier layer 101 outside the second groove region.

2 , in some embodiments, the first deep trench 102 is continuously formed. Specifically, a photoresist layer is formed, and the thickness of the photoresist layer is between 2 μm and 6 μm. The thickness of the photoresist layer can be adjusted according to the depth requirement of the trench. Generally speaking, as the trench depth becomes shallower, the thickness of the photoresist layer can become thinner, and vice versa. Next, a photolithography process is performed to transfer the pattern of the trench mask to the photoresist layer, and an etching process is performed to form the first deep trench 102 with a high aspect ratio on the semiconductor substrate 100. Finally, ashing or solvent dissolution is used to remove the remaining photoresist layer.

In a specific embodiment of the present application, the etching process preferably uses a BOSCH etching process for deep silicon etching. The BOSCH etching process achieves etching and sidewall passivation by alternately switching etching gas and passivation gas, wherein the etching gas is SF6 and the passivation gas is C4F8. The unique etching process characteristics make the etching depth-to-width ratio of the BOSCH etching process as high as 50: 1. The depth of the first deep trench 102 is between 100nm and 50μm, and the specific depth is set according to the capacitor withstand voltage and capacitance density requirements.

3, in some embodiments, a first barrier layer 104, a first conductive layer 105, a first dielectric layer 106, a second conductive layer 107 and a buffer layer 108 are sequentially deposited on the inner wall of the first deep trench 102 and the surface of the semiconductor substrate 100. The first conductive layer 105, the first dielectric layer 106 and the second conductive layer 107 conductive layer form a capacitor structure, called a plate-insulator-plate structure (PIP, Plate-Insulator-Plate). The combined structure of the capacitor in the present invention is not limited to this, and can be adjusted according to the specific requirements of the capacitance density, such as PIPIP, PIPIPIP, etc.

In some embodiments, the material of the first barrier layer 104 is, for example, silicon nitride or silicon oxide, and the first barrier layer 104 is formed by, for example, atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD). Preferably, the first barrier layer 104 is silicon nitride formed by low pressure chemical vapor deposition, and the thickness of the first barrier layer 104 is between 20 nm and 50 nm.

In some embodiments, the material of the first conductive layer 105 and the second conductive layer 107 is, for example, a conductive material such as doped polysilicon, and the formation method thereof is, for example, low-pressure chemical vapor deposition or physical vapor deposition (PVD). Preferably, the first conductive layer 105 and the second conductive layer 107 are n-type phosphorus-doped polysilicon thin films formed by low-pressure chemical vapor deposition, the reaction gases are silane and phosphine, the growth temperature is between 580 and 630 degrees Celsius, and the phosphorus doping concentration is between 1.5E20 and 3E20cm-3.

In order to further improve the conductivity of the conductive layer, the first conductive layer 105 and the second conductive layer 107 need to be combined with a high temperature annealing process to activate the impurity atoms and improve the crystallinity of the film. Preferably, a rapid annealing process is used, the annealing temperature is between 1000 and 1150 degrees Celsius, and the annealing time is between 10s and 30s.

In some other embodiments, the first conductive layer 105 and the second conductive layer 107 may also be grown at a lower temperature, such as 500 to 530 degrees Celsius, to obtain an amorphous silicon film, and combined with a rapid annealing process to obtain a polysilicon film with a high doping concentration.

The thickness of the first conductive layer 105 and the second conductive layer 107 is adjusted based on the characteristic width of the groove and the stacked layer combination to ensure that the first deep groove 102 can be closed to prevent the liquid in the subsequent process from flowing into the groove 102, thereby preventing the conductive layer or the dielectric layer from being damaged. In addition, the thickness of the second conductive layer 107 is 1.2 to 1.5 times the thickness of the first conductive layer 105 to ensure that the subsequent grinding process has a sufficient process window.

In some embodiments, the material of the first dielectric layer 106 is, for example, a dielectric material such as a nitride, an oxide, and a nitride oxide, such as SiO2, Si3N4, HfO2, Al2O3, ZrO2, La2O3, etc. The structure of the first dielectric layer 106 is, for example, a nitride or oxide single-layer structure, a composite structure of a nitride and an oxide, or a stacked structure of a nitride and an oxide. The formation method of the first dielectric layer 106 is, for example, atomic layer deposition, low-pressure chemical vapor deposition, and physical vapor deposition.

Preferably, the first dielectric layer 106 is a multilayer stacked structure of silicon oxide/silicon nitride/silicon oxide (Oxide-Nitride-Oxide, ONO) formed by low-pressure chemical vapor deposition. The stacked structure of silicon oxide/silicon nitride/silicon oxide combines the stability of silicon oxide and the high dielectric properties of silicon nitride. The capacitor prepared with this stacked structure has the characteristics of low leakage and high density. The thickness of each layer in the stacked structure is adjusted according to the capacitance density and withstand voltage requirements, and the thickness ratio is, for example, 1:1:1, 1:2:1, 1:3:1, etc.

In some embodiments, the material of the buffer layer 108 is, for example, silicon oxide. The buffer layer 108 may be formed by plasma enhanced chemical vapor deposition, etc. The thickness of the buffer layer 108 is between 100 nm and 200 nm. The buffer layer 108 is used as a polishing buffer layer to obtain a smooth surface.

4 , a chemical mechanical polishing (CMP) process is performed, which includes a first stage and a second stage. By adjusting the selectivity of the chemical mechanical polishing and detecting signals of related substances in the polishing liquid, the polishing can be stopped on different materials.

The first stage of the chemical mechanical polishing process is used to polish the raised buffer layer 108 so that the polishing stops above the second conductive layer 107 in the raised area. In this stage, the ratio of the polishing rate of the second conductive layer 107 to the polishing rate of the buffer layer 108 should be controlled at 1.5:1 to 3:1.

The second stage of the chemical mechanical polishing process is used to polish the buffer layer 108 and the second conductive layer 107, and stops above the barrier layer 101. In this stage, the ratio of the polishing rate of the second conductive layer 107 to the polishing rate of the buffer layer 108 should be controlled at 1.2:1 to 1:1, and the ratio of the polishing rate of the second conductive layer 107 to the polishing rate of the barrier layer 101 should be greater than 3:1.

It should be noted that after the chemical mechanical polishing process is performed, the buffer layer 108 should be completely removed, and the thickness of the second conductive layer 107 in the horizontal direction should not be less than the thickness of the first conductive layer 105 .

5 , a polysilicon etch-back process is performed, wherein the etch-back process adopts a wet or dry etching process with a high polysilicon etching selectivity to silicon oxide and silicon nitride, and the etch-back process adopts a blanket etch. After the etch-back process is performed, the height of the first conductive layer 105 and the second conductive layer 107 is 2 nm to 10 nm lower than the height of the first dielectric layer 106, and the height difference ΔH can be adjusted based on the thickness of the dielectric layer to avoid the problem of peeling of the first dielectric layer 106.

6, in some embodiments, the second deep trench 108 is continuously formed. Specifically, an isolation layer 109 is formed, the material of the isolation layer 109 is, for example, silicon nitride, and the method of forming the isolation layer 109 is, for example, low pressure chemical vapor deposition, plasma chemical vapor deposition, atomic layer deposition, etc., and the thickness of the isolation layer 109 is between 200nm and 400nm; then, a photoresist layer is formed, the patterning of the second deep trench 108 is performed, and the photoresist layer in the second deep trench 108 region is removed; then, an etching process is performed, and the etching process is divided into two stages. In the first stage, the isolation layer 109 and the barrier layer 101 are etched away, and in the second stage, a BOSCH etching process is used to perform deep silicon etching to form the second deep trench 108, and the second deep trench 108 has the same depth as the first deep trench 102. Finally, ashing or solvent dissolution is used to remove the residual photoresist layer. .

7 , in some embodiments, a second barrier layer 110 is formed on the surface of the isolation layer 109 and the bottom surface of the second deep trench 108. The second barrier layer 110 is formed by, for example, physical vapor deposition, chemical vapor deposition, etc. The step coverage (the percentage of the ratio of the film thickness on the sidewall of the deep trench to the film thickness on the plane) of the second barrier layer 110 needs to be very small, so that the second barrier layer 110 is only formed on the surface of the isolation layer 109 and the bottom surface of the second deep trench 108, and no or only a small amount of the second barrier layer 110 is formed on the sidewall of the second deep trench 108. The step coverage of the second barrier layer 110 is, for example, less than 20%. The thickness of the second barrier layer 110 on the plane is, for example, 40nm to 100nm.

Furthermore, wet etching is performed to remove the first barrier layer 104 on the sidewall of the second trench 108. Based on the etching rate, the wet etching process can achieve precise etching by controlling the etching time. The wet etching needs to remove the first barrier layer 104 on the sidewall of the second trench 108 on the one hand, and on the other hand, it needs to ensure that the thickness of the second barrier layer 110 is not less than the deposition thickness of the first barrier layer 104.

Furthermore, a second dielectric layer 111 , a third conductive layer 112 , a third dielectric layer 113 and a fourth conductive layer 114 are sequentially deposited on the inner wall of the second deep trench 108 and the surface of the second barrier layer 110 .

Preferably, the second dielectric layer 111 and the third dielectric layer 113 are the same as the first dielectric layer 106 , and are a multi-layer stacked structure of silicon oxide/silicon nitride/silicon oxide (Oxide-Nitride-Oxide, ONO) formed by low pressure chemical vapor deposition.

Preferably, the third conductive layer 112 and the fourth conductive layer 114 are the same as the first conductive layer 105 and the second conductive layer 107, and are n-type phosphorus-doped polysilicon thin films formed by low-pressure chemical vapor deposition, the reaction gases are silane and phosphine, the growth temperature is between 580 and 630 degrees Celsius, and the phosphorus doping concentration is between 1.5E20 and 3E20cm-3. They are also subjected to a rapid annealing process, the annealing temperature is between 1000 and 1150 degrees Celsius, and the annealing time is between 10s and 30s.

8 , in some embodiments, the conductive layer is patterned to expose the conductive contact area. The patterning sequence of the conductive layer is: first patterning the top conductive layer, then patterning the lower conductive layers one by one, and the patterning process includes but is not limited to photolithography, etching, and wet cleaning.

Specifically, the step of patterning the fourth conductive layer 114 includes: forming a photoresist layer, using a photolithography process to retain the photoresist in the conductive contact area of the fourth conductive layer 114, and removing the photoresist in other areas; then, using an etching process to remove the fourth conductive layer 114 and the third dielectric layer 113 in the area not covered by the photoresist, the etching process will over-etch the third conductive layer 112, and the thickness of the over-etching is between 5nm and 15nm to ensure that the third conductive layer 112 in the area not covered by the photoresist is completely exposed; finally, using ashing or solvent dissolution to remove the remaining photoresist layer.

The step of patterning the third conductive layer 112 includes: forming a photoresist layer, using a photolithography process to retain the photoresist in the conductive contact areas of the fourth conductive layer 114 and the third conductive layer 112, and removing the photoresist in other areas; then, using an etching process to remove the third conductive layer 112, the second barrier layer 110 and the insulating layer 109 in the areas not covered by the photoresist, and the etching process will over-etch the second conductive layer 107 to ensure that the third conductive layer 112, the second barrier layer 110 and the insulating layer 109 not covered by the photoresist are completely removed; finally, using ashing or solvent dissolution to remove the remaining photoresist layer.

The steps of patterning the second conductive layer 107 and the first conductive layer 105 are similar to the steps of patterning the fourth conductive layer 114 , and will not be described in detail herein.

Preferably, the etching processes in the patterning of the conductive layer are all reactive ion etching processes.

Optionally, in some embodiments, before each patterning of the conductive layer, an atomic layer deposition method is first used to form a thinner isolation layer on the conductive layer, such as silicon oxide with a thickness of between 5nm and 10nm. The isolation layer is used to isolate the conductive layer from the photoresist layer, thereby facilitating the removal of residual photoresist after the patterning process.

9, in some embodiments, a sidewall spacer 115 is further formed on the sidewall of the conductive layer. Specifically, a dielectric layer is first formed, and the dielectric layer is, for example, a single-layer silicon oxide or silicon nitride structure, or a multi-layer silicon oxide/silicon nitride stack structure, and the dielectric layer is formed by, for example, atomic layer deposition, low-pressure chemical vapor deposition, etc.; then, an anisotropic dry etching process is used to form the sidewall spacer 115 on the sidewall of the conductive layer.

In some embodiments, a metal silicide process is implemented in the conductive region of the conductive layer. Specifically, a dielectric layer 116 is formed, the material of the dielectric layer 116 is, for example, silicon oxide, and the method of forming the dielectric layer 116 is, for example, chemical vapor deposition; then, a patterning process is implemented to expose the conductive contact area, and the patterning process includes but is not limited to photolithography and etching processes; then, a layer of metal is formed by physical vapor deposition, and the material of the metal is, for example, Ti, Co, NiPt, etc.; then, a cap layer TiN is formed by physical vapor deposition; then, a low-temperature rapid annealing process is implemented to form a high-resistance metal silicide; then, a selective wet etching process is implemented to remove the surface TiN and the unreacted metal film; finally, a high-temperature rapid annealing process is implemented to form a low-resistance metal silicide 117, such as TiSi2, CoSi2, NiPtSi, etc.

In some embodiments, an etch stop layer 118 and an inter-layer dielectric layer 119 (ILD) are formed. The material of the etch stop layer 118 is, for example, silicon nitride. The etch stop layer 118 is formed by, for example, chemical vapor deposition. The thickness of the etch stop layer 118 is between 40 nm and 100 nm. The material of the inter-layer dielectric layer 119 is, for example, tetraethyl orthosilicate, fluorine- or carbon-doped silicon oxide. The inter-layer dielectric layer 119 is formed by, for example, high-density plasma chemical vapor deposition (HDP-CVD) or sub-atmospheric pressure chemical vapor deposition (SACVD). The thickness of the inter-layer dielectric layer 119 is between 1 μm and 2 μm. Finally, a chemical mechanical polishing process is performed to thin the inter-layer dielectric layer 119 to about 0.9 μm.

Further, a contact plug 120 is formed. Specifically, a photolithography process and an etching process are performed to form a contact through hole in the etching stop layer 118 and the interlayer dielectric layer 119; then, a metal is filled in the contact through hole, and the material of the metal is, for example, copper, aluminum, tungsten, etc., and the metal is formed by, for example, electroplating, physical vapor deposition, etc. Preferably, a barrier layer of titanium nitride (not shown) and metal tungsten are filled in the contact through hole by physical vapor deposition; then, a chemical mechanical polishing process is performed to remove the barrier layer of titanium nitride and metal tungsten on the surface to form a contact plug 120. The contact plug 120 includes a contact plug 120a connected to the fourth conductive layer 114, a contact plug 120b connected to the third conductive layer 112, a contact plug 120c connected to the second conductive layer 107, and a contact plug 120d connected to the first conductive layer 105.

In summary, the present technical invention forms a second deep trench in the sidewall region of the first deep trench, realizing continuous stacking of conductive plates and dielectric layers in the first deep trench and the second deep trench, greatly improving space utilization, increasing capacitance density to 2 to 3 times of the original, and improving product competitiveness.

It should be noted that in the above-mentioned specific embodiments, the terms used in detailing the specific implementation scheme of the present invention, such as "on...", "below...", "side wall", "inner wall" and other terms describing the orientation or position relationship, only refer to the orientation or position relationship in the drawings, and do not indicate or imply that the device or component must have a specific orientation, or be constructed and operated in a specific orientation. In addition, when describing the implementation scheme of the present invention in detail, in order to clearly represent the structure of the present invention for the convenience of explanation, the structure in the drawings is not drawn according to the general scale, and is partially enlarged, deformed and simplified. Therefore, it should be avoided to be understood as a limitation of the present invention.

Claims (4)

1. A trench capacitor, wherein the trench capacitor is a double trench capacitor, comprising a semiconductor substrate, a first trench formed on the surface of the semiconductor substrate, a second trench formed on the surface of the semiconductor substrate, a conductive layer and a dielectric layer alternately stacked in the first trench, and a dielectric layer and a conductive layer alternately stacked in the second trench; wherein the first trench is staggered with the second trench, the second trench has the first layer structure in the adjacent first trench as a sidewall, and the conductive layer and the dielectric layer in the first trench are alternately continuous with the conductive layer and the dielectric layer in the second trench. 2 . The trench capacitor according to claim 1 , wherein the first trench and the second trench have the same depth. 3. A method for forming a trench capacitor, characterized in that: 1) Providing a semiconductor substrate; 2) forming a barrier layer on the surface of the semiconductor substrate; 3) forming a first trench on the surface of the semiconductor substrate, wherein the first trench is located on both sides of the barrier layer; 4) forming a first barrier layer in the first trench, on the barrier layer and on the surface of the semiconductor substrate, and alternately stacking a conductive layer and a dielectric layer n times on the first barrier layer to form a first stacking structure; in this process, controlling the first layer structure on the surface of the semiconductor substrate to be higher than the barrier layer and the upper second layer structure to be lower than the barrier layer; 5) forming a polishing buffer layer on the first stacked structure, performing a chemical mechanical polishing process, and stopping at the barrier layer; 6) performing a polysilicon etch-back process and forming an isolation layer on the first stacked structure and the barrier layer; 7) removing the insulating layer and the barrier layer in the second trench region to form a second trench on the surface of the semiconductor substrate; 8) alternately stacking dielectric layers and conductive layers m times on the bottom of the second trench and the insulating layer to form a second stacking structure; in this process, the conductive layers and dielectric layers in the second trench are controlled to alternate continuously with the conductive layers and dielectric layers in the first trench; 9) patterning the conductive layer to expose the conductive contact area; 10) Forming sidewalls and metal silicide; 11) Forming an interlayer dielectric layer and contact plugs. 4 . The method for forming a trench capacitor according to claim 3 , wherein the first stacking structure closes the first trench; and the second stacking structure closes the second trench.