CN117831596B - Repairing method of sparse failure unit circuit of memory chip - Google Patents
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Abstract
The invention discloses a method for repairing a sparse failure unit circuit of a memory chip, which belongs to the technical field of chip testing and specifically comprises the following steps: the chip tester obtains the circuit information of the failure unit, distributes a repairing scheme for the failure unit of the specific area, stores the rest sparse failure unit information into a hash table, constructs X-Y and Y-X hash table structures in any area, covers a coverage matrix and an influence degree matrix of X coordinates and Y coordinates, and calculates the influence degree of each coordinate; selecting a coordinate which is repaired preferentially according to the coverage and the influence acting degree, and repairing the coordinate which has the largest coverage and the smallest influence acting degree preferentially if the row and column standby circuits are not used up; if only the row or column standby circuit is used up, directly repairing the corresponding coverage set, repeating the process until the information in the hash table is emptied, and completing chip repair; the invention improves the repairing effect on the sparse failure unit circuit in the memory chip.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a method for repairing a sparse failure unit circuit of a memory chip.
Background
Memory chip testing is primarily directed to memory, including random access memory, flash memory, etc., semiconductor devices used to store and read data or program code. The contents of the test include some performance parameters such as read time, write recovery time, data save time, etc. The purpose of these tests is to ensure that the memory reliably and accurately stores and reads data under a variety of conditions.
Compared with the test of the system-level chip, the memory chip has an extra repairing flow, the tester acquires the failed circuit information of each chip according to the test requirement to form a log file of a failed unit circuit, a repairing analysis program of the tester loads the log file to generate a repairing scheme, and a standby circuit is used for repairing the damaged circuit and mainly comprises two types: a row standby circuit and a column standby circuit, wherein the upper diagram is provided with a group of row standby circuits and two groups of column standby circuits; in the circuit repairing process, if a failure unit circuit exists in a normal circuit, a group of rows or columns are required to be allocated to repair the area, and if the number of standby circuits on each chip cannot repair the area of the damaged circuit on the chip, the chip is removed and does not enter the following process.
The failure unit circuit is divided into a row or column specific repair type failure unit circuit and a sparse failure unit circuit area, and a repair standby circuit allocation scheme aiming at the row or column specific repair type failure unit area is generally a fixed solution due to the standby circuit design. The sparse failure unit circuit can be repaired by using a row standby circuit or a column standby circuit, so that the repairing scheme is flexible and changeable.
Because the sparse failure unit circuit does not need a specific type of standby circuit to repair, the repair scheme is flexible and changeable, the repair schemes for the same sparse failure unit circuit are different, the repair ranges of the circuits of the rows or the columns are inconsistent, the same failure unit circuit can be repaired by the standby circuits of the rows or the columns at the same time, and the number of the used standby circuits is different. Based on the above-mentioned scene, it can be understood that the repair allocation algorithm of the processing failure unit circuit of the testing machine can influence the yield of the memory chip in the test packaging process, and the optimal repair scheme can maximize the economic value of chip production, but because the failure information of chip repair is complex, the solution of program allocation can only reach a relatively better solution.
Disclosure of Invention
The invention aims to provide a method for repairing a sparse failure unit circuit of a memory chip, which solves the following technical problems:
Because the sparse failure unit circuit does not need a specific type of standby circuit to repair, the repair scheme is flexible and changeable, the repair schemes for the same sparse failure unit circuit are different, the repair ranges of the circuits of the rows or the columns are inconsistent, the same failure unit circuit can be repaired by the standby circuits of the rows or the columns at the same time, and the number of the used standby circuits is different. The optimal repairing scheme can maximize the economic value of chip production, but the solution distributed by the program can only reach a relatively better solution due to the complex failure information of chip repairing.
The aim of the invention can be achieved by the following technical scheme:
A method for repairing a sparse failure unit circuit of a memory chip comprises the following steps:
S1: the chip tester runs a test program to obtain the information of the failure unit circuit of the whole memory chip, and firstly, a repairing scheme of the failure unit circuit in a specific area is allocated; storing the rest sparse failure unit information into a hash table data structure, and marking the rest sparse failure unit information as a phi set;
S2: generating an X-Y hash table structure and a Y-X hash table structure in any region;
S3: respectively constructing an X coordinate coverage matrix and a Y coordinate coverage matrix, and taking the number value of failure units corresponding to each X address or Y address as a coverage value;
S4: respectively constructing an X coordinate influence action degree matrix and a Y coordinate influence action degree matrix, acquiring the number k of failure units corresponding to each X address or Y address, adding 1 to the influence action degree if k is more than or equal to 2, and performing cumulative calculation to obtain the influence action degree under any coordinate;
S5: when the row and column standby circuits are not used, a value alpha with the largest coverage and a value gamma with the smallest influence on the action degree in the X coordinate are obtained, and a value beta with the largest coverage and a value delta with the smallest influence on the action degree in the Y coordinate are obtained; if alpha is larger than beta, preferentially repairing X coordinates corresponding to alpha, or preferentially repairing Y coordinates corresponding to beta, and if alpha is equal to beta, preferentially repairing coordinates corresponding to the smallest value in gamma and delta;
S6: when the row standby circuits are used up, acquiring the set size of the Y coverage matrix, and if the set size value is smaller than the number of the column standby circuits, directly repairing the Y coordinate set in the Y coverage; otherwise, the memory chip is not repairable, and the iteration is stopped;
S7: when the column standby circuits are used up, acquiring the set size of the X coverage matrix, and if the set size value is smaller than the number of the row standby circuits, directly repairing an X coordinate set in the X coverage; otherwise, the memory chip is not repairable, and the iteration is stopped;
s8: repeating the steps S1-S7 until all sparse failure unit information in the phi set is emptied, and completing the repair of the memory chip.
As a further scheme of the invention: the sparse failure unit information is phi= { f 1,f2,...,fn},fi=l1,l2,l3,l4, n represents the number of sparse failure unit circuits, fi represents any sparse failure unit circuit information, i epsilon n, and l 1,l2,l3,l4 sequentially represents the area number, IO number, X address and Y address of the failure unit circuits.
As a further scheme of the invention: the process of generating the X-Y hash table structure and the Y-X hash table structure is as follows:
Taking any X address as a key word, wherein the X address corresponds to a set of Y address values of all failure unit circuits and is used as a key value to obtain an X-Y hash table structure;
And taking any Y address as a key, wherein the Y address corresponds to the set of X address values of all the failure unit circuits and is used as a key value, so that a Y-X hash table structure is obtained.
As a further scheme of the invention: each repair is to delete the failure unit information where the repair is successful from the collection and updateValues in the set.
As a further scheme of the invention: the coverage matrix of the X coordinate is ：X={x1,x2,...,xm},Vx={v1,v2,...,vm},xm, which represents the X coordinate of the failure unit, m represents the number of the X coordinate, v m represents the value corresponding to the number of the failure unit under X m;
The coverage matrix for the Y coordinate is: y= { Y 1,y2,...,yn},Vy={v1,v2,...,vn }, n represents the number of coordinates of Y, Y n represents the coordinates of the failed unit Y, and v n represents a value corresponding to the number of failed units under Y n.
As a further scheme of the invention: the influence degree matrix of the X coordinate is ：X0={x1,x2,...,xm},Hx={h1,h2,...,hm},xm, which represents the X coordinate of the failure unit, m represents the number of the X coordinate, and h m represents the influence degree value of the failure unit under the corresponding X m;
the influence degree matrix of the Y coordinate is ：Y0={y1,y2,...,yn},Hy={h1,h2,...,hn}, And (3) indicating the Y coordinates of the failure unit, n indicating the number of the Y coordinates, and h n indicating the influence degree value of the failure unit under the corresponding Y n.
The invention has the beneficial effects that:
The method is applied to the calculation of the repair scheme of the sparse failure unit circuit in the repair process of the memory chip, introduces the concept of influence degree by considering the mutual influence of the row direction and the column direction of the failure unit, avoids repeated repair of the same sparse failure unit circuit by the row standby circuit and the column standby circuit, and can effectively reduce the use amount of the standby circuit, thereby improving the yield in the repair process of the memory chip.
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The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic flow chart of the present invention;
FIG. 2 is a diagram illustrating a failure cell circuit of a single block of a memory chip according to the present invention;
FIG. 3 is an exemplary diagram of a memory chip area redundancy circuit repair map of the present invention;
FIG. 4 is an exemplary diagram of a memory chip area alternate circuit repair map of the present invention;
FIG. 5 is a schematic diagram of a spare circuit repair sparse failure cell circuit according to one embodiment of the present invention;
FIG. 6 is a schematic diagram of a spare circuit repair sparse failure cell circuit according to the second embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-6, a method for repairing a sparse failure unit circuit of a memory chip includes the following steps:
S1: the chip tester runs a test program to obtain the information of the failure unit circuit of the whole memory chip, and firstly, a repairing scheme of the failure unit circuit in a specific area is allocated; storing the rest sparse failure unit information into a hash table data structure, and marking the rest sparse failure unit information as a phi set;
S2: generating an X-Y hash table structure and a Y-X hash table structure in any region;
S3: respectively constructing an X coordinate coverage matrix and a Y coordinate coverage matrix, and taking the number value of failure units corresponding to each X address or Y address as a coverage value;
S4: respectively constructing an X coordinate influence action degree matrix and a Y coordinate influence action degree matrix, acquiring the number k of failure units corresponding to each X address or Y address, adding 1 to the influence action degree if k is more than or equal to 2, and performing cumulative calculation to obtain the influence action degree under any coordinate;
S5: when the row and column standby circuits are not used, a value alpha with the largest coverage and a value gamma with the smallest influence on the action degree in the X coordinate are obtained, and a value beta with the largest coverage and a value delta with the smallest influence on the action degree in the Y coordinate are obtained; if alpha is larger than beta, preferentially repairing X coordinates corresponding to alpha, or preferentially repairing Y coordinates corresponding to beta, and if alpha is equal to beta, preferentially repairing coordinates corresponding to the smallest value in gamma and delta;
S6: when the row standby circuits are used up, acquiring the set size of the Y coverage matrix, and if the set size value is smaller than the number of the column standby circuits, directly repairing the Y coordinate set in the Y coverage; otherwise, the memory chip is not repairable, and the iteration is stopped;
S7: when the column standby circuits are used up, acquiring the set size of the X coverage matrix, and if the set size value is smaller than the number of the row standby circuits, directly repairing an X coordinate set in the X coverage; otherwise, the memory chip is not repairable, and the iteration is stopped;
s8: repeating the steps S1-S7 until all sparse failure unit information in the phi set is emptied, and completing the repair of the memory chip.
Memory chips play a critical role in modern electronic devices, however, the problem of possible failure during use has been a problem that plagues the industry. Aiming at the problem, the invention provides a method for calculating a repairing scheme of a sparse failure unit circuit in the repairing process of a memory chip. The method introduces the concept of influencing the degree of effect on the basis of considering the mutual influence of the row direction and the column direction of the failure unit, thereby avoiding the situation that the spare circuits of the row and the column repeatedly repair the same sparse failure unit circuit.
In the conventional memory chip repair methods, the amount of use of the spare circuit tends to be large because these methods fail to sufficiently consider the interaction between the failed cells and the spare circuit. The excessive use of the standby circuit not only increases the cost in the repair process, but also may aggravate the yield drop of the memory chip. For this reason, the present invention skillfully solves this problem by introducing a concept that affects the degree of action.
The degree of influence is a parameter describing the degree of interaction between the failed cells and the standby circuit. When the standby circuit repair scheme is calculated, whether a certain sparse failure unit circuit needs to be repaired or not can be judged according to the influence degree. If the influence degrees of a plurality of failure units overlap with each other, we can preferentially select the failure unit with larger influence degree to repair, so as to avoid repeatedly repairing the same failure unit.
By the method, the use amount of the standby circuit is effectively reduced, and the yield in the memory chip repairing process is improved. This is certainly a good news to memory chip manufacturers because they can reduce the production cost and increase the product competitiveness on this basis. In addition, the invention can be applied to other types of electronic equipment, and brings a new solution to the field of fault repair.
In a word, the invention provides a method for calculating the repair scheme of the sparse failure unit circuit in the memory chip repair process, and the method effectively reduces the use amount of the standby circuit and improves the yield in the memory chip repair process by introducing the concept of influencing the degree of action. The innovative method is expected to bring revolutionary transformation to the memory chip industry, and simultaneously provides a new idea for the field of fault repair of other electronic equipment.
Referring to fig. 5 and 6, it is assumed that there are two sets of row redundancy circuits and one set of column redundancy circuits:
Firstly, calculating an X coordinate set, wherein corresponding coverage values of 3X, 6X and 9X are respectively 1,3 and 2, and influence acting values are respectively 0,2,2; calculating a Y coordinate set, wherein corresponding coverage values of 5Y, 7Y,9Y and 11Y are respectively 1,2 and 2, and influence action values are respectively 0,1,2,2;
Firstly, if the coverage corresponding to 6X is maximum, a group of row standby circuits are allocated to repair the 6X position, at the moment, the information of the failure circuit is updated to obtain a lower diagram, and the steps are repeated;
Repeating the steps 2-5, calculating an X coordinate set, wherein the corresponding coverage values of 3X and 9X are respectively 1 and 2, and the influence acting degree values are respectively 0 and 0; calculating a Y coordinate set, wherein coverage values corresponding to 5Y,9Y and 11Y are respectively 1,1 and 1, and influence acting degree values are respectively 0,0 and 0;
At this time, if the coverage corresponding to 9X is maximum, a group of row standby circuits is allocated to repair the 9X position, at this time, the information of the failure circuit is updated, only the failure unit circuit of the coordinate (3, 5) is left unrepaired, at this time, a group of column standby circuits is allocated, at this time, the Φ set is empty, iteration is stopped, and the DUT can be repaired.
In another preferred embodiment of the present invention, the sparse failure unit information is Φ= { f 1,f2,...,fn},fi=l1,l2,l3,l4, n represents the number of sparse failure unit circuits, fi represents any sparse failure unit circuit information, i e n, l 1,l2,l3,l4 represents the area number, IO number, X address, Y address of the failure unit circuit in sequence.
In another preferred embodiment of the present invention, the process of generating the X-Y hash table structure and the Y-X hash table structure is:
Taking any X address as a key word, wherein the X address corresponds to a set of Y address values of all failure unit circuits and is used as a key value to obtain an X-Y hash table structure;
And taking any Y address as a key, wherein the Y address corresponds to the set of X address values of all the failure unit circuits and is used as a key value, so that a Y-X hash table structure is obtained.
In another preferred embodiment of the present invention, each repair deletes the failure unit information where the repair is successful from the collection, updatesValues in the set.
In another preferred embodiment of the present invention, a coverage matrix of X coordinates of ：X={x1,x2,...,xm},Vx={v1,v2,...,vm},xm represents the X coordinates of the failed cells, m represents the number of X coordinates, v m represents a value corresponding to the number of failed cells under X m;
The coverage matrix for the Y coordinate is: y= { Y 1,y2,...,yn},Vy={v1,v2,...,vn }, n represents the number of coordinates of Y, Y n represents the coordinates of the failed unit Y, and v n represents a value corresponding to the number of failed units under Y n.
In another preferred embodiment of the present invention, the influence degree matrix of the X coordinate is ：X0={x1,x2,...,xm},Hx={h1,h2,...,hm},xm, where m represents the number of X coordinates, and h m represents the influence degree value of the corresponding X m under which the failure unit exists;
the influence degree matrix of the Y coordinate is ：Y0={y1,y2,...,yn},Hy={h1,h2,...,hn}, And (3) indicating the Y coordinates of the failure unit, n indicating the number of the Y coordinates, and h n indicating the influence degree value of the failure unit under the corresponding Y n.
The foregoing describes one embodiment of the present invention in detail, but the description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications within the scope of the present invention are intended to be covered by the present invention.
Claims (5)
1. The repairing method of the sparse failure unit circuit of the memory chip is characterized by comprising the following steps of:
S1: the chip tester runs a test program to obtain the information of the failure unit circuit of the whole memory chip, and firstly, a repairing scheme of the failure unit circuit in a specific area is allocated; storing the rest sparse failure unit information into a hash table data structure, and marking the rest sparse failure unit information as a phi set;
S2: generating an X-Y hash table structure and a Y-X hash table structure in any region;
The process of generating the X-Y hash table structure and the Y-X hash table structure is as follows:
Taking any X address as a key word, wherein the X address corresponds to a set of Y address values of all failure unit circuits and is used as a key value to obtain an X-Y hash table structure;
Taking any Y address as a key word, wherein the Y address corresponds to a set of X address values of all failure unit circuits and is used as a key value to obtain a Y-X hash table structure;
S3: respectively constructing an X coordinate coverage matrix and a Y coordinate coverage matrix, and taking the number value of failure units corresponding to each X address or Y address as a coverage value;
S4: respectively constructing an X coordinate influence action degree matrix and a Y coordinate influence action degree matrix, acquiring the number k of failure units corresponding to each X address or Y address, adding 1 to the influence action degree if k is more than or equal to 2, and performing cumulative calculation to obtain the influence action degree under any coordinate;
S5: when the row and column standby circuits are not used, a value alpha with the largest coverage and a value gamma with the smallest influence on the action degree in the X coordinate are obtained, and a value beta with the largest coverage and a value delta with the smallest influence on the action degree in the Y coordinate are obtained; if alpha is larger than beta, preferentially repairing X coordinates corresponding to alpha, or preferentially repairing Y coordinates corresponding to beta, and if alpha is equal to beta, preferentially repairing coordinates corresponding to the smallest value in gamma and delta;
S6: when the row standby circuits are used up, acquiring the set size of the Y coverage matrix, and if the set size value is smaller than the number of the column standby circuits, directly repairing the Y coordinate set in the Y coverage; otherwise, the memory chip is not repairable, and the iteration is stopped;
S7: when the column standby circuits are used up, acquiring the set size of the X coverage matrix, and if the set size value is smaller than the number of the row standby circuits, directly repairing an X coordinate set in the X coverage; otherwise, the memory chip is not repairable, and the iteration is stopped;
s8: repeating the steps S1-S7 until all sparse failure unit information in the phi set is emptied, and completing the repair of the memory chip.
2. The method for repairing the sparse failure unit circuit of the memory chip according to claim 1, wherein the sparse failure unit information is Φ= { f 1,f2,...,fn},fi=l1,l2,l3,l4, n represents the number of the sparse failure unit circuits, fi represents any sparse failure unit circuit information, i e n, l 1,l2,l3,l4 sequentially represents the area number, the IO number, the X address and the Y address of the failure unit circuit.
3. The method for repairing sparse failure cell circuit of memory chip according to claim 1, wherein each repair is performed by deleting failure cell information where repair is successful from the set, and updatingValues in the set.
4. The method for repairing the sparse failure unit circuit of the memory chip according to claim 1, wherein a coverage matrix of X coordinates is ：X={x1,x2,...,xm},Vx={v1,v2,...,vm},xm, wherein m represents the number of X coordinates, v m represents a value corresponding to the number of failed units under X m;
The coverage matrix for the Y coordinate is: y= { Y 1,y2,...,yn},Vy={v1,v2,...,vn }, n represents the number of coordinates of Y, Y n represents the coordinates of the failed unit Y, and v n represents a value corresponding to the number of failed units under Y n.
5. The method for repairing the sparse failure unit circuit of the memory chip according to claim 1, wherein an influence degree matrix of an X coordinate is ：X0={x1,x2,...,xm},Hx={h1,h2,...,hm},xm, wherein m represents the number of coordinates of the failure unit X, and h m represents an influence degree value of the failure unit under the corresponding X m;
the influence degree matrix of the Y coordinate is ：Y0={y1,y2,...,yn},Hy={h1,h2,...,hn}, And (3) indicating the Y coordinates of the failure unit, n indicating the number of the Y coordinates, and h n indicating the influence degree value of the failure unit under the corresponding Y n.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7076699B1 (en) * | 2001-09-19 | 2006-07-11 | Lsi Logic Corporation | Method for testing semiconductor devices having built-in self repair (BISR) memory |
| CN111755060A (en) * | 2020-06-22 | 2020-10-09 | 上海华力微电子有限公司 | Failure data recovery circuit and method, nonvolatile memory, and readable storage medium |
| CN113129989A (en) * | 2021-04-20 | 2021-07-16 | 苏州鲲腾智能科技有限公司 | Preparation method of three-dimensional memory failure analysis sample |
| CN115083497A (en) * | 2021-03-12 | 2022-09-20 | 中国科学院微电子研究所 | Failure unit detection and repair method of memory chip |
| CN115798559A (en) * | 2023-02-10 | 2023-03-14 | 长鑫存储技术有限公司 | Failure unit prediction method, device, equipment and storage medium |
| WO2023123919A1 (en) * | 2021-12-29 | 2023-07-06 | 寒武纪行歌(南京)科技有限公司 | Data processing circuit, data processing method, and related product |
| CN117153233A (en) * | 2023-03-03 | 2023-12-01 | 悦芯科技股份有限公司 | Method, device and equipment for generating redundancy repair scheme of memory chip based on genetic algorithm and storage medium |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6928591B2 (en) * | 2002-12-23 | 2005-08-09 | Lsi Logic Corporation | Fault repair controller for redundant memory integrated circuits |
| US8331151B2 (en) * | 2009-12-25 | 2012-12-11 | Samsung Electronics Co., Ltd. | Semiconductor memory including control unit responsive to erase command to determine selection of redundant memory block |
-
2024
- 2024-03-05 CN CN202410245295.2A patent/CN117831596B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7076699B1 (en) * | 2001-09-19 | 2006-07-11 | Lsi Logic Corporation | Method for testing semiconductor devices having built-in self repair (BISR) memory |
| CN111755060A (en) * | 2020-06-22 | 2020-10-09 | 上海华力微电子有限公司 | Failure data recovery circuit and method, nonvolatile memory, and readable storage medium |
| CN115083497A (en) * | 2021-03-12 | 2022-09-20 | 中国科学院微电子研究所 | Failure unit detection and repair method of memory chip |
| CN113129989A (en) * | 2021-04-20 | 2021-07-16 | 苏州鲲腾智能科技有限公司 | Preparation method of three-dimensional memory failure analysis sample |
| WO2023123919A1 (en) * | 2021-12-29 | 2023-07-06 | 寒武纪行歌(南京)科技有限公司 | Data processing circuit, data processing method, and related product |
| CN115798559A (en) * | 2023-02-10 | 2023-03-14 | 长鑫存储技术有限公司 | Failure unit prediction method, device, equipment and storage medium |
| CN117153233A (en) * | 2023-03-03 | 2023-12-01 | 悦芯科技股份有限公司 | Method, device and equipment for generating redundancy repair scheme of memory chip based on genetic algorithm and storage medium |
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