CN117827560A - Chip interface and testing method thereof - Google Patents

Abstract

A chip interface and a testing method thereof are provided, the chip interface includes: an input port for receiving a pseudo random binary PRBS test sequence from an external test path; the test sequence comparison module is used for comparing the PRBS test sequence received by the input port with a standard sequence in the test sequence comparison module and outputting a comparison result; the test sequence generation module is used for generating a PRBS test sequence; and the output port is used for outputting the PRBS test sequence generated by the test sequence generation module to an external test path.

Description

Chip interface and test method thereof

Technical Field

The present invention relates to the field of testing, and in particular to a chip interface and a testing method thereof.

Background technique

In recent years, Moore's Law has gradually slowed down. Although new silicon process technology continues to emerge, its update cycle has been extended a lot. At the same time, the semiconductor industry is also facing other challenges such as cost and computing power. Die technology is to package multiple smaller die into a single die, and achieve the same performance through the combination of multiple small die. These small die can be manufactured using different process nodes, manufactured by different semiconductor companies, provided by different suppliers, and made of different materials (silicon, gallium arsenide, silicon carbide, etc.). Multiple die are integrated together through specific design architecture and advanced packaging technology to achieve complete functions, which can break through the bottleneck of current single chip design. The key to die technology is to interconnect small die through a unified and stable interconnection standard. Therefore, how to perform efficient and stable self-testing on the transmission path provided by this fine interconnection interface has become an important topic.

Summary of the invention

Based on the above problems in the prior art, the present invention provides a chip interface, including:

An input port for receiving a pseudo-random binary PRBS test sequence from an external test path;

A test sequence comparison module, used to compare the PRBS test sequence received by the input port with the standard sequence in the test sequence comparison module, and output a comparison result;

A test sequence generation module, used to generate a PRBS test sequence;

The output port is used to output the PRBS test sequence generated by the test sequence generation module to an external test path.

In one embodiment, the test sequence comparison module and the test sequence generation module both include a specific PRBS sequence generation circuit for generating the PRBS test sequence.

In one embodiment, the output port is further configured to output the PRBS test sequence received from the input port to an external test path.

In one embodiment, the chip interface further comprises:

A receiving data path, for receiving a PRBS test sequence from the input port;

The output data path is used to receive the PRBS test sequence from the receiving data path and output it to an external test path via the output port.

In one embodiment, the test sequence comparison module includes a detection circuit, which includes multiple XOR gates corresponding to multiple channels, each XOR gate includes a first input end for receiving a PRBS test sequence, a second input end for receiving a standard sequence, and an output end for outputting a comparison result.

In one embodiment, the detection circuit further includes:

The OR gate array composed of a plurality of OR gates comprises a plurality of input terminals corresponding to a plurality of channels for receiving comparison results from the plurality of XOR gates, and an output terminal for outputting the comparison results.

In one embodiment, the chip interface further includes a control module, which is used to receive a comparison result from the detection circuit, and adjust and control a corresponding channel based on the comparison result.

In one embodiment, the test sequence comparison module includes a specific PRBS sequence generation circuit, and the test sequence comparison module is configured to:

The PRBS test sequence received by the test sequence comparison module is stored in its register in sequence;

Comparing whether the PRBS test sequence in the register is consistent with a pre-stored comparison sequence;

Initializing the PRBS test sequence in the register as a comparison sequence, and the specific PRBS sequence generation circuit in the test sequence comparison module calculates a standard sequence based on the comparison sequence, the PRBS function and the state machine;

When the next PRBS test sequence data arrives at the test sequence comparison module, the newly received PRBS test sequence is compared with the standard sequence in sequence to obtain a comparison result.

The present invention also provides a test method for the chip interface, comprising:

Transmitting the PRBS test sequence received from the external test path at the input port to the test sequence comparison module;

The test sequence comparison module compares the received PRBS test sequence with the standard sequence in the test sequence comparison module and outputs a comparison result.

In one embodiment, the test sequence comparison module compares the received PRBS test sequence with the standard sequence in the test sequence comparison module, and the step of outputting the comparison result further includes:

The PRBS test sequence received by the test sequence comparison module is stored in its register in sequence;

Comparing whether the PRBS test sequence in the register is consistent with a pre-stored comparison sequence;

Initializing the PRBS test sequence in the register as a comparison sequence, and the specific PRBS sequence generation circuit in the test sequence comparison module calculates a standard sequence based on the comparison sequence, the PRBS function and the state machine;

When the next PRBS test sequence data arrives at the test sequence comparison module, the newly received PRBS test sequence is compared with the standard sequence in sequence to obtain a comparison result.

The chip interface and the test method thereof in the present invention use a random sequence as a test sequence, do not need to test the integrity of the sequence, use a PRBS test sequence to avoid packet header and packet tail errors, have a high fault tolerance rate, and improve accuracy; in the process of generating a PRBS test sequence, the test can be performed at any time; the test method is simpler, does not need to pre-store longer test sequences and standard sequences, saves area, and is flexible in operation, and has no strict requirements on the test sequence.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing a chip interface structure according to an embodiment of the present invention.

FIG. 2A is a schematic diagram showing a proximal pathway loop according to an embodiment of the present invention.

FIG. 2B is a schematic diagram showing a far-end pathway loopback according to an embodiment of the present invention.

FIG. 3A shows a schematic diagram of a single-channel detection circuit according to an embodiment of the present invention.

FIG. 3B shows a schematic diagram of a multi-channel detection circuit according to an embodiment of the present invention.

FIG4 shows a schematic diagram of a PRBS 7 code generation circuit.

FIG5 shows a flow chart of a method for comparing a received PRBS sequence with a standard sequence according to an embodiment of the present invention.

FIG. 6 shows a flow chart of a chip interface self-test method according to an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be noted that the embodiments given in the present invention are only for illustration and do not limit the protection scope of the present invention.

FIG1 shows a schematic diagram of a chip interface structure according to an embodiment of the present invention. In the present invention, the term "chip" is used in its broad definition to include a package (socket), a die, and a chiplet, etc. The chip includes a normal working mode and a self-test mode. During the normal working mode, the chips transmit communication data required for their normal working; during the self-test mode, the chips stop transmitting communication data required for normal working, but transmit data for testing the chip interface. As shown in FIG1, the chip interface structure for self-test includes a first interface 100 located on a first chip and a second interface 200 located on a second chip, which are coupled to each other. The first interface 100 and the second interface 200 are connected through a tested path 1 and a tested path 2. The tested path 1 and the tested path 2 may include N (N is a positive integer) channels, which can transmit N-bit wide data.

The first interface 100 includes a first output data path 102, which is used to output inter-chip communication data during a normal working mode, and the data path can be disabled by a first control module 104 during a self-test mode; a first test sequence generation module 103, which is used to generate a test sequence during the self-test mode; a first output port 101, which is used to output data from the first output data path 102 or the first test sequence generation module 103; a multiplexer 110 is used to receive data from the first output data path 102 and the first test sequence generation module 103, and under the control of the first control module 104, selectively output the data from the first output data path 102 or the first test sequence generation module 103; a first input port 107, used for receiving data from the second output port 201 of the second interface 200 via the N-bit wide tested path 2 and outputting the data to the first receiving data path 105 or the first test sequence comparison module 106; the first receiving data path 105 is used for receiving chip-to-chip communication data during the normal working mode, and the data path can be disabled by the first control module 104; the first test sequence comparison module 106 is used for comparing the test sequence received from the first input port 107 with the standard sequence during the self-test mode, and outputting the comparison result; the first control module 104 is used for controlling the coordinated operation of the modules in the first interface 100. For the sake of clarity, the connection lines between the first control module 104 and the modules are not shown.

In one embodiment, there is a data path (not shown in FIG. 1 ) between the first input port 107 and the first output port 101, and the first control module 104 controls the on and off of the data path. For example, a multiplexer is connected between the first input port 107 and the first output port 101, and the first control module 104 controls the multiplexer to further control the data transmission between the first input port 107 and the first output port 101.

In one embodiment, there is a data path (not shown in FIG. 1 ) between the first output data path 102 and the first receiving data path 105 , and the first control module 104 controls the on and off of the data path. For example, a multiplexer is connected between the first output data path 102 and the first receiving data path 105 , and the first control module 104 controls the multiplexer to further control the data transmission between the first output data path 102 and the first receiving data path 105 .

The second interface 200 includes a second input port 207, which is used to receive data from the first output port 101 via the N-bit wide tested path 1 and output the data to the second receiving data path 205 or the second test sequence comparison module 206; the second receiving data path 205 is used to receive inter-chip communication data during the normal operating mode, and the data path can be disabled by the second control module 204; the second test sequence comparison module 206 is used to compare the test sequence received from the second input port 207 from the first test sequence generation module 103 with the standard sequence during the self-test mode, and output the comparison result. The second output data path 202 is used to output inter-chip communication data during normal working mode, and the data path can be disabled by the second control module 204 during self-test mode; the second test sequence generation module 203 is used to generate a test sequence; the second output port 201 is coupled to the first input port 107, and is used to output data from the second output data path 202 or the second test sequence generation module 203; the multiplexer 210 is used to receive data from the second output data path 202 and the second test sequence generation module 203, and under the control of the second control module 204, selectively outputs the data from the second output data path 202 or the second test sequence generation module 203; the second control module 204 is used to control the coordinated operation of the modules in the second interface 200. For the sake of clarity, the connecting lines between the second control module 204 and the modules are not shown.

In one embodiment, there is a data path (not shown in FIG. 1 ) between the second input port 207 and the second output port 201, and the second control module 204 controls the on and off of the data path. For example, a multiplexer is connected between the second input port 207 and the second output port 201, and the second control module 204 controls the multiplexer to further control the data transmission between the second input port 207 and the second output port 201.

In one embodiment, there is a data path (not shown in FIG. 1 ) between the second output data path 202 and the second receiving data path 205 , and the second control module 204 controls the on and off of the data path. For example, a multiplexer is connected between the second output data path 202 and the second receiving data path 205 , and the second control module 204 controls the multiplexer to control the data transmission between the second output data path 202 and the second receiving data path 205 .

In FIG1 , the first interface 100 further includes a clock module-a first duty cycle correction circuit (DCC) 108 and a first delay lock loop (DLL) 109, and the second interface 200 further includes a clock module-a second DCC 208 and a second DLL 209. The first DCC 108 and the second DLL 209 are used to provide clock calibration between the first interface 100 and the second interface 200, so that the second interface 200 can correctly recover the test sequence. The first DLL 109 and the second DCC 208 are used to provide clock calibration between the first interface 100 and the second interface 200, so that the first interface 100 can correctly recover the test sequence. The structure and application of the DCC and DLL circuits are well known in the art and will not be described in detail here.

When there is a data path between the input port 107, 207 and the output port 101, 201 of the interface 100, 200, and there is also a data path between the receiving data path 105, 205 and the output data path 102, 202, each interface can be tested through two test path loopbacks, namely, the near-end path loopback and the far-end path loopback. The second interface 200 is used as an example for explanation below. FIG2A shows a schematic diagram of a near-end path loopback according to an embodiment of the present invention, wherein components unrelated to the near-end path loopback are omitted. As shown in FIG2A, the second control module 204 controls the data path between the second input port 207 and the second output port 201 to be turned on, and controls the test sequence to be sent directly from the second input port 207 to the second output port 201 to output the test sequence. FIG2B shows a schematic diagram of a far-end path loopback according to an embodiment of the present invention, wherein components unrelated to the far-end path loopback are omitted. As shown in FIG2B , the second control module 204 controls the data path between the second receiving data path 205 and the second output data path 202 to be connected, and controls the multiplexer 210 to output the data of the second output data path 202 to the second output port 201. The second control module 204 controls the test sequence to be sent from the second input port 207 to the second receiving data path 205, and transmitted to the second output port 201 via the second output data path 202 to output the test sequence. The remote path loopback can test whether the data path between the entire chip meets the requirements.

The test sequence comparison module (including the first test sequence comparison module 103 and the second test sequence comparison module 203) is used to compare the received test sequence with the standard sequence during the self-test mode, and output the comparison result. In one embodiment, the test sequence comparison module includes a single-channel detection circuit and/or a multi-channel detection circuit, and the second test sequence comparison module 203 is used as an example for explanation below. FIG3A shows a schematic diagram of a single-channel detection circuit according to an embodiment of the present invention. As shown in FIG3A, the test sequence comparison module is used to test N channels 1-N for transmitting data, and the first channel 1 includes an XOR gate C1, having a first input terminal in1 for receiving a test sequence, a second input terminal in2 for receiving a standard sequence, and an output terminal out for outputting the comparison result to the second control module 204. The second control module 204 adjusts and controls the first channel based on the comparison result. When the test sequence is the same as the standard sequence data, the output of the XOR gate C1 is 0, and when the test sequence is different from the standard sequence data, the output of the XOR gate C1 is 1. In one embodiment, the second control module 204 calculates the bit error rate between the test sequence and the standard sequence, and when the bit error rate exceeds a certain threshold value, the first channel test result is not passed. In one embodiment, when the second control module 204 continuously receives the first number of data 0s, the first channel test result is considered to be passed. When the second control module 204 does not continuously receive the first number of data 0s, the first channel test result is considered to be not passed. When the first channel test result is not passed, the second control module 204 can disable the first channel. In one embodiment, the comparison result can also be output to the first control module 104, and the first control module 104 adjusts and controls the first channel based on the comparison result. The second channel-the Nth channel is similar to the first channel and will not be repeated here.

FIG3B shows a schematic diagram of a multi-channel detection circuit according to an embodiment of the present invention. As shown in FIG3B , the test sequence comparison module is used to test N channels 1-N for transmitting data. The first channel 1 includes an XOR gate C1, which has a first input terminal in1 for receiving a test sequence, a second input terminal in2 for receiving a standard sequence, and an output terminal out for output. The second channel-the Nth channel is similar to the first channel and will not be described in detail here. The multi-channel detection circuit also includes an OR gate array GA, which includes a plurality of OR gates, for receiving output data from N XOR gates C1-CN, and outputting the output data to the second control module 204 after performing an OR operation. The second control module 204 adjusts and controls the N channels based on the comparison result. In one embodiment, the second control module 204 calculates the bit error rate between the test sequence and the standard sequence. When the bit error rate exceeds a certain threshold, the test results of the N channels are not passed. In one embodiment, when the second control module 204 continuously receives the first number of data 0s, the test results of the N channels are considered to be passed. When the second control module 204 does not continuously receive the first number of data 0s, the test results of the N channels are considered to be failed. When the test results of the N channels are not passed, the second control module 204 can disable the N channels. In one embodiment, the comparison result can also be output to the first control module 104, and the first control module 104 adjusts and controls the N channels based on the comparison result.

The first test sequence comparison module 103 and the second test sequence comparison module 203 have the same circuit, which will not be described in detail here. In one embodiment, when the first interface 100 and the second interface 200 establish communication, the first interface 100 informs the second interface 200 to use single-channel or multi-channel detection through a sideband signal. In single-channel detection, N-bit width will have N channels for independent detection.

In one embodiment, the test sequence is a sequence with a special header and tail, and the standard sequence is the same as the test sequence. In one embodiment, the first control module 104 of the first interface 100 can intentionally add at least one bit error in the test sequence, and when the second interface 200 receives the test sequence, it can accurately identify the error by comparing it with the standard sequence, and the test passes. In this case, when the bit error rate between the test sequence and the standard sequence exceeds a certain threshold, the test result is a failure.

In one embodiment, the test sequence is a pseudo-random binary sequence (PRBS sequence). The PRBS sequence has a "random" characteristic. In the PRBS code stream, the binary numbers "0" and "1" appear randomly, but it is different from the real random code. This "random" characteristic is only local, that is, after the code stream generation function and the initial code are determined, "0" and "1" appear randomly within the cycle, but the code streams in each PRBS sequence cycle are exactly the same, so it is called a "pseudo" random code. The PRBS sequence generation circuit is well known in the art. FIG4 shows a schematic diagram of a PRBS 7 code generation circuit, which includes 7 linear feedback shift registers 401-407 and an XOR gate 408, and the PRBS code function is 1+X ⁶ +X ^7. The PRBS code generation principle is well known in the art and will not be repeated here. In this embodiment, a standard sequence can be generated based on the test sequence received by the test sequence comparison module and the PRBS sequence generation circuit, and the received PRBS sequence is compared with the standard sequence to obtain a comparison result. It is only necessary to include the same PRBS sequence generation circuit in the corresponding test sequence generation module 103, 203 and the test sequence comparison module 106, 206, and there is no need to store complex standard sequences.

FIG5 shows a flow chart of a method for comparing a received PRBS test sequence with a standard sequence according to an embodiment of the present invention, which comprises the following steps:

Step 501: The PRBS test sequence received by the test sequence comparison module is stored in the register in sequence, and the number of bits stored is greater than the number of bits in one cycle of the PRBS test sequence.

Step 502: Check whether the PRBS test sequence in the comparison register is consistent with the pre-stored comparison sequence.

The pre-stored comparison sequence is an arbitrary random sequence, so the comparison result is usually inconsistent. This step is used to provide an initialized comparison to obtain a comparison sequence with the same length as the PRBS test sequence in the register.

Step 503: Initialize the PRBS test sequence in the register as a comparison sequence. The PRBS sequence generation circuit in the test sequence comparison module can calculate subsequent PRBS test sequence data, ie, a standard sequence, based on the comparison sequence, the PRBS function and the state machine.

Among them, the test sequence generation module and the test sequence comparison module have the same PRBS sequence generation circuit.

It is a well-known technology in the art that the PRBS sequence generation circuit obtains subsequent PRBS test sequence data based on the comparison sequence, the PRBS function and the state machine calculation, which will not be described in detail here.

Step 504: When the next PRBS test sequence data arrives at the test sequence comparison module, the newly received PRBS test sequence data is compared with the standard sequence data in sequence to obtain a comparison result, and the result is transmitted to the control module.

In one embodiment, when the first number of consecutive data matches, the PRBS test result is considered to be passed. If there is no first number of consecutive data matching, or the detection times out, the PRBS test result is considered to be failed. For example, if 32 consecutive bits of data match, the PRBS test is considered to be passed.

In this method, if the PRBS test sequence initially stored in the register has an error, the calculated PRBS test sequence data will be correspondingly erroneous, and when the newly received PRBS test sequence data is compared with the calculated data in sequence, there is no continuous first number of data matches, and the PRBS test fails. If the test sequence data initially stored in the register is correct, the calculated test sequence data is also correct. If the newly received PRBS test sequence data has an error, it will also result in no continuous first number of data matches, and the PRBS test fails.

In one embodiment, at least one bit error can be intentionally added by artificially configuring the PRBS generation circuit in the test sequence generation module. By comparing the test sequence with the standard sequence, if the error can be accurately identified, the test is considered to have passed. In this embodiment, when the bit error rate between the PRBS test sequence and the standard sequence exceeds a certain threshold, the test result is a failure.

In another embodiment, the same standard sequence as the PRBS test sequence may be generated by the same PRBS sequence generating circuit, and the PRBS test sequence may be compared with the standard sequence.

The advantages of using PRBS sequence testing are that it avoids packet header and packet tail errors, has a higher fault tolerance rate, and improves accuracy; testing can be performed at any time during the process of generating the PRBS sequence; the test method is simpler, there is no need to pre-store longer sequences, it saves area, is more flexible, and has no strict requirements on the sequence.

The following uses a PRBS sequence as an example to specifically illustrate the chip interface self-test method of the present invention. The present invention provides a chip interface self-test method, and FIG6 shows a flow chart of the chip interface self-test method according to an embodiment of the present invention. In conjunction with FIG1 and FIG6, the chip interface self-test method includes the following steps:

Step 601 : confirm that the first interface 100 and the second interface 200 are connected to each other, that is, confirm that the first output port 101 of the first interface 100 is connected to the second input port 207 of the second interface 200 and/or the first input port 107 of the first interface 100 is connected to the second output port 201 of the second interface 200 .

In one embodiment, after receiving an instruction from the outside, the first control module 104 confirms that the first interface 100 is connected to the second interface 200 .

In one embodiment, a ready signal is sent to the second interface 200 via a side signal of the first interface 100, or a ready signal is sent to the first interface 100 via a side signal of the second interface 200, so as to determine that the first interface 100 and the second interface 200 are connected to each other.

In one embodiment, clock and reset information also needs to be confirmed.

Step 602 : Control the first test sequence generation module 103 of the first interface 100 to generate a PRBS test sequence, and send the PRBS test sequence to the first output port 101 of the first interface 100 .

In one embodiment, the first test sequence generation module 103 includes a PRBS sequence generation circuit.

Step 603: After receiving the PRBS test sequence, the second input port 207 of the second interface 200 sends the received PRBS test sequence to the test sequence comparison module, and the test sequence comparison module compares the received PRBS test sequence with the corresponding standard sequence to obtain a comparison result.

The test sequence comparison module includes the same PRBS sequence generation circuit as the first test sequence generation module 103 .

In one embodiment, the test sequence comparison module is a second test sequence comparison module 206, and the second input port 207 sends the received PRBS test sequence to the second test sequence comparison module 206. The second test sequence comparison module 206 compares the received PRBS test sequence with the corresponding standard sequence to obtain a comparison result.

In one embodiment, the test sequence comparison module is the first test sequence comparison module 106, the second input port 207 transmits the received PRBS sequence to the second output port 201 through a proximal path loopback or a distal path loopback, and the second output port 201 transmits the received PRBS sequence to the first test sequence comparison module 106 via the first input port 107 of the first interface 100. The first test sequence comparison module 106 compares the received PRBS test sequence with the corresponding standard sequence to obtain a comparison result.

Step 604: Send the comparison result to the first control module 104 of the first interface 100. The first control module 104 adjusts and controls the test path based on the comparison result to achieve the functions of testing and correction.

In one embodiment, the second test sequence comparison module 206 generates a comparison result, and sends the comparison result to the first control module 104 of the first interface 100 via a sideband signal.

In one embodiment, the first test sequence comparison module 106 generates a comparison result and directly sends the comparison result to the first control module 104 of the first interface 100 .

In one embodiment, the first control module 104 may shut down the problematic channel and enable a redundant channel.

Although the first interface 100 is used as an output port and the second interface 200 is used as an input port in the above embodiment, it is understood by those skilled in the art that, according to application requirements, the first interface 100 may also be used as an input port and the second interface 200 may be used as an output port. It should be understood by those skilled in the art that, in actual applications, multiple chips may also be interconnected and tested simultaneously.

The chip interface and the self-test method thereof in the present invention use a random sequence as a test sequence, and do not require the integrity of the test sequence; in the present invention, both near-end loopback test and far-end loopback test can be used, and single or multiple chip tests can be performed; and the present invention has macroscopic control over the test results, such as feedback of redundant channels, which increases the integrity of the self-test.

Although the present invention has been described through preferred embodiments, the present invention is not limited to the embodiments described herein but includes various changes and modifications that may be made without departing from the scope of the present invention.

Claims (10)

1. A chip interface, comprising:

an input port for receiving a pseudo random binary PRBS test sequence from an external test path;

the test sequence comparison module is used for comparing the PRBS test sequence received by the input port with a standard sequence in the test sequence comparison module and outputting a comparison result;

the test sequence generation module is used for generating a PRBS test sequence;

and the output port is used for outputting the PRBS test sequence generated by the test sequence generation module to an external test path.

2. The chip interface of claim 1, wherein the test sequence comparison module and the test sequence generation module each comprise a particular PRBS sequence generation circuit for generating the PRBS test sequence.

3. The chip interface of claim 1, wherein the output port is further configured to output the PRBS test sequence received from the input port to an external test path.

4. A chip interface according to one of claims 1-3, wherein the chip interface further comprises:

a receive data path for receiving a PRBS test sequence from the input port;

and an output data path for receiving the PRBS test sequence from the receive data path and outputting to an external test path via the output port.

5. The chip interface of claim 1, wherein the test sequence comparison module comprises a detection circuit comprising a plurality of exclusive or gates corresponding to a plurality of lanes, each exclusive or gate comprising a first input for receiving a PRBS test sequence, a second input for receiving a standard sequence, and an output for outputting a comparison result.

6. The chip interface of claim 5, wherein the detection circuit further comprises:

the OR gate array consists of a plurality of OR gates, comprises a plurality of input ends corresponding to a plurality of channels and is used for receiving comparison results from the plurality of the XOR gates, and an output end is used for outputting the comparison results.

7. The chip interface according to claim 5 or 6, wherein the chip interface further comprises a control module for receiving the comparison result from the detection circuit and adjusting and controlling the respective channels based on the comparison result.

8. The chip interface of claim 1, wherein the test sequence comparison module comprises a particular PRBS sequence generation circuit, the test sequence comparison module configured to:

sequentially storing PRBS test sequences received by the test sequence comparison module into a register thereof;

comparing whether the PRBS test sequence in the register is consistent with a prestored comparison sequence;

initializing a PRBS test sequence in the register into a comparison sequence, wherein a specific PRBS sequence generating circuit in the test sequence comparison module calculates a standard sequence based on the comparison sequence, a PRBS function and a state machine;

and when the next PRBS test sequence data arrives at the test sequence comparison module, sequentially comparing the newly received PRBS test sequence with the standard sequence to obtain a comparison result.

9. A test method for the chip interface of any one of claims 1-8, comprising:

transmitting the PRBS test sequence received by the input port from the external test path to a test sequence comparison module;

and the test sequence comparison module compares the received PRBS test sequence with the standard sequence in the test sequence comparison module and outputs a comparison result.

10. The test method of claim 9, wherein the test sequence comparison module compares the received PRBS test sequence with a standard sequence in the test sequence comparison module and outputting a comparison result further comprises:

sequentially storing PRBS test sequences received by the test sequence comparison module into a register thereof;

comparing whether the PRBS test sequence in the register is consistent with a prestored comparison sequence;

initializing a PRBS test sequence in the register into a comparison sequence, wherein a specific PRBS sequence generating circuit in the test sequence comparison module calculates a standard sequence based on the comparison sequence, a PRBS function and a state machine;

and when the next PRBS test sequence data arrives at the test sequence comparison module, sequentially comparing the newly received PRBS test sequence with the standard sequence to obtain a comparison result.