CN117811737B - Data processing method and device and electronic equipment - Google Patents

Abstract

The application is applied to the technical field of data security, and provides a data processing method, a data processing device and electronic equipment, which are used for improving the operation efficiency of a KDF algorithm, so that the data processing efficiency is improved. The method comprises the following steps: the first equipment acquires an abscissa value of any coordinate point on the elliptic curve and an ordinate value of the coordinate point; the first device comprises p processing modules; the first device determines a general iteration value according to the abscissa value and the ordinate value, and inputs the general iteration value into p processing modules; the first equipment generates a parameter set and inputs p first parameters contained in the parameter set into p processing modules; the first device invokes p processing modules and performs the following steps in each processing module: calculating the input first parameter and the general iteration value, and outputting a first sub-result; the first device determines a key result corresponding to the elliptic curve according to the p first sub-results.

Description

Data processing method, device and electronic equipment

Technical Field

The present application relates to the field of data security technology, and in particular to a data processing method, device and electronic device.

Background Art

With the development of informatization and computer technology, network security issues have become a common challenge faced by mankind in the information age. The SM2 elliptic curve public key cryptography algorithm (or SM2 algorithm) is a common public key cryptography algorithm. In cloud computing, network data transmission and other scenarios, data processing equipment can encrypt and decrypt data through the SM2 algorithm, thereby improving the security of data transmission. Among them, the SM2 algorithm includes a key derivation function (KDF) (or KDF algorithm). During the execution of the KDF algorithm used by the SM2 algorithm, the following loop operations need to be implemented through counter control: determine the iteration value, and perform operations based on the parameters corresponding to the iteration value and the counter. Obviously, the computational efficiency under the loop operation in the KDF algorithm is low, which leads to low efficiency in encrypting and decrypting data through the SM2 algorithm.

Summary of the invention

The present application provides a data processing method, device and electronic device for improving the operational efficiency of the KDF algorithm in the SM2 encryption and decryption algorithm, thereby improving data processing efficiency.

In the first aspect, the present application provides a data processing method, which includes: a first device obtains the horizontal coordinate value and the vertical coordinate value of any coordinate point on an elliptic curve; the first device includes p processing modules; p is greater than or equal to 2 and p is a positive integer; the first device determines a universal iteration value based on the horizontal coordinate value and the vertical coordinate value, and inputs the universal iteration value into the p processing modules; the first device generates a parameter set, and inputs the p first parameters contained in the parameter set into the p processing modules; the first device calls p processing modules, and performs the following steps in each processing module: operates on the input first parameter and the universal iteration value, and outputs a first sub-result; wherein the p processing modules perform operations in parallel and each processing module performs different operations; the first device determines the key result corresponding to the elliptic curve based on the p first sub-results; the first device can also encrypt the first plaintext data according to the key result to obtain the first ciphertext data; or, the first device can also decrypt the second ciphertext data according to the key result to obtain the second plaintext data.

Based on the above method, the first device can first calculate the general iteration value, and then perform parallel operations based on the general iteration value and different parameters in the parameter set to obtain multiple first sub-results, thereby determining the key result; there is no need to repeatedly determine the general iteration value, and multiple first sub-results can be obtained through parallel operations, thereby improving the operational efficiency of the KDF algorithm in the SM2 encryption and decryption algorithm, thereby improving data processing efficiency, thereby solving the problem of low efficiency in encrypting and decrypting data using the SM2 algorithm.

In a possible design, the parameter set further includes q second parameters, q is less than or equal to p and q is a positive integer; the process of determining the key result includes: the first device inputs the q second parameters into q processing modules; the first device calls the q processing modules and performs the following steps in each processing module: operates on the input second parameters and the universal iteration value, and outputs a second sub-result; wherein the q processing modules operate in parallel and each processing module performs a different operation; the first device determines the key result according to The key result is determined by using q first sub-results and q second sub-results output by q processing modules; m is the number of parameters included in the parameter set.

With this design, the first device can determine the key result by combining the second parallel results corresponding to the q second parameters, thereby improving the accuracy of the key result.

In one possible design, the process of determining the key result in the aforementioned design includes: the first device obtains a preset key length; the first device concatenates p first sub-results and q second sub-results to obtain a temporary key; the first device intercepts the leftmost part of the bit value of the temporary key according to the preset key length to obtain the key result; the length of the key result is the preset key length.

With this design, the first device can determine that the length of the key result is a preset key length, thereby making encryption and decryption operations more efficient.

In one possible design, the length of the concatenated horizontal and vertical coordinate values is 512 bits.

In one possible design, the first device can also receive single instruction multiple data (SIMD) instructions; the SIMD instructions are used to instruct p processing modules to perform operations in parallel; and/or, the first device can also schedule the p processing modules to p parallel execution threads for processing; and/or, the first device can also perform parallel operations on the p processing modules through a graphics processor (GPU).

With this design, the first device can implement parallel computing in a variety of different ways, thereby improving flexibility.

In a second aspect, the present application further provides a data processing device, which includes a communication module and a processing module, wherein the communication module is used to receive and send data, and the processing module is used to execute the method shown in the first aspect.

In a possible example, the communication module is specifically used to: obtain the horizontal coordinate value and the vertical coordinate value of any coordinate point on the elliptic curve; the data processing device includes p processing modules; p is greater than or equal to 2 and p is a positive integer; the processing module is specifically used to: determine the universal iteration value according to the horizontal coordinate value and the vertical coordinate value, and input the universal iteration value into the p processing modules; the processing module is also used to: generate a parameter set, and input the p first parameters contained in the parameter set into the p processing modules; the processing module is also used to: call p processing modules, and perform the following steps in each of the processing modules: operate on the input first parameter and the universal iteration value, and output a first sub-result; wherein the p processing modules operate in parallel and each processing module performs different operations; the processing module is also used to: determine the key result corresponding to the elliptic curve according to the p first sub-results; the processing module is also used to: encrypt the first plaintext data according to the key result to obtain the first ciphertext data; or, decrypt the second ciphertext data according to the key result to obtain the second plaintext data.

In a possible design, the parameter set further includes q second parameters, q is less than or equal to p and q is a positive integer; the processing module is specifically used to: input the q second parameters into the q processing modules; call the q processing modules, and perform the following steps in each of the processing modules: operate on the input second parameters and the universal iteration value, and output a second sub-result; wherein the q processing modules operate in parallel and each processing module performs a different operation; according to The key result is determined by using q first sub-results and q second sub-results output by q processing modules; m is the number of parameters included in the parameter set.

In one possible design, the processing module is specifically used to: obtain a preset key length through the communication module; concatenate p first sub-results and q second sub-results to obtain a temporary key; according to the preset key length, intercept the leftmost part of the bit value of the temporary key to obtain a key result; the length of the key result is the preset key length.

In one possible design, the length of the concatenated horizontal and vertical coordinate values is 512 bits.

In one possible design, the processing module is also used to: receive single instruction multiple data (SIMD) instructions through the communication module; the SIMD instructions are used to instruct p processing modules to perform operations in parallel; and/or, schedule the p processing modules to p parallel execution threads for processing; and/or, perform parallel operations on the p processing modules through a graphics processor (GPU).

In a third aspect, the present application further provides an electronic device comprising a processor and a memory, wherein the processor is used to implement the steps of the data processing method as described in the first aspect above and any possible design thereof when executing a computer program stored in the memory.

In a fourth aspect, the present application further provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the data processing method as described in the first aspect and any possible design thereof.

In a fifth aspect, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the steps of the data processing method as described in the first aspect and any possible design thereof.

In addition, the technical effects brought about by the second to fifth aspects can be found in the description of the first aspect above and will not be repeated here.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

FIG1 is a schematic diagram of a flow chart of a data encryption method provided in an embodiment of the present application;

FIG2 is a flow chart of a data decryption method provided in an embodiment of the present application;

FIG3 is a schematic diagram of a flow chart of a data processing method provided in an embodiment of the present application;

FIG4a is a diagram showing an example of a data processing flow provided in an embodiment of the present application;

FIG4b is another example diagram of a data processing flow provided in an embodiment of the present application;

FIG4c is another example diagram of a data processing flow provided in an embodiment of the present application;

FIG4d is another example diagram of a data processing flow provided in an embodiment of the present application;

FIG5a is an example diagram of parallel processing provided by an embodiment of the present application;

FIG5b is an example diagram of another parallel processing provided by an embodiment of the present application;

FIG6 is a schematic diagram of a modular structure of a data processing device provided in an embodiment of the present application;

FIG. 7 is a schematic diagram of the structure of another data processing device provided in an embodiment of the present application.

DETAILED DESCRIPTION

In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. The acquisition, storage, use, and processing of data in the technical solution of this application are in compliance with the relevant provisions of national laws and regulations.

The following are some explanations of the symbols designed in this application:

(1) “||” indicates character concatenation. For example, “A||B” means concatenating “A” and “B”; assuming A = “123” and B = “456”, then A||B = “123456”.

(2) Indicates that C is rounded up. For example, Indicates 8; Means 3.

(3) Indicates that D is rounded down. For example, Indicates 7; Means 2.

In the embodiments of the present application, the number of nouns, unless otherwise specified, means "singular noun or plural noun", that is, "one or more". "At least one" means one or more, and "plural" means two or more. "And/or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character "/" generally indicates that the previous and next associated objects are in an "or" relationship. For example, A/B means: A or B. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c means: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c can be single or multiple.

The ordinal numbers such as "first" and "second" mentioned in the embodiments of the present application are used to distinguish multiple objects, and are not used to limit the size, content, order, timing, application scenario, priority or importance of the multiple objects. For example, the first cell and the second cell can be the same cell or different cells, and such names do not indicate the difference in priority, application scenario or importance of the two cells.

In the embodiments of the present application, "when...", "under the circumstances...", and "if...", "then" may represent the same meaning and may be replaced with each other.

The embodiment of the present application provides a possible data processing architecture, which includes a KDF computing device (or computing device), an encryption device, and a decryption device. Among them, the encryption device and the decryption device can be the same device in some scenarios. It should be understood that in a data processing architecture, the computing device, the encryption device, and the decryption device can be integrated into the same device, which is not limited in this application.

In order to improve the operational efficiency of the KDF algorithm and thus improve the data processing efficiency, the embodiment of the present application provides a data processing method, which is applied to a first device. The data processing method in the present application can be applied in the aforementioned data processing architecture, wherein the first device can be a computing device in the aforementioned data processing architecture.

In combination with the aforementioned data processing architecture, taking the SM2 encryption algorithm as an example, the present application embodiment provides a data processing method, which is applied to an encryption device, and the method is used to encrypt plaintext data to be encrypted. As shown in FIG1 , the method specifically includes the following steps:

Step A1: The encryption device generates a random number k through a random number generator, where k is an integer between 1 and n-1, and n is the order of the base point G. The value of n can refer to GB/T 32918.5-2017 "Information Security Technology SM2 Elliptic Curve Public Key Cryptography Algorithm Part 5: Parameter Definition", which is not elaborated in this application.

Step A2: The encryption device calculates the coordinates of the elliptic curve point C ₁ : C ₁ = [k] G = (x ₁ , y ₁ ). The encryption device can also refer to the methods given in 4.2.9 and 4.2.5 of GB/T 32918.1-2016 "Information Security Technology SM2 Elliptic Curve Public Key Cryptography Algorithm Part 1: General Principles" to convert the data type of C ₁ into a bit string.

Step A3: Assume that the user corresponding to the decryption device (or receiver, decryptor) is user B, and the public key of user B is _PB . The encryption device calculates the value of the elliptic curve point S according to the public key of user B: S = [h] _PB . If S is a point at infinity, an error is reported and the system exits; otherwise, step A4 is continued; where h is the cofactor. The value of h can refer to GB/T 32918.5-2017 "Information Security Technology SM2 Elliptic Curve Public Key Cryptography Algorithm Part 5: Parameter Definition", which is not described in detail in this application.

Step A4: The encryption device calculates the value of the elliptic curve point [k] _PB : [k] _PB = ( _x2 , _y2 ). The encryption device can also refer to the methods given in 4.2.6 and 4.2.5 of GB/T 32918.1-2016 "Information Security Technology SM2 Elliptic Curve Public Key Cryptography Algorithm Part 1: General Principles" to convert the data types of the coordinates _x2 and _y2 into bit strings.

Step A5: The encryption device calls the computing device to calculate the value of the key stream t: t = KDF (x ₂ || y ₂ , klen); wherein klen represents the bit length of the plaintext data to be encrypted. If t is a string of all 0 bits, the encryption device returns to step A1; otherwise, the encryption device continues to execute step A6. The KDF function is a key derivation function, and the calculation process of the KDF function can refer to the method given in Section 5.4.3 of GB/T 32918.4-2016 "Information Security Technology SM2 Elliptic Curve Public Key Cryptography Algorithm Part 4: Public Key Cryptography Algorithm".

The processing actions of the computing device will be described in detail later in the text and will not be repeated here.

Step A6: The encryption device calculates the bit string C ₂ according to the plaintext data M to be encrypted: C ₂ =M⊕t.

Step A7: The encryption device calculates the bit string C ₃ : C ₃ =SM3(x ₂ ||M||y ₂ ).

Step A8: The encryption device confirms and outputs the ciphertext C: C=C ₁ || C ₃ || C ₂ , where the ciphertext C is the ciphertext corresponding to the plaintext data M mentioned above.

In combination with the aforementioned data processing architecture, taking the SM2 decryption algorithm as an example, the present application embodiment provides a data processing method, which is applied to a decryption device, and the method is used to decrypt the ciphertext data to be decrypted. As shown in FIG2 , the method specifically includes the following steps:

Step B1: The decryption device determines the bit string C ₁ according to the ciphertext C. Referring to the methods given in 4.2.4 and 4.2.10 of GB/T 32918.1-2016 "Information Security Technology SM2 Elliptic Curve Public Key Cryptography Algorithm Part 1: General Principles", the decryption device converts the data type of C ₁ into the coordinate point on the elliptic curve. The decryption device verifies whether C ₁ satisfies the elliptic curve equation; if not, the decryption device reports an error and exits; otherwise, the decryption device continues to execute step B2.

Step B2: The decryption device calculates the value of the elliptic curve point S: S = [h] C ₁ . If S is a point at infinity, the decryption device reports an error and exits; otherwise, the decryption device continues to execute step B3.

Step B3: Assuming that the user corresponding to the decryption device is user B, and the private key of user B is d _B , the decryption device calculates the value of [d _B ]C1: [d _B ]C1=(x ₂ , y ₂ ). The decryption device can also refer to the methods given in 4.2.6 and 4.2.5 of GB/T32918.1-2016 "Information Security Technology SM2 Elliptic Curve Public Key Cryptography Algorithm Part 1: General Principles" to convert the data types of coordinates x ₂ and y ₂ into bit strings.

Among them, user B's public key _PB corresponds to the private key _dB .

Step B4: The decryption device calls the calculation device to calculate the value of the key stream t: t = KDF ( _x2 || _y2 , klen). If t is an all-0 bit string, the decryption device reports an error and exits; otherwise, the decryption device continues to execute step B5.

The processing actions of the computing device will be described in detail later in the text and will not be repeated here.

Step B5: The decryption device determines the bit string C ₂ according to the ciphertext C. The decryption device calculates the decrypted plaintext data M': M'=C ₂ ⊕t.

Step B6: The decryption device calculates the value of u: u=SM3(x ₂ || M'|| y ₂ ). The decryption device can also determine the bit string C ₃ based on the ciphertext C. The decryption device verifies whether the value of u is the same as the value of C ₃ ; if u≠C ₃ , the decryption device reports an error and exits; otherwise, the decryption device continues to execute step B7.

Step B7: The decryption device outputs the decrypted plaintext data M'.

In combination with the aforementioned data processing architecture, an embodiment of the present application provides a data processing method for executing a KDF algorithm in an encryption operation or a decryption operation, thereby improving the calculation rate of the encryption operation or the decryption operation.

The data processing method provided by the embodiment of the present application is described below in conjunction with the accompanying drawings. FIG3 is a data processing method provided by the embodiment of the present application, which is applied to a first device (such as a computing device). The method may include the following steps:

S301: The first device obtains the horizontal coordinate value and the vertical coordinate value of any coordinate point on the elliptic curve; the first device includes p processing modules; p is greater than or equal to 2 and p is a positive integer.

It is worth mentioning that, in actual application, when p=1, this solution can still be executed, that is, when the first device includes only one processing module, data processing can be achieved by cyclically executing the steps in this method.

Optionally, the length of the bit message block Z obtained by concatenating the horizontal axis value and the vertical axis value is 512 bits.

For example, x ₂ in the aforementioned step A5 and step B4 is the horizontal coordinate value, and y ₂ in the aforementioned step A5 and step B4 is the vertical coordinate value. The length of the bit data string x ₂ || y ₂ is 512 bits.

S302: The first device determines a common iteration value according to the abscissa value and the ordinate value, and inputs the common iteration value into p processing modules.

Optionally, assuming that the universal iteration value is represented by V ⁽¹⁾ ; the first device may determine the universal iteration value V ⁽¹⁾ according to the first preset value V ⁽⁰⁾ , the abscissa value and the ordinate value.

For example, the first device expands the 512-bit bit message block Z to obtain 68 32-bit words, and the expanded bit word set is recorded as E(Z)=( _W0 , _W1 , ..., _W67 ), see Section 5.3.2 of GB/T32905-2016; the first device obtains a first preset value V ⁽⁰⁾ , where V ⁽⁰⁾ is the 256-bit initial value "7380166F4914B2B9172442D7DA8A0600A96F30BC163138AAE38DEE4DB0FB0E4E" (in hexadecimal) defined in Section 4.1 of GB/T32905-2016; the first device performs 64 rounds of iterative compression to obtain a universal iterative value, recorded as V ⁽¹⁾ =F(V ⁽⁰⁾ , ( _W0 , _W1 , ..., _W67) )), see Section 5.3.3 of GB/T32905-2016; that is, V ⁽¹⁾ = F (V ⁽⁰⁾ , E (Z)) = CF (V ⁽⁰⁾ , Z). Among them, the CF function is the compression function described in Section 5.3.1 of GB/T 32905-2016 "Information Security Technology SM3 Cryptographic Hash Algorithm", and V ⁽¹⁾ is the output value of the CF function.

S303: The first device generates a parameter set, and inputs p first parameters included in the parameter set into p processing modules.

Optionally, the first device calls a counter, and the counter generates m positive integers (1 to m); the first device concatenates each of the m positive integers with the second preset value pad, determines m parameters, and thus generates a parameter set. Wherein, pad = 0x80||0x00||blen.

Optionally, assuming that the bit length value output by the SM3 hash algorithm is represented by hlen, the first device may determine the value of m according to the preset key lengths klen and hlen, for example,

Among them, the first device can determine hlen by referring to the bit length of the SM3 hash algorithm output in Section 5.4.3 of GB/T 32918.4-2016 "Information Security Technology SM2 Elliptic Curve Public Key Cryptography Algorithm Part 4: Public Key Encryption Algorithm", for example, hlen is 512.

For example, the first device takes m 64-byte parameters (byte strings): _Yi = ct _i || 0x80 || 0x00 ⁽⁵¹⁾ || blen, i = 1, 2, ..., m; wherein the 64-byte byte string _Y1 =

00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00

00 00 00 00 00 00 00 80 00 00 00 00 00 00 02 20.

The first device generates a parameter set based on the m parameters determined above. Wherein, ct _i represents a byte string representing the big end of i as 4 bytes. For example, when i is 1, the hexadecimal representation of the byte string ct _i is "00000001"; 0x80 represents a specific value of 1 byte; 0x00 ⁽⁵¹⁾ represents a byte string of 51 bytes all of which are 0x00. blen represents a byte string of a specific value of 8 bytes, and its hexadecimal representation is "0000000000000220".

Furthermore, the first device inputs the p first parameters included in the parameter set into p processing modules, ie, stores (Y ₁ , Y ₂ , . . . , Y _p ), so as to save some computing resources in the next round of computing.

S304: The first device calls p processing modules, and executes the following steps in each processing module: operates on the input first parameter and the common iteration value, and outputs a first sub-result; wherein the p processing modules operate in parallel and each processing module performs different operations.

Here, p is also called a parallel index, and the maximum number of times the first device can execute operations (eg, CF functions) in parallel is p.

S305: The first device determines the key result corresponding to the elliptic curve according to the p first sub-results.

It should be understood that when p is greater than or equal to m, operations corresponding to the m parameters in the parameter set can be completed in one round of parallel processing, that is, the p first sub-results include the first sub-results corresponding to the m parameters respectively.

Optionally, the process of the first device obtaining the key result in step S305 may include: the first device obtains a preset key length; the first device concatenates p first sub-results to obtain a temporary key; the first device intercepts the leftmost bit value of the temporary key according to the preset key length to obtain the key result; the length of the key result is the preset key length. The preset key length is represented by klen, for example, the value is less than (2 ³² -1)hlen (where hlen=256 bits represents the hash value length of SM3).

For example, the first device concatenates m first sub-results V ⁽²⁾ ₁ , V ⁽²⁾ ₂ , ..., V ⁽²⁾ _m together to obtain a temporary key: K'=V ⁽²⁾ ₁ ||V ⁽²⁾ ₂ || ... ||V ⁽²⁾ _m ; the first device intercepts the leftmost klen bits of K' as the key result K, that is, K=MSB _klen (K'). The first device can also output the aforementioned key result K. The most significant bit (MSB) function represents taking the bit representing the highest value in binary.

In a possible design, when p is less than m, the first device may repeatedly perform the actions in step S303 and step S304, thereby performing multiple rounds ( round) to obtain m first sub-results; further, when executing step S305, the first device can determine the key result corresponding to the elliptic curve according to the m first sub-results.

Optionally, when p is not divisible by m, in the last round of parallel operation, assuming that the number of first parameters to be processed is less than p, the first device pads the insufficient message blocks with 0. For example, multiple rounds of parallel operation are expressed as: (V ⁽²⁾ _1+j , V ⁽²⁾ _2+j , …, V ⁽²⁾ _p+j )=CF ^(p) (V ⁽¹⁾ , (Y _1+j , Y _2+j , …, Y _p+j )), where if j+p>m, Y _j+p =0.

Optionally, when p is not divisible by m, in the last round of parallel computing, assuming that the number of first parameters to be processed is less than p, the first device calculates the first parameters to be processed one by one in a traditional manner, that is, parallel processing is not performed. The ordinary non-parallel CF compression function is executed sequentially: V ⁽²⁾ _j+1 =CF(V ⁽¹⁾ , Y _j ).

In another possible design, when p is not divisible by m, After step S303 and step S304, the first device obtains The parameter set also includes q second parameters. q is less than p and q is a positive integer; then step S305 includes the following steps:

Step 1: The first device inputs q second parameters into q processing modules.

Step 2: The first device calls q processing modules, and executes the following steps in each processing module: operates on the input second parameter and the common iteration value, and outputs a second sub-result; wherein the q processing modules operate in parallel and each processing module performs different operations.

Step 3: First device based The key result is determined based on the q first sub-results and the q second sub-results output by the q processing modules.

Optionally, the process of the first device determining the key result in step 3 may include: the first device obtains a preset key length; the first device The first sub-results and q second sub-results are concatenated to obtain a temporary key; the first device intercepts the leftmost bit value of the temporary key according to the preset key length to obtain a key result; the length of the key result is the preset key length.

Optionally, after executing step S305, the first device may also encrypt the first plaintext data according to the key result to obtain the first ciphertext data. For example, the first device may serve as an encryption device to execute the process of confirming and outputting the ciphertext C in the aforementioned step A8.

Optionally, after executing step S305, the first device may also decrypt the second ciphertext data according to the key result to obtain the second plaintext data. For example, the first device may serve as a decryption device to execute the process of outputting the decrypted plaintext data in the aforementioned step B7.

In the encryption and decryption calculation process of the traditional SM2 algorithm, the calculations in the aforementioned steps A5 and B4 are the operations of the KDF algorithm, which need to be executed in sequence in a loop in the encryption device (or decryption device), that is, m calculations are performed. The method specifically includes the following steps:

Step C1: The encryption device (or decryption device) initializes the 32-bit counter ct=0x00000001;

C2: for i from 1 to implement:

C2-1: Calculate _Hi = SM3(Z||ct);

C2-2: add 1 to the 32-bit counter ct, that is, ct = ct + 1;

C3: concatenate m hash strings into K'=H ₁ || H ₂ || ... || H _m ;

C4: intercept the leftmost klen bits of K' as K output, that is, output K = MSB _klen (K').

FIG4a is an example diagram of an SM2 data processing flow provided by an embodiment of the present application. In which, the first device calculates the first parameter to be processed one by one, that is, does not perform parallel processing. It should be understood that the data processing flow can be understood as the data processing flow when p=1, that is, the traditional processing method of the SM2 encryption and decryption algorithm. The aforementioned data processing flow includes the following steps:

Step 4a-1: Obtain parameter 1 (i.e., bit message block Z) and parameter 2 (i.e., any parameter in the parameter set), wherein parameter 1 is the horizontal coordinate value and the vertical coordinate value of any coordinate point on the elliptic curve in the aforementioned step S301; parameter 2 is the first parameter in the parameter set in the aforementioned step S303.

Step 4a-2: Execute operations A1 and A2 according to parameter 1 to obtain an iterative value.

Step 4a-3: Perform operations B1 and B2 according to parameter 2 and the aforementioned iteration value to obtain the subkey.

Step 4a-4: After repeatedly executing multiple rounds of the aforementioned steps 4a-1 to 4a-3, a key result K is determined based on multiple subkeys.

Obviously, in the encryption and decryption calculation process of the traditional SM2 algorithm, multiple rounds of steps C1 to C2-2 (or steps 4a-1 to 4a-3) need to be repeated, and step C2-1 (or step 4a-2) needs to be repeated multiple times without distinction, resulting in a waste of computing resources and increasing the time cost of the calculation.

FIG4b is an example diagram of an SM2 data processing flow provided by an embodiment of the present application. As shown in FIG4b, in combination with the method and design shown in the aforementioned steps S301 to S305, the flow of the data processing method may include the following steps:

Step 4b-1: For i (1 to m), take a 64-byte byte string Yi respectively.

Step 4b-2: Calculate the universal iteration value v ⁽¹⁾ =F(v ⁽⁰⁾ , E(Z))=CF(v ⁽⁰⁾ , Z); Step 4b-2 may refer to the aforementioned step S302 and will not be described in detail here.

Step 4b-3: for j(0, p, 2p, ...), respectively perform the function calculation of p processing modules in parallel; this step 4b-3 can refer to the aforementioned steps S303 to S304, which will not be described in detail here; it should be understood that the m data are divided into group, and to the front The group data executes the aforementioned step 4b-3.

Step 4b-4: When p is not divisible by m, The last group (eg, m') of data to be processed in the group is subjected to function calculation; for example, m' function calculations are performed in parallel; or for another example, function calculations are performed one by one.

Step 4b-5: concatenate the above results obtained by function calculation to obtain a temporary key K'.

Step 4b-6: intercept the leftmost klen bits of K' as the key result K; Step 4b-5 and Step 4b-6 can refer to the aforementioned step S305 and will not be described in detail here.

FIG4c is an example diagram of an SM2 data processing flow provided in an embodiment of the present application. As shown in FIG4c, in combination with the method and design shown in the aforementioned steps S301 to S305, the flow of the data processing method may include the following steps:

Step 4c-1: Obtain parameter 1 (ie, bit message block Z); parameter 1 is the horizontal coordinate value and the vertical coordinate value of any coordinate point on the elliptic curve in the aforementioned step S301.

Step 4c-2: In the first SM3 block processing module, operations A1 and A2 are performed according to parameter 1 and the first preset value V ⁽⁰⁾ to obtain a universal iteration value V ⁽¹⁾ . Step 4c-2 can refer to the aforementioned step S302 and will not be described in detail here.

Step 4c-3: Obtain parameter 2 (ie, parameter set); parameter 2 is any parameter in the parameter set in the aforementioned step S303.

Step 4c-4: For each parameter in the parameter set (i ₃₂ , for example: 1 ₃₂ , 2 ₃₂ , 3 ₃₂ . . . m ₃₂ ), concatenate the second preset value pad, and use the concatenated result (i ₃₂ || pad) for subsequent operations. Steps 4c-3 and 4c-4 may refer to the aforementioned step S303 and will not be described in detail here.

Step 4c-5: In other subsequent SM3 processing modules, perform operations B1 and B2 to obtain operation results (eg, V ⁽²⁾ ₁ , V ⁽²⁾ _{2 .} . . V ⁽²⁾ _m ). Step 4c-5 may refer to the aforementioned step S304 and will not be described in detail here.

When executing operation B1, since the 64-byte byte string i ₃₂ || pad is predictable data, operation B1 can be pre-calculated; that is, operation B1 is performed in advance for each parameter in the parameter set, and its result is stored. The result consists of 68 4-byte data, so storing the result of one operation B1 only requires 68*4=272 bytes. Based on this, when executing operation B2, multiple operations B2 are processed in parallel.

Step 4c-6: concatenate the above operation results to obtain a temporary key K', and intercept the leftmost klen bits of K' as the key result K. This step 4c-6 can refer to the above step S305 and will not be described in detail here.

FIG4d is an example diagram of a data processing flow provided by an embodiment of the present application. As shown in FIG4d, in combination with the method and design shown in the aforementioned steps S301 to S305, the flow of the data processing method may include the following steps:

Step 4d-1: Obtain parameter 1 (ie, bit message block Z); parameter 1 is the horizontal coordinate value and the vertical coordinate value of any coordinate point on the elliptic curve in the aforementioned step S301.

Step 4d-2: According to parameter 1 and the first preset value V ⁽⁰⁾ , operations A1 and A2 are performed to obtain a universal iteration value V ⁽¹⁾ . Step 4d-2 can refer to the aforementioned step S302 and will not be described in detail here.

Step 4d-3: Obtain parameter 2 (ie, parameter set); parameter 2 is any parameter in the parameter set in the aforementioned step S303.

Step 4d-4: splice each parameter (i ₃₂ , for example: 1 ₃₂ , 2 ₃₂ , 3 ₃₂ ...m ₃₂ ) in the parameter set with the second preset value pad, and input the spliced result (i ₃₂ || pad) into multiple modules for performing operation B1; perform multiple operations B2 according to the result of operation A2 and the results of multiple operations B1. This step 4c-4 can refer to the aforementioned step S304 and will not be described in detail here.

It should be understood that FIG. 4 d only shows one set of parallel solutions, and in actual application, other multiple sets of parallel solutions may be included, and the number of parallel solutions in each set is less than or equal to p.

Step 4d-5: Determine the key result corresponding to the elliptic curve according to the results of the aforementioned multiple operations B2. Step 4c-5 can refer to the aforementioned step S305 and will not be described in detail here.

In a possible design, the first device may satisfy the data processing method of parallel processing (i.e., parallel operation of the CF compression function) in the following manner:

Mode 1: The first device receives a single instruction multiple data (SIMD) instruction; the SIMD instruction is used to instruct p processing modules to perform operations in parallel;

Method 2: The first device schedules p processing modules to p parallel execution threads for processing;

Method three: The first device performs parallel calculations of p processing modules through a graphics processor GPU.

It should be understood that the above three methods can be selected any one or combined, and this application does not limit them.

Figure 5a is an example diagram of a parallel processing (CF compression function) provided by an embodiment of the present application, where (V ⁽ⁱ⁺¹⁾ ₁ , V ^{(i +1)} ₂ , …, V ⁽ⁱ⁺¹⁾ _p ) = CF ^(p) (V ⁽ⁱ⁾ , ( _Y1 , _Y2 , …, _Yp )) represents the parallel execution of p CF compression functions, that is, V ⁽ⁱ⁺¹⁾ _j = CF(V ⁽ⁱ⁾ , _Yj ), j = 1, 2, …, p. Among them, ( _Y1 , _Y2 , …, _Yp ) is a p-bit message block Z (512 bits), and (V ⁽ⁱ⁺¹⁾ ₁ , V ⁽ⁱ⁺¹⁾ ₂ , …, V ^{(i +1)} _p ) is p calculation results, that is, p first sub-results.

As shown in Figure 5b, the first device can pre-store a general iteration value, that is, store a set of bit words after the 512-bit bit message block Z is expanded: E(Z) = ( _W0 , _W1 , ..., _W67 ); in this way, when the first device subsequently simultaneously executes the following p CF compression functions: (V ⁽²⁾ _1+j , V ⁽²⁾ _2+j , ..., V ⁽²⁾ _p+j ) = CF ^(p) (V ⁽¹⁾ , ( _Y1+j , Y2 _+j , ..., Yp _+j )), there is no need to redundantly calculate the values of ( _Y1+j , Y2 _+j , ..., Yp _+j ), which can save computing resources.

Based on the data processing method shown in FIG3 , the present application provides the following embodiments: Assuming that the first device (or workstation) uses an Intel processor that supports the AVX512 instruction set, the SM3 CF compression function implemented in parallel by the AVX512 instruction is selected, and one CPU core can process 16 CF compression functions in parallel, that is, p=16; using megabyte (MB) to gigabyte (GB) level data for testing, the execution efficiency when using the data processing method shown in FIG3 is about 10-16 times that of the traditional implementation method. Obviously, the data processing method shown in the present application can greatly improve the computational efficiency of the KDF algorithm, thereby improving the data processing efficiency.

Based on the same concept as the above-mentioned data processing method, an embodiment of the present application also provides a data processing device for implementing the above-mentioned method performed by the data processing device.

FIG6 is a schematic diagram of a modular structure of a data processing device provided in an embodiment of the present application. Among them, the communication module 601 can be used to receive and send data, and the processing module 602 can be used to execute the data processing method shown in steps S301 to S305. The specific actions and functions performed are not further elaborated here, and the description of the aforementioned method embodiment can be referred to.

FIG. 7 shows a schematic diagram of the structure of a data processing device provided in an embodiment of the present application.

The electronic device in the embodiment of the present application may include a processor 701. The processor 701 is the control center of the data processing device, and various interfaces and lines can be used to connect various parts of the data processing device, by running or executing instructions stored in the memory 702 and calling data stored in the memory 702. Optionally, the processor 701 may include one or more processing units, and the processor 701 may integrate an application processor and a modem processor, wherein the application processor mainly processes operating systems and application programs, etc., and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 701. In some embodiments, the processor 701 and the memory 702 may be implemented on the same chip, and in some embodiments, they may also be implemented separately on independent chips.

Processor 701 may be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and may implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps performed by the first device or the second device disclosed in the embodiments of the present application may be performed directly by a hardware processor, or by a combination of hardware and software modules in the processor.

In an embodiment of the present application, the memory 702 stores instructions that can be executed by at least one processor 701, and the at least one processor 701 can be used to execute the aforementioned steps performed by the first device or the second device by executing the instructions stored in the memory 702.

The memory 702 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 702 may include at least one type of storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory, a random access memory (Random Access Memory, RAM), a static random access memory (Static Random Access Memory, SRAM), a programmable read-only memory (Programmable Read Only Memory, PROM), a read-only memory (Read Only Memory, ROM), an electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), a magnetic memory, a disk, an optical disk, etc. The memory 702 is any other medium that can be used to carry or store a desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The memory 702 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and/or data.

In the embodiment of the present application, the network device may further include a communication interface 703, and the data processing device may transmit data through the communication interface 703. For example, if the data processing device is a server, the communication interface 703 may be used to obtain information of multiple container network interface CNI plug-ins configured by the user.

Optionally, the processing module 602 shown in FIG. 6 may be implemented by the processor 701 (or the processor 701 and the memory 702 ) shown in FIG. 7 , and/or the communication module 601 shown in FIG. 6 may be implemented by the communication interface 703 .

Based on the same inventive concept, the embodiment of the present application further provides a computer-readable storage medium, which may store instructions, and when the instructions are executed on a computer, the computer executes the operation steps provided in the above method embodiment. The computer-readable storage medium may be the memory 702 shown in FIG. 7 .

Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

The present application is described with reference to the flowchart and/or block diagram of the method, device (system), and computer program product according to the present application. It should be understood that each process and/or box in the flowchart and/or block diagram, as well as the combination of the process and/or box in the flowchart and/or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one process or multiple processes in the flowchart and/or one box or multiple boxes in the block diagram.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims (12)

1. A method of data processing, the method comprising:

The method comprises the steps that first equipment obtains an abscissa value of any coordinate point on an elliptic curve and an ordinate value of the coordinate point; the first device comprises p processing modules; p is greater than or equal to 2 and p is a positive integer;

The first device determines a general iteration value according to the abscissa value and the ordinate value, and inputs the general iteration value into the p processing modules;

The first device generates a parameter set and inputs p first parameters contained in the parameter set into the p processing modules;

The first device invokes the p processing modules and performs the following steps in each of the processing modules: calculating the input first parameter and the general iteration value, and outputting a first sub-result; the p processing modules perform operation in parallel, and the operation executed by each processing module is different;

The first device determines a key result corresponding to the elliptic curve according to the p first sub-results;

encrypting the first plaintext data according to the key result to obtain first ciphertext data; or decrypting the second ciphertext data according to the key result to obtain second plaintext data.

2. The method of claim 1, wherein the set of parameters further comprises q second parameters, q is less than or equal to the p and q is a positive integer; the first device determines a key result corresponding to the elliptic curve according to the p first sub-results, including:

the first device inputs the q second parameters into q processing modules;

The first device invokes the q processing modules and performs the following steps in each of the processing modules: calculating the input second parameter and the general iteration value, and outputting a second sub-result; the q processing modules operate in parallel, and the operation executed by each processing module is different;

The first device is according to the The key result is determined by the first sub-results and the q second sub-results output by the q processing modules; m is the number of parameters contained in the parameter set.

3. The method of claim 2, wherein the first device determining the key result from the p first sub-results and q second sub-results output by the q processing modules comprises:

the first device obtains a preset key length;

the first device splices the p first sub-results and the q second sub-results to obtain a temporary key;

The first device intercepts the leftmost part bit value of the temporary key according to the preset key length to obtain the key result; the length of the key result is the preset key length.

4. The method of claim 1, wherein the length of the concatenated abscissa and ordinate values is 512 bits.

5. The method of any one of claims 1-4, wherein the method further comprises:

the first device receives a single instruction multiple data stream SIMD instruction; the SIMD instruction is used for indicating the p processing modules to operate in parallel; and/or the number of the groups of groups,

The first device dispatches the p processing modules to p threads which are executed in parallel for processing; and/or the number of the groups of groups,

And the first equipment performs parallel operation of the p processing modules through an image processor GPU.

6. A data processing apparatus, the apparatus comprising:

the communication module is used for acquiring an abscissa value of any coordinate point on the elliptic curve and an ordinate value of the coordinate point; the data processing device comprises p processing modules; p is greater than or equal to 2 and p is a positive integer;

The processing module is used for determining a general iteration value according to the abscissa value and the ordinate value and inputting the general iteration value into the p processing modules;

The processing module is further configured to: generating a parameter set, and inputting p first parameters contained in the parameter set into the p processing modules;

The processing module is further configured to: calling the p processing modules, and executing the following steps in each processing module: calculating the input first parameter and the general iteration value, and outputting a first sub-result; the p processing modules perform operation in parallel, and the operation executed by each processing module is different;

the processing module is further configured to: determining a key result corresponding to the elliptic curve according to the p first sub-results;

The processing module is further configured to: encrypting the first plaintext data according to the key result to obtain first ciphertext data; or decrypting the second ciphertext data according to the key result to obtain second plaintext data.

7. The apparatus of claim 6, wherein the set of parameters further comprises q second parameters, q is less than or equal to the p and q is a positive integer; the processing module is specifically configured to:

inputting the q second parameters into q processing modules;

Invoking the q processing modules, and executing the following steps in each processing module: calculating the input second parameter and the general iteration value, and outputting a second sub-result; the q processing modules operate in parallel, and the operation executed by each processing module is different;

according to the described The key result is determined by the first sub-results and the q second sub-results output by the q processing modules; m is the number of parameters contained in the parameter set.

8. The apparatus of claim 7, wherein the processing module is specifically configured to:

acquiring a preset key length through the communication module;

Splicing the p first sub-results and the q second sub-results to obtain a temporary key;

According to the preset key length, intercepting the leftmost part bit value of the temporary key to obtain the key result; the length of the key result is the preset key length.

9. The apparatus of claim 6, wherein the length of the concatenated abscissa and ordinate values is 512 bits.

10. The apparatus of any of claims 6-9, wherein the processing module is further to:

Receiving a single instruction multiple data stream SIMD instruction through the communication module; the SIMD instruction is used for indicating the p processing modules to operate in parallel; and/or the number of the groups of groups,

Scheduling the p processing modules to p threads which are executed in parallel for processing; and/or the number of the groups of groups,

And carrying out parallel operation of the p processing modules through an image processor GPU.

11. An electronic device, comprising:

A memory for storing program instructions;

a processor for invoking program instructions stored in the memory and for performing the steps comprised in the method according to any of claims 1-5 in accordance with the obtained program instructions.

12. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program comprising program instructions which, when executed by a computer, cause the computer to perform the method of any of claims 1-5.