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CN117811360A - Capacitor discharge control circuit for flyback converter - Google Patents

Capacitor discharge control circuit for flyback converter Download PDF

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Publication number
CN117811360A
CN117811360A CN202311845510.4A CN202311845510A CN117811360A CN 117811360 A CN117811360 A CN 117811360A CN 202311845510 A CN202311845510 A CN 202311845510A CN 117811360 A CN117811360 A CN 117811360A
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CN
China
Prior art keywords
signal
control
circuit
control circuit
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311845510.4A
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Chinese (zh)
Inventor
缪芳婷
顾冬烈
郑晨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siruipu Microelectronics Technology Shanghai Co ltd
Original Assignee
Siruipu Microelectronics Technology Shanghai Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Siruipu Microelectronics Technology Shanghai Co ltd filed Critical Siruipu Microelectronics Technology Shanghai Co ltd
Priority to CN202311845510.4A priority Critical patent/CN117811360A/en
Publication of CN117811360A publication Critical patent/CN117811360A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H02H11/002—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of inverted polarity or connection; with switching for obtaining correct connection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
    • H02H7/1213—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for DC-DC converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a capacitor discharge control circuit for a flyback converter, which comprises a transformer and a resonance capacitor, wherein the capacitor discharge control circuit is connected with two ends of the resonance capacitor, and comprises: discharge circuit, detection circuit and control circuit. The discharging circuit is connected with the resonance capacitor; the detection circuit is used for generating a first characterization signal and a second characterization signal which are used for characterizing the voltage of the capacitor at two ends; the control circuit is configured to adjust the first control signal based on the first characterization signal and the second characterization signal. According to the capacitor discharge control circuit for the flyback converter, disclosed by the invention, the active control feedback for controlling the capacitor discharge control circuit is performed by rapidly and autonomously discharging the resonant capacitor and detecting the voltage before the chip is started, so that the converter is ensured to have low enough charge on the resonant capacitor during starting and high safety; the current is not split during normal conversion of the converter, and the efficiency is improved.

Description

Capacitor discharge control circuit for flyback converter
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a capacitive discharge control circuit for flyback converters.
Background
As shown in fig. 1, in the Active Clamp Flyback (active clamp flyback converter ACF) structure, a large resonant capacitor SNBR (μf level) is generally hung on the primary side of the transformer as a device for absorbing the leakage inductance Lk energy, and the voltage difference across the resonant capacitor SNBR in the steady state is N times the ACF output voltage VOUT. The previously stored charge on the resonant capacitor SNBR needs to be brought below a threshold value each time the flyback converter is started to avoid a large current being drawn from the resonant capacitor SNBR to the SW node to burn out the upper tube M0 (or to trigger the over-current protection OCP to cause a fault condition) when starting the conversion.
The common passive discharging method is that a resistor R in a megaohm level is connected in parallel to two ends of a resonant capacitor SNBR, the discharge current in a microampere level is used for continuous discharging, the discharging time is in a second level, the discharging is slow, and when the ACF works normally, the resistor R can be shunted, so that the efficiency of the ACF is reduced.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a capacitor discharge control circuit for a flyback converter, which can detect the voltages at two ends of a resonant capacitor and discharge the voltages rapidly when the flyback converter is started, ensure that the voltages at two ends of the resonant capacitor discharge below a threshold voltage in a shorter time, and avoid introducing loss when the flyback converter works normally.
To achieve the above object, an embodiment of the present invention provides a capacitor discharge control circuit for a flyback converter, the flyback converter including a transformer and a resonant capacitor, the resonant capacitor being connected to a primary side of the transformer, the capacitor discharge control circuit being connected to both ends of the resonant capacitor, the capacitor discharge control circuit comprising:
the discharging circuit is connected with two ends of the resonant capacitor and is used for discharging the resonant capacitor based on the control of the first control signal;
the detection circuit is connected with two ends of the resonance capacitor, and is used for detecting the capacitor voltage at two ends of the resonance capacitor based on the control of the first control signal and generating a first characterization signal and a second characterization signal for characterizing the capacitor voltage at two ends; and
and a control circuit for adjusting the first control signal based on the first characterization signal and the second characterization signal.
In one or more embodiments of the present invention, the capacitor discharge control circuit further includes a level shift circuit, the level shift circuit being connected to the discharge circuit, the detection circuit, and the control circuit, the level shift circuit being configured to level shift the initial signal to generate the first control signal, and the control circuit being configured to adjust the initial signal based on the first characterization signal, the second characterization signal, and the reference voltage.
In one or more embodiments of the present invention, the level shift circuit includes one or more first resistors connected in series for generating a first control signal, and a first isolation tube and/or a first current source connected in series with the first resistors and controlled to be turned on and off by an initial signal.
In one or more embodiments of the present invention, the discharging circuit includes a load unit and a switch control unit connected to each other, and the switch control unit controls on/off of a path between the load unit and the resonance capacitor based on control of the first control signal.
In one or more embodiments of the invention, the load unit comprises a discharge resistor connected to a switch control unit, or
The load unit comprises a first current mirror connected with the switch control unit and a second current source connected with the first current mirror.
In one or more embodiments of the present invention, the capacitive discharge control circuit further includes a backflow prevention unit connected to the discharge circuit.
In one or more embodiments of the present invention, the detection circuit includes a first conversion unit connected to a first terminal of the resonance capacitor to generate a first characterization signal based on control of a first control signal, and a second conversion unit connected to a second terminal of the resonance capacitor to generate a second characterization signal based on control of the first control signal.
In one or more embodiments of the present invention, the first conversion unit includes a second isolation tube and a plurality of first voltage dividing resistors, one or more of the first voltage dividing resistors is connected between a first end of the second isolation tube and a first end of the resonant capacitor, and one or more of the first voltage dividing resistors is connected between a second end of the second isolation tube and a ground voltage for generating a first characterization signal; and/or
The second conversion unit comprises a third isolation tube and a second voltage dividing resistor, wherein one or more first voltage dividing resistors are connected between the second end of the third isolation tube and the second end of the resonant capacitor and used for generating a second characterization signal.
In one or more embodiments of the present invention, the control circuit includes an operation unit for performing a flip-threshold operation of a first comparator based on a second characterization signal to generate a reference signal, a first end of the first comparator for receiving the reference signal, a second end of the first comparator for receiving the first characterization signal, an output of the first comparator for outputting a comparison signal, and a logic control unit for generating an initial signal based on the comparison signal and a reset signal.
In one or more embodiments of the present invention, the logic control unit includes an inverter and a nand gate, an input terminal of the inverter is configured to receive a reset signal, a first input terminal of the nand gate is connected to an output terminal of the nand gate, a second input terminal of the nand gate is connected to an output terminal of the first comparator, and an output terminal of the nand gate outputs an initial signal.
Compared with the prior art, the capacitor discharge control circuit for the flyback converter provided by the embodiment of the invention has the advantages that the control feedback is made by rapidly and autonomously discharging the resonant capacitor before the chip is not started and detecting the voltage on the resonant capacitor, no current is split during normal conversion of the converter, the efficiency is improved, and the capacitor discharge control circuit adopts active control feedback to ensure that the charge on the resonant capacitor is low enough and the safety is high during the starting of the converter; and an anti-backflow unit is added on the passage of the high-side power domain, so that the safety of the circuit is further ensured.
Drawings
Fig. 1 is a schematic circuit diagram of a capacitive discharge circuit for a flyback converter according to the prior art.
Fig. 2 is a system diagram of a capacitive discharge control circuit for a flyback converter according to a first embodiment of the present invention.
Fig. 3 is a schematic circuit diagram of a capacitive discharge control circuit for a flyback converter according to a first embodiment of the present invention.
Fig. 4 is a first circuit schematic of a level shifter circuit according to a first embodiment of the present invention.
Fig. 5 is a second circuit schematic of the level shifter circuit according to the first embodiment of the present invention.
Fig. 6 is a third circuit schematic of the level shifter circuit according to the first embodiment of the present invention.
Fig. 7 is a first circuit schematic of a discharge circuit according to a first embodiment of the present invention.
Fig. 8 is a second circuit schematic of a discharge circuit according to a first embodiment of the invention.
Fig. 9 is a first schematic diagram of a backflow preventing unit according to a first embodiment of the present invention.
Fig. 10 is a second schematic diagram of the backflow preventing unit according to the first embodiment of the present invention.
Fig. 11 is a schematic circuit diagram of a first conversion unit according to a first embodiment of the present invention.
Fig. 12 is a schematic circuit diagram of an arithmetic unit according to the first embodiment of the present invention.
Fig. 13 is a first schematic circuit diagram of a discharge circuit according to a second embodiment of the invention.
Fig. 14 is a second schematic circuit diagram of a discharge circuit according to a second embodiment of the present invention.
Detailed Description
Specific embodiments of the invention will be described in detail below with reference to the drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediary, such as an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connections may also include connections through other active or passive devices, such as through circuits or components such as switches, follower circuits, and the like, that accomplish the same or similar functional objectives. Furthermore, in the present invention, terms such as "first," "second," and the like, are used primarily to distinguish one technical feature from another, and do not necessarily require or imply a certain actual relationship, number or order between the technical features.
Example 1
A capacitor discharge control circuit for a flyback converter, as shown in FIG. 2, includes a transformer T and a resonant capacitor SNBR connected to the primary side of the transformer T. The capacitor discharging control circuit is connected with two ends of the resonance capacitor SNBR, a first end of the resonance capacitor SNBR is connected with the node SW through the switch tube MK, and a second end of the resonance capacitor SNBR is connected with the power supply voltage VDD. When the flyback converter is in a steady state, the voltage on the resonant capacitor SNBR is V=N×VOUT, and when the resonant capacitor SNBR is discharged, the first end of the resonant capacitor SNBR outputs discharge current to the capacitor discharge control circuit for discharging.
As shown in fig. 3, the capacitive discharge control circuit includes: level conversion circuit, discharge circuit, detection circuit and control circuit. As can be seen from fig. 3, the second terminal of the resonant capacitor SNBR is connected to the power supply voltage VDD, and the first terminal of the resonant capacitor SNBR outputs a discharge current when discharging, and the resonant capacitor SNBR is in a high-side power supply domain with the power supply voltage VDD as "ground".
In one embodiment, the level shifter is connected to the discharging circuit, the detecting circuit and the control circuit, and the level shifter is used for level shifting the initial signal init_ss to generate the first control signal init_ss_hv. The initial signal init_ss in the low-side power domain is converted into the first control signal init_ss_hv in the high-side power domain by the level conversion circuit.
The discharging circuit is connected with two ends of the resonance capacitor SNBR, and the discharging circuit discharges the resonance capacitor SNBR based on the control of the first control signal INIT_SS_HV.
The detection circuit is connected with two ends of the resonance capacitor SNBR, and is used for detecting the capacitor voltage at two ends of the resonance capacitor SNBR based on the control of the first control signal INIT_SS_HV and generating a first characterization signal VA and a second characterization signal VB for characterizing the capacitor voltage at two ends.
The control circuit is arranged to adjust the initial signal init_ss based on the first characterization signal VA and the second characterization signal VB. If the resonance capacitor SNBR is in the low-side power domain, the level shift circuit is not provided, and the control circuit directly adjusts the first control signal init_ss_hv based on the first characterization signal VA and the second characterization signal VB.
As shown in fig. 4, the level shift circuit includes one or more first resistors R1 connected in series for generating the first control signal init_ss_hv, and a first isolation tube MN1 and a first current source A1 connected in series with the first resistor R1 and controlled to be turned on and off by the initial signal init_ss. In other embodiments, the level shifting circuit may be other level shifting circuits such as pulse type or level type.
In one embodiment, the first resistor R1 is provided with two first ends, wherein the first end of one first resistor R1 is connected to the first end of the first isolation tube MN1, the second end is connected to the first end of the other first resistor R1, and the second end of the other first resistor R1 is connected to the first end of the resonant capacitor SNBR. The second end of the first isolation tube MN1 is connected to the first end of the first current source A1, the second end of the first current source A1 is connected to the ground voltage GND, and the control end of the first isolation tube MN1 is configured to receive the initial signal init_ss. The first isolation tube MN1 is an N-channel MOS tube, the first end of the first isolation tube MN1 is a drain electrode, the second end of the first isolation tube MN1 is a source electrode, and when the first isolation tube MN1 is controlled to be conducted by an initial signal INIT_SS and the first current source A1 is controlled to be started by the initial signal, a node connected with the two first resistors R1 generates a first control signal INIT_SS_HV. In other embodiments, the number of the first resistors R1 may be more than three in series as desired.
As shown in fig. 5 and 6, in other embodiments, in the selection of the first isolation tube MN1 and the first current source A1, only the first current source A1 may be selected, or only the first isolation tube MN1 may be selected.
The discharging circuit comprises a load unit and a switch control unit which are connected, and the switch control unit controls the on-off of a channel between the load unit and the resonance capacitor SNBR based on the control of the first control signal INIT_SS_HV.
As shown in fig. 7, in one embodiment, the load unit includes a discharge resistor Rz connected to the switch control unit. The switch control unit includes an inverter N and a switching tube MK. The switch tube MK is a P channel MOS tube, the first end of the switch tube MK is a drain electrode, the second end of the switch tube MK is a source electrode, and the control end of the switch tube MK is a grid electrode. The second end of the switch tube MK is connected with the first end of the resonance capacitor SNBR, the first end of the switch tube MK is connected with the first end of the discharge resistor Rz, the second end of the discharge resistor Rz is connected with the first end of the resonance capacitor SNBR, the output end of the inverter N is connected with the control end of the switch tube MK, and the input end of the inverter N is used for receiving the first control signal INIT_SS_HV.
In other embodiments, as shown in fig. 8, the switch tube MK is an N-channel MOS tube, so that the inverter N may not be provided.
In addition, as can be seen in fig. 7 and 8, the capacitive discharge control circuit further includes a backflow prevention unit connected to the discharge circuit. The anti-backflow unit is connected in series with the branch circuit where the load unit and the switch control unit are located.
As shown in fig. 9, in an embodiment, the anti-backflow unit may be composed of a diode D or a MOS transistor MD. In fig. 7, the anode of the diode D is connected to the second terminal of the discharge resistor Rz, and the cathode of the diode D is connected to the second terminal of the resonance capacitor SNBR. In fig. 8, the anode of the diode D is connected to the second terminal of the switching tube MK, and the cathode of the diode D is connected to the second terminal of the resonance capacitor SNBR.
As shown in fig. 9, if a single MOS transistor MD is used, the MOS transistor MD may be an N-channel MOS transistor or a P-channel MOS transistor. The control end of the MOS tube MD is connected with the second end of the MOS tube MD to form a diode connection method, the control end of the MOS tube MD is a grid electrode, the second end of the MOS tube MD is a source electrode, and the first end of the MOS tube MD is a drain electrode. If the MOS tube MD is an N-channel MOS tube, the control end of the MOS tube MD is connected with the second end of the MOS tube MD to be used as the anode of a diode, and if the MOS tube MDP is a channel MOS tube, the control end of the MOS tube MD is connected with the second end of the MOS tube MD to be used as the cathode of the diode. The anti-backflow function is realized through the body diode DP of the MOS tube MD.
In other embodiments, as shown in fig. 10, the backflow preventing unit may also be formed by a single N-channel or P-channel MOS tube MD. When the single MOS tube MD is adopted, according to the type of the MOS tube MD, when the resonance capacitor SNBR discharges, a control signal is input to the control end of the MOS tube MD to control the MOS tube MD to be in a conducting state. If the MOS tube MD is a P-channel MOS tube, a control signal lower than the power supply voltage VDD is input to the control end of the MOS tube MD to control the MOS tube MD to be in a conducting state; if the MOS tube MD is an N-channel MOS tube, the control end of the MOS tube MD can be input with a first control signal INIT_SS_HV to control the MOS tube MD to be in a conducting state, and the anti-backflow function is realized through the body diode DP of the MOS tube MD.
As shown in fig. 11, the detection circuit includes a first conversion unit and a second conversion unit. The first conversion unit is connected to a first end of the resonant capacitor SNBR to generate a first characterization signal VA based on control of a first control signal init_ss_hv. The second switching unit is connected to a second terminal of the resonance capacitor SNBR to generate a second characterization signal VB based on the control of the first control signal init_ss_hv.
As shown in fig. 11, the first conversion unit includes a second isolation tube MN2 and a plurality of first voltage dividing resistors Rp1, wherein one or more first voltage dividing resistors Rp1 are connected between a first end of the second isolation tube MN2 and a first end of the resonant capacitor SNBR, and one or more first voltage dividing resistors Rp1 are connected between a second end of the second isolation tube MN2 and a ground voltage GND for generating a first characterization signal VA.
The second isolation tube MN2 is an N-channel MOS tube, the first end of the second isolation tube MN2 is a drain electrode, the second end of the second isolation tube MN2 is a source electrode, and the control end of the second isolation tube MN2 is a grid electrode. In an embodiment, four first divider resistors Rp1 are provided, wherein two first divider resistors Rp1 are connected in series between the first end of the second isolation tube MN2 and the first end of the resonant capacitor SNBR, and the other two first divider resistors Rp1 are connected in series between the second end of the second isolation tube MN2 and the ground voltage GND, and generate the first characterization signal VA at the node where the two first divider resistors Rp1 are connected when the control end of the second isolation tube MN2 is controlled by the first control signal init_ss_hv to be turned on. In other embodiments, the second isolation tube MN2 may be a P-channel MOS tube, and the number of the first voltage dividing resistors Rp1 may be set as required.
As shown in fig. 11, the second conversion unit includes a third isolation tube MN3 and a second voltage dividing resistor Rp2, wherein a first end of the third isolation tube MN3 and a second end of the resonant capacitor SNBR, and one or more first voltage dividing resistors Rp1 are connected between the second end of the third isolation tube MN3 and the ground voltage GND for generating the second characterization signal VB.
The third isolation tube MN3 is an N-channel MOS tube, the first end of the third isolation tube MN3 is a drain electrode, the second end of the third isolation tube MN3 is a source electrode, and the control end of the third isolation tube MN3 is a grid electrode. In one embodiment, two second voltage dividing resistors Rp2 are provided, the two second voltage dividing resistors Rp2 are connected in series between the second end of the third isolation tube MN3 and the ground voltage GND, and when the control end of the third isolation tube MN3 is controlled by the first control signal init_ss_hv to be turned on, the node where the two second voltage dividing resistors Rp2 are connected generates the second characterization signal VB. In other embodiments, the third isolation tube MN3 may be a P-channel MOS tube, and the number of the second voltage dividing resistors Rp2 may be set as required.
As shown in fig. 3, the control circuit includes an operation unit 10, a first comparator cmp1, and a logic control unit. The operation unit 10 is configured to generate the reference signal VG based on the second characterization signal VB and the inversion threshold of the first comparator cmp1, the first end of the first comparator cmp1 is configured to receive the reference signal VG, the second end of the first comparator cmp1 is configured to receive the first characterization signal VA, the output end of the first comparator cmp1 is configured to output the comparison signal DK, and the logic control unit generates the initial signal init_ss based on the comparison signal DK and the reset signal POR.
In one embodiment, as shown in fig. 12, the operation unit 10 includes an amplifier AO, a second resistor R2, and a third current source A3, where a first input terminal of the amplifier AO is configured to receive the second characterization signal VB, a second input terminal of the amplifier AO is connected to an output terminal of the amplifier AO, a first terminal of the second resistor R2 is connected to the output terminal of the amplifier AO, and a second terminal of the second resistor R2 is connected to the third current source A3 to output the reference signal VG. The first input of the amplifier AO is a positive input and the second input of the amplifier AO is a negative input.
As can be seen from the above, the first characterization signal VA is obtained by dividing the voltage of the first end of the resonant capacitor SNBR by the first dividing resistor Rp1, and the second characterization signal VB is obtained by dividing the voltage of the second end of the resonant capacitor SNBR by the second dividing resistor Rp 2. It is assumed that the comparison signal DK output by the first comparator cmp1 is inverted (e.g., turned to a high level) when the voltage at the first terminal of the resonant capacitor SNBR is smaller than the voltage at the second terminal of the resonant capacitor SNBR to be the reference voltage VREF.
In design, the voltage division ratio of the node a and the node B is k, the dimensions of the second isolation tube MN2 and the third isolation tube MN3 are the same, that is, when the first characterization signal VA at the node a is greater than the second characterization signal VB at the node B by vref×k, the comparison signal DK output by the first comparator cmp1 is turned over, and at this time, the turning threshold of the first comparator cmp1 can be considered as vref×k.
The reference signal vg=ir2+vb is obtained by the operation unit 10, I is the current of the third current source A3, and i×r2 is equal to vref×k, so as to satisfy the inversion requirement of the first comparator cmp 1.
As shown in fig. 3, the logic control unit includes a NOT gate NOT and a nand gate AT, wherein an input end of the NOT gate NOT is used for receiving a reset signal POR, a first input end of the nand gate AT is connected to an output end of the nand gate NOT, a second input end of the nand gate AT is connected to an output end of the first comparator cmp1, and an output end of the nand gate AT outputs an initial signal init_ss.
Before the chip is started, an initial signal INIT_SS is needed to reset the circuit state, and the signal is a control signal of a low-side power domain. Since the transformer corresponds to a short circuit under direct current before the start of the conversion, the voltage of the power supply voltage VDD at this time is equal to the voltage of the SW node.
In one embodiment, the initial signal init_ss is used as a switching signal, when the initial signal init_ss is high, the chip is considered to be in a reset state, the first control signal init_ss_hv is generated after passing through the level conversion circuit, the discharging circuit and the detecting circuit in the high-side power domain are turned on, the discharging circuit discharges the resonant capacitor SNBR in milliamp level, and the detecting circuit detects the voltages at two ends of the resonant capacitor SNBR in real time and converts the voltages to the low-side power domain.
And the anti-backflow unit is connected to the discharge path so as to prevent the substrate VBUS and/or SW nodes of the MOS tube M1 from flowing current to the resonance capacitor SNBR through the discharge control circuit when the anti-backflow unit is started.
When the voltage difference between the two ends of the resonant capacitor SNBR is smaller than the preset reference voltage VREF, the comparison signal DK turns high, which means that enough charges are discharged on the resonant capacitor SNBR at the moment, the initialization is completed, the initial signal INIT_SS turns low and turns off the discharging circuit and the detecting circuit, so that the charging current of the resonant capacitor SNBR can not be shunted when the converter works normally, and the efficiency is improved. If the charge on the resonance capacitor SNBR is not sufficiently low, i.e. the comparison signal DK is low, the chip is always in a reset state and no conversion is started.
Example 2
The present embodiment differs from embodiment 1 in the structure of the load unit and the connection manner with the switch control unit.
As shown in fig. 13, the load unit includes a first current mirror connected to the switch control unit and a second current source A2 connected to the first current mirror.
The first current mirror comprises a first MOS tube M1 and a second MOS tube M2, the first MOS tube M1 and the second MOS tube M2 are P-channel MOS tubes, the first end of the first MOS tube M1 and the first end of the second MOS tube M2 are drain electrodes, the second end of the first MOS tube M1 and the second end of the second MOS tube M2 are source electrodes, and the control end of the first MOS tube M1 and the control end of the second MOS tube M2 are grid electrodes.
The second end of the first MOS tube M1 and the second end of the second MOS tube M2 are connected with the first end of the resonance capacitor SNBR, the control end of the first MOS tube M1 is connected with the control end of the second MOS tube M2, and the control end of the first MOS tube M1 is connected with the first end of the first MOS tube M1.
The first end of the first MOS tube M1 is connected with the second end of a switch tube MK of the switch control unit, the first end of the switch tube MK is connected with the first end of a second current source A2 and the second end of the resonance capacitor SNBR, the control end of the switch tube MK is connected with the inverter N, the second end of the second current source A2 is connected with the ground voltage, and the second current source A2 is in a low-side power domain.
The first end of the second MOS transistor M2 may be connected to a backflow preventing unit, which is simultaneously connected to the first end of the switch transistor MK and the second end of the resonance capacitor SNBR. In other embodiments, the resonant capacitor SNBR may not be provided, and the first end of the second MOS transistor M2 at this time may be directly connected to the first end of the switch transistor MK and the second end of the resonant capacitor SNBR.
Various structures of the backflow preventing unit are described in embodiment 1, and are not described here again.
In other embodiments, as shown in fig. 14, the first MOS transistor M1 and the second MOS transistor M2 are N-channel MOS transistors, the first end of the first MOS transistor M1 and the first end of the second MOS transistor M2 are drain electrodes, the second end of the first MOS transistor M1 and the second end of the second MOS transistor M2 are source electrodes, and the control end of the first MOS transistor M1 and the control end of the second MOS transistor M2 are gate electrodes.
The control end of the first MOS tube M1 is connected with the control end of the second MOS tube M2, the first end of the first MOS tube M1 is connected with the control end of the first MOS tube M1, the first end of the first MOS tube M1 is connected with the second current source A2, and the second current source A2 is in a high-side power domain.
The second end of the first MOS tube M1 and the second end of the second MOS tube M2 are connected with the second end of the resonance capacitor SNBR through the backflow preventing unit, the first end of the second MOS tube M2 is connected with the first end of the switching tube MK, the second end of the switching tube MK is connected with the first end of the resonance capacitor SNBR, and the control end of the switching tube MK is connected with the inverter N.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teachings or may be acquired from other forms, structures, arrangements, proportions, and with other components, materials and parts. The exemplary embodiments were chosen and described in order to explain the principles of the invention and its practical application to thereby enable others skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (10)

1. A capacitive discharge control circuit for a flyback converter, the flyback converter comprising a transformer and a resonant capacitor, the resonant capacitor being connected to a primary side of the transformer, the capacitive discharge control circuit being connected to two ends of the resonant capacitor, the capacitive discharge control circuit comprising:
the discharging circuit is connected with two ends of the resonant capacitor and is used for discharging the resonant capacitor based on the control of the first control signal;
the detection circuit is connected with two ends of the resonance capacitor, and is used for detecting the capacitor voltage at two ends of the resonance capacitor based on the control of the first control signal and generating a first characterization signal and a second characterization signal for characterizing the capacitor voltage at two ends; and
and a control circuit for adjusting the first control signal based on the first characterization signal and the second characterization signal.
2. The capacitive discharge control circuit for a flyback converter of claim 1 further comprising a level shifter circuit coupled to the discharge circuit, the detection circuit, and the control circuit, the level shifter circuit configured to level shift the initial signal to generate the first control signal, the control circuit configured to adjust the initial signal based on the first characterization signal, the second characterization signal, and the reference voltage.
3. The capacitive discharge control circuit for a flyback converter of claim 2 wherein the level shifter circuit includes one or more first resistors connected in series for generating the first control signal, and a first isolation tube and/or a first current source connected in series with the first resistors and controlled to turn on and off by the initial signal.
4. The capacitive discharge control circuit for a flyback converter of claim 1 wherein the discharge circuit includes a load cell and a switch control cell connected, the switch control cell being controlled based on the first control signal to control the on-off of a path between the load cell and the resonant capacitor.
5. The capacitive discharge control circuit for a flyback converter of claim 4 wherein the load cell includes a discharge resistor connected to a switch control cell, or
The load unit comprises a first current mirror connected with the switch control unit and a second current source connected with the first current mirror.
6. The capacitive discharge control circuit for a flyback converter of claim 1 further comprising a backflow prevention unit coupled to the discharge circuit.
7. The capacitive discharge control circuit for a flyback converter of claim 1 wherein the detection circuit includes a first switching unit coupled to a first terminal of the resonant capacitor to generate the first characterization signal based on control of the first control signal and a second switching unit coupled to a second terminal of the resonant capacitor to generate the second characterization signal based on control of the first control signal.
8. The capacitive discharge control circuit for a flyback converter of claim 7 wherein the first conversion unit includes a second isolation tube and a plurality of first voltage dividing resistors, one or more of the first voltage dividing resistors connected between a first end of the second isolation tube and a first end of the resonant capacitor, one or more of the first voltage dividing resistors connected between a second end of the second isolation tube and ground voltage for generating the first characterization signal; and/or
The second conversion unit comprises a third isolation tube and a second voltage dividing resistor, wherein one or more first voltage dividing resistors are connected between the second end of the third isolation tube and the second end of the resonant capacitor and used for generating a second characterization signal.
9. The capacitive discharge control circuit for a flyback converter of claim 2, wherein the control circuit includes an arithmetic unit for performing a flip-threshold operation of the first comparator based on the second characterization signal to generate the reference signal, a first end of the first comparator for receiving the reference signal, a second end of the first comparator for receiving the first characterization signal, an output of the first comparator for outputting the comparison signal, and a logic control unit for generating the initial signal based on the comparison signal and the reset signal.
10. The capacitive discharge control circuit for a flyback converter of claim 9 wherein the logic control unit comprises a not gate and a nand gate, the input of the not gate being configured to receive the reset signal, the first input of the nand gate being coupled to the output of the nand gate, the second input of the nand gate being coupled to the output of the first comparator, the output of the nand gate outputting the initial signal.
CN202311845510.4A 2023-12-28 2023-12-28 Capacitor discharge control circuit for flyback converter Pending CN117811360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311845510.4A CN117811360A (en) 2023-12-28 2023-12-28 Capacitor discharge control circuit for flyback converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311845510.4A CN117811360A (en) 2023-12-28 2023-12-28 Capacitor discharge control circuit for flyback converter

Publications (1)

Publication Number Publication Date
CN117811360A true CN117811360A (en) 2024-04-02

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Family Applications (1)

Application Number Title Priority Date Filing Date
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