CN117810322A - LED epitaxial structure, LED chip and light-emitting device - Google Patents

Abstract

The invention provides an LED epitaxial structure, an LED chip and a light-emitting device. The LED epitaxial structure includes a bottom-up stacked substrate, a first semiconductor layer, an active layer and a second semiconductor layer. The active layer includes n pairs. The combination of well layer and barrier layer. The structural material _of the well layer is (Al _X1 Ga _1‑X1 ) _Y1 In _{1‑Y1 P , and} the structural material of the barrier layer is (Al Apply to reduce the In content of the well layer and barrier layer simultaneously. Since there is still a certain difference in In content between the well layer and the barrier layer, it is ensured that the compressive stress of the well layer will not affect the luminous efficiency. At the same time, the reduced In content reduces the difference in lattice constants between the well layer and the substrate, reduces the occurrence of defects such as dislocations, and improves the crystal quality of the epitaxial layer. After adopting the active layer design of this application, not only the dark and bright lines at the edge of the epitaxial wafer are greatly converged, but also the brightness of the LED chip is increased by 5%-10%.

Description

An LED epitaxial structure, LED chip and light-emitting device

Technical Field

The present invention relates to the technical field of semiconductor light-emitting materials, and in particular to an LED epitaxial structure, an LED chip and a light-emitting device.

Background technique

Light Emitting Diode (Light Emitting Diode) is a semiconductor device that can directly convert electrical energy into light energy. It is a solid-state cold light source. The inherent physical characteristics of LEDs enable them to operate at low voltage/current, and have the characteristics of high luminous efficiency, small size, long life, and energy saving. Therefore, LED has now become the core light-emitting device in transportation display, medical lighting, military communications and other fields. Red LED chips are generally made of AlGaInP (aluminum gallium indium phosphorus) quaternary material. Quaternary AlGaInP light-emitting diodes have the characteristics of low power consumption, high luminous efficiency, long life, small size, and low cost. Therefore, they are widely used in lighting and Optical fiber communication systems have a wide range of applications. The epitaxial wafer of an AlGaInP light-emitting diode usually includes a substrate and an N-type layer, an active layer, a P-type layer, etc. sequentially stacked on the substrate. The active layer serves as the light-emitting area, and the quality of its epitaxy directly determines the luminous efficiency of the LED.

For the red LED epitaxial layer, by enlarging the stress difference between the well layer and the barrier layer in the active layer, the well layer's ability to recombine carriers can be improved and the brightness can be improved. However, most design methods are achieved by increasing the compressive stress of the well while keeping the barrier stress unchanged. However, for the substrate, the strain of the well layer is too large, resulting in excessive lattice mismatch, which can easily cause dislocations. Especially, the compressive stress at the edge of the epitaxial wafer is higher than that at the center. Based on this, it is easy to cause 0-2mm at the edge. Dark and bright lines are produced due to stress mismatch, which poses quality risks.

Therefore, it is necessary to redesign the well layer and barrier layer of the active layer to reduce the lattice mismatch between the well layer and the substrate, while maintaining the stress difference between the well layer and the barrier layer to improve brightness.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an LED epitaxial structure for solving the problem of dark-bright lines caused by stress mismatch in the prior art.

In order to achieve the above objects and other related objects, the present invention provides an LED epitaxial structure. The LED epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked from bottom to top. The active layer Including n layer pairs, each layer pair includes a combination of a well layer and a barrier layer;

The structural material of the well layer is ( _{AlX1Ga1 -X1} ) _{Y1In1 -} Y1P, 0.4≤Y1≤0.5≤1-Y1≤1; the structural material of the barrier layer is ( _{AlX2Ga1 -X2} ) _{Y2In1 -Y2P} , 0.4≤1-Y2≤0.5≤Y2≤0.6.

Preferably, it also includes a substrate, a buffer layer and an etching stop layer located between the substrate and the first semiconductor layer.

Preferably, the first semiconductor layer includes a stacked N-type ohmic contact layer, an N-type current spreading layer, and an N-type covering layer.

Preferably, the second semiconductor layer includes a stacked P-type cover layer, a P-type current spreading layer, and a P-type ohmic contact layer.

Preferably, 0≤X1≤0.2, 0.5≤X2≤1.

Preferably, 5%≤((1-Y1)/Y1)-1≤20%, 5%≤(Y2/(1-Y2))-1≤20%.

Preferably, 1≤n≤50.

Preferably, along the bottom-up direction, the In content of the plurality of well layers gradually increases, and the In content of the plurality of barrier layers gradually decreases.

Preferably, the substrate of the LED epitaxial structure is GaAs, and the LED epitaxial structure radiates red light.

The invention also provides an LED chip, which is characterized in that the LED chip includes:

LED epitaxial structure, the LED epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked from bottom to top; the active layer includes n layer pairs, and each layer pair includes a well layer and a The _{combination of} barrier layers _; the structural material of _the well layer is ₍ Al _1-X2 ) _Y2 In _{1- Y2} P，0.4≤1-Y2≤0.5≤Y2≤0.6;

An N electrode and a P electrode, wherein the N electrode is electrically connected to the first semiconductor layer, and the P electrode is electrically connected to the second semiconductor layer.

Preferably, 0≤X1≤0.2, 0.5≤X2≤1.

Preferably, 5%≤((1-Y1)/Y1)-1≤20%, 5%≤(Y2/(1-Y2))-1≤20%.

Preferably, 1≤n≤50.

Preferably, along the bottom-up direction, the In content of the plurality of well layers gradually increases, and the In content of the plurality of barrier layers gradually decreases.

Preferably, the LED chip radiates red light.

The present invention also provides a light-emitting device, which includes the above-mentioned LED chip. As mentioned above, the present invention provides an LED epitaxial structure, an LED chip and a light-emitting device. The LED epitaxial structure includes a bottom-up stacked substrate, a first semiconductor layer, an active layer, and a second semiconductor layer. The layers include n pairs of well layer and barrier layer combinations. The structural material of the well layer is (Al _X1 Ga _1-X1 ) _Y1 In _{1-Y1 P , and} the structural material of the barrier layer is ( _Al (1-Y1)/Y1)-1≤20%, 5%≤(Y2/(1-Y2))-1≤20%. Compared with the existing technical solution, this application reduces the In content of the well layer and the barrier layer simultaneously. Since there is still a certain difference in In content between the well layer and the barrier layer, the compressive stress of the well layer is ensured without affecting the In content. Will affect the luminous efficiency. At the same time, the reduced In content reduces the difference in lattice constants between the well layer and the substrate, reduces the occurrence of defects such as dislocations, and improves the crystal quality of the epitaxial layer. After adopting the active layer design of this application, not only the dark and bright lines at the edge of the epitaxial wafer are greatly converged, but also the brightness of the LED chip is increased by 5%-10%.

Description of drawings

Figure 1 shows a schematic diagram of the LED epitaxial structure.

Figure 2 shows a schematic structural diagram of the LED chip of the present invention as a horizontal chip.

FIG. 3 is a schematic diagram showing the structure of a vertical flip chip LED chip of the present invention.

Figure 4 shows a schematic structural diagram of the LED chip of the present invention as a vertically mounted chip.

FIG. 5 shows a schematic top structural view of the light-emitting device of the present invention.

Component number description

100 substrate

101 Buffer Layer

102 Etch cutoff layer

103 N-type ohmic contact layer

104 N-type current expansion layer

105 N type cover

106 active layer

107 P type covering

108 P-type current expansion layer

109 P-type ohmic contact layer

1061 Well layer

1062 Layer

201 bonding layer

202 substrate

203 P electrode

204 N electrode

205 DBR reflective layer

300 light fixtures

301 circuit board

302 lighting unit

Detailed ways

The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

When describing the embodiments of the present invention in detail, for convenience of explanation, the cross-sectional views showing the device structure are not partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual production.

For convenience of description, spatial relationship words such as "below", "below", "below", "below", "above", "on", etc. may be used herein to describe an element or element shown in the drawings. The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientations depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between" means including both endpoint values.

In the context of this application, structures described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features. Embodiments between second features such that the first and second features may not be in direct contact.

It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

As shown in Figure 1, it is a common epitaxial structure of a GaAs red LED, including a bottom-up substrate 100, a buffer layer 101, an etching stop layer 102, a first semiconductor layer, an active layer 106, and a second semiconductor layer. . The first semiconductor layer includes an N-type ohmic contact layer 103, an N-type current spreading layer 104, and an N-type cladding layer 105 stacked from bottom to top; the second semiconductor layer includes a P-type cladding layer stacked from bottom to top. 107. P-type current expansion layer 108, P-type ohmic contact layer 109.

The active layer 106 includes n layer pairs, each layer pair includes a combination of a well layer 1061 and a barrier layer 1062, the structural material of the well layer 1061 is (Al _X1 Ga _1-X1 ) _Y1 In _1-Y1 P, 0≤X1≤1, 0≤Y1≤1-Y1≤1; the structural material of the barrier layer 1062 is (Al _X2 Ga _1-X2 ) _Y2 In _1-Y2 P, 0≤X2≤1, 0≤Y2≈1-Y2≤1.

In the existing technical solution, the well is usually rich in In, ((1-Y1)/Y1)-1≥20%, that is, Y1≤0.45, 1-Y1≥0.55, that is, the actual In content of the well layer 1061 is greater than 0.55. The higher In content is designed here because there is stress between the well barriers, which can improve the brightness. However, the higher In content of the well layer 1061 will increase the lattice mismatch between it and the substrate 100. The lattice constant of the substrate GaAs is The lattice constants of AlP and GaP are/> The lattice constant of InP is The lattice constant of the well layer 1061 can be roughly calculated according to the proportion of various materials, that is, The well layer 1061 has a high In content and a large lattice constant, and therefore will be subjected to compressive stress from the barrier layer 1062. This compressive stress can increase the brightness; but at the same time, the lattice constant of the well layer 1061 is greater than the lattice constant of the substrate 100. The large lattice mismatch leads to dislocations, especially at the edge of the epitaxial wafer at 0-2mm, where stress mismatch produces dark-bright lines, affecting the epitaxial quality and the quality of the subsequently formed LED chips.

Therefore, the present invention proposes a design idea to reduce the lattice mismatch between the well layer 1061 and the substrate 100 while maintaining the stress between the well barriers, and improve the epitaxial quality.

Specifically, as shown in FIG. 1 , the present invention provides an LED epitaxial structure, which includes a substrate 100 , a first semiconductor layer, an active layer 106 , and a second semiconductor layer stacked from bottom to top. The first semiconductor layer includes an N-type ohmic contact layer 103, an N-type current spreading layer 104, and an N-type cladding layer 105 stacked from bottom to top; the second semiconductor layer includes a P-type cladding layer stacked from bottom to top. 107. P-type current expansion layer 108, P-type ohmic contact layer 109.

Specifically, the material of the substrate 100 includes but is not limited to GaAs. In this embodiment, GaAs is used as the substrate 100 .

The N-type current spreading layer 104 is disposed on the surface of the substrate 100 . Among them, the material of the N-type current spreading layer 104 is AlGaInP, and in order to improve the current spreading effect of the N-type current spreading layer 104, the N-type current spreading layer 104 is doped with a certain concentration of N-type impurities.

As an optional solution, a buffer layer 101, an etching stop layer 102, and an N-type ohmic contact layer 103 are sequentially arranged between the substrate 100 and the N-type current spreading layer 104; wherein, since the lattice quality of the buffer layer 101 is better than that of the substrate 100, growing the buffer layer 101 on the substrate 100 is conducive to eliminating the influence of the lattice defects of the substrate 100 on the epitaxial layer; the etching stop layer 102 is used as a stop layer when chemically etching and removing the substrate 100 in the later step, and the N-type ohmic contact layer 103 is used to form a good ohmic contact when preparing the electrode. In this embodiment, the etching stop layer 102 is an N-type etching stop layer 102, the material is N-GaInP, and the material of the N-type ohmic contact layer 103 is N-GaAs. The N-type doping of each of the above-mentioned N-type functional layers is silicon doping.

The N-type cladding layer 105 and the P-type cladding layer 107 are N-type doped and P-type doped respectively, and are used to provide electrons and holes respectively, so that recombination occurs in the active layer 106 to form radiative emission.

The P-type current spreading layer 108 is disposed above the P-type cladding layer 107 . Optionally, the material of the P-type current spreading layer 108 is GaP, and the thickness ranges from 0.8 to 3 μm. A P-type ohmic contact layer 109 is provided above the P-type current spreading layer 108 to form a good ohmic contact when preparing electrodes. The P-type doping of the P-type cladding layer 107 is magnesium doping.

The active layer 106 is a region that provides light radiation for the recombination of electrons and holes. Different materials can be selected according to different luminescent wavelengths. The active layer 106 includes n layer pairs, 1≤n≤50. Each layer pair includes a combination of a well layer 1061 and a barrier layer 1062. The barrier layer 1062 has a wider band gap than the well layer 1061, thereby confining electrons and holes in the well layer 1061 to recombine and generate radiant light.

The structural material _{of the} well layer 1061 is _{( Al} The structural material _of the barrier layer ₁₀₆₂ is _{( Al}

Furthermore, as a preferred solution, 20%≥((1-Y1)/Y1)-1≥5%, 5%≤(Y2/(1-Y2))-1≤20%. After calculation, we get 0.454≤Y1≤0.487, 0.512≤Y2≤0.545; the In content 1-Y1 in the well layer 1061 is 0.513≤1-Y1≤0.546, and the In content 1-Y2 in the barrier layer 1062 is 0.455≤1-Y2 ≤0.488.

Compared with the existing technical solutions, this application reduces the In content of the well layer 1061 and the barrier layer 1062 simultaneously. Since there is still a certain difference in In content between the well layer 1061 and the barrier layer 1062, it is ensured that the well layer 1061 The compressive stress will not affect the luminous efficiency. At the same time, the reduced In content reduces the difference in lattice constants between the well layer 1061 and the substrate 100, reduces the occurrence of defects such as dislocations, improves the crystal quality of the epitaxial layer, and ensures that the dark and bright lines at the edge of the epitaxial wafer are changed from the original 0 -2mm converges to within 0.5mm.

The preparation method of the above epitaxial structure is:

Provide a substrate 100;

A buffer layer 101 , an etching stop layer 102 , an N-type ohmic contact layer 103 , an N-type current spreading layer 104 , an N-type cap layer 105 , an active layer 106 , a P-type cap layer 107 , a P-type current spreading layer 108 , and a P-type ohmic contact layer 109 are sequentially formed on the substrate 100 .

Each of the above layers can be deposited by chemical vapor deposition. The In content of the well layer and barrier layer in the active layer can be adjusted by the gas flow rate of the raw material gas such as TMIn.

Embodiment 1

As an example, in this embodiment, the In content 1-Y1 in the well layer 1061 is selected to be 0.52, then the lattice constant of the well layer 1061 is The In content 1-Y2 in the barrier layer 1062 is selected to be 0.46, then the lattice constant of the barrier layer 1062 is/> Among them, the lattice constant of the substrate GaAs is/>

It can be seen that this application reduces the In content of the well layer 1061 and the barrier layer 1062 simultaneously, reducing the difference in lattice constants between them and the GaAs substrate, and improving the epitaxial quality. At the same time, the difference in lattice constants between the well layer 1061 and the barrier layer 1062 is maintained. Because the barrier layer 1062 is close to the well layer 1061 and the lattice constant of the barrier layer 1062 is smaller than the lattice constant of the well layer 1061, it is equivalent to converting a small mold frame into a small mold. It is placed on a large mold frame to provide a certain compressive stress to the well layer 1061, which is beneficial to improving the luminous efficiency.

According to actual measurements, after adopting the well and barrier scheme of the present application, not only the dark and bright lines at the edge of the epitaxial wafer are greatly converged, but also the brightness of the LED chip is increased by 5%-10%.

Embodiment 2

Based on the first embodiment, this embodiment continues to improve the structures of the well layer 1061 and the barrier layer 1062. When there are multiple layer pairs of well layers 1061 and barrier layers 1062 in the active layer 106, along the bottom-up direction, the In content of the multiple well layers 1061 gradually increases, and the In content of the multiple barrier layers 1062 gradually decreases. .

Specifically, the In content of the well layer near the bottom is relatively reduced, and the In content of the barrier layer near the bottom is relatively increased, so that the lattice constants of the well layer 1061 and the barrier layer 1062 below can be closer to the lattice constant of the substrate 100, laying a good foundation for the well above. Because of the overflow effect of electrons, the holes are relatively insufficient and cannot reach the quantum well near the bottom. In other words, the quantum well above the P-type cover layer 107 is the main light-emitting well. Therefore, the well below does not need to consider the light-emitting problem, but only needs to lay a good crystal quality epitaxial foundation for the subsequent well barriers, and does not require a large stress between the well barriers to improve the light-emitting efficiency. As the main light-emitting well, the quantum well above requires a large In content difference between the well barriers to improve the light-emitting efficiency.

As an alternative, the above-mentioned gradual increase or decrease can be a step-like increase or decrease. For example, the lowest well layers 1061 use the same In content, and the middle well layers 1061 use the same In content. content, the uppermost well layers 1061 use the same In content. As another alternative, the above-mentioned gradual increase or decrease can be a continuously changing increase or decrease. For any two adjacent upper and lower well layers 1061, the In content of the upper well layer 1061 is always greater than that of the lower well layer. In content of 1061.

Embodiment 3

Based on the above embodiments, this embodiment provides an LED chip, which includes the LED epitaxial structure in the above embodiments, and an N electrode and a P electrode, wherein the N electrode is electrically connected to the first semiconductor layer, and the P electrode is electrically connected to the second semiconductor layer.

In one embodiment, as shown in Figure 2, the LED chip is a flip chip. The LED chip also includes a substrate 202. The substrate 202 can be a sapphire substrate, a Cu substrate, a SiC substrate, etc. In this embodiment, the substrate 202 is a sapphire substrate, and a bonding layer 201 is provided between the substrate 202 and the P-type ohmic contact layer 109 for bonding the substrate 202 to the P-type ohmic contact layer 109 in the epitaxial structure. At the same time, the substrate 100, the buffer layer 101 and the etching stop layer 102 are removed, and the N electrode 204 is formed on the surface of the N-type ohmic contact layer 103. A step structure is also etched on the LED epitaxial structure, which exposes part of the surface of the P-type ohmic contact layer 109. The P electrode 203 is formed on the surface of the P-type ohmic contact layer 109 exposed by the step.

Specifically, mechanical grinding may be used to thin the substrate 100 first, and then wet etching may be used to remove the substrate 100, the buffer layer 101 and the etching stop layer 102, and expose the N-type ohmic contact layer 103. The P electrode or N electrode can be formed by evaporation or sputtering of metal.

In another embodiment, as shown in Figure 3, the LED chip is a vertical flip chip. The difference from the horizontal chip is that the vertical flip chip does not have a step structure, and the P electrode 203 is directly formed away from the substrate 202. The surface of the P-type ohmic contact layer 109 . The N electrode 204 is still formed on the surface of the N-type ohmic contact layer 103 . At this time, the substrate 202 is a conductive substrate, such as silicon, silicon carbide or a metal substrate. The metal substrate is preferably a copper, tungsten or molybdenum substrate.

In another embodiment, as shown in FIG. 4 , the LED chip is a vertical formal chip. For the epitaxial structure of the vertical formal chip, the substrate does not need to be removed, so there is no need to etch the cutoff layer 103 instead. is the DBR reflective layer 205 located between the buffer layer 101 and the N-type ohmic contact layer 103 . The DBR reflective layer 205 is used to prevent the substrate from absorbing light. After thinning the substrate, the N electrode 204 is directly formed on the surface of the substrate 100 away from the N-type ohmic contact layer 103; the P electrode 203 is directly formed on the surface of the P-type ohmic contact layer 109.

Embodiment 4

This embodiment provides a light-emitting device. As shown in FIG. 5 , the light-emitting device 300 includes a circuit substrate 301 and a light-emitting unit 302 provided on the circuit substrate 301 . The light-emitting unit 302 may be the LED chip provided in Embodiment 3 of the present application, and the plurality of light-emitting units 302 may be arranged in an array on the circuit substrate 301 .

It should be understood that the light-emitting device provided in this embodiment is made based on the LED chip structure provided in Embodiment 3. Therefore, the light-emitting device provided in this embodiment also has high luminous efficiency.

To sum up, the present invention provides an LED epitaxial structure, an LED chip and a light-emitting device. The LED epitaxial structure includes a substrate, a first semiconductor layer, an active layer and a second semiconductor layer stacked from bottom to top. The source layer includes n pairs of well layer and barrier layer combinations. The structural material of the well layer is (Al _X1 Ga _1-X1 ) _Y1 In _{1-Y1 P , and} the structural material of the barrier layer is ( _Al (1-Y1)/Y1)-1≤20%, 5%≤(Y2/(1-Y2))-1≤20%. Compared with the existing technical solution, this application reduces the In content of the well layer and the barrier layer simultaneously. Since there is still a certain difference in In content between the well layer and the barrier layer, the compressive stress of the well layer is ensured without affecting the In content. Will affect the luminous efficiency. At the same time, the reduced In content reduces the difference in lattice constants between the well layer and the substrate, reduces the occurrence of defects such as dislocations, and improves the crystal quality of the epitaxial layer. After adopting the active layer design of this application, not only the dark and bright lines at the edge of the epitaxial wafer are greatly converged, but also the brightness of the LED chip is increased by 5%-10%.

The above embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (16)

1. An LED epitaxial structure, characterized in that the LED epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked from bottom to top, and the active layer includes n layer pairs, Each layer pair includes a combination of a well layer and a barrier layer; _{The structural} material _{of the} well _layer is _{( Al} In _1-Y2 P, 0.4≤1-Y2≤0.5≤Y2≤0.6. 2 . The LED epitaxial structure according to claim 1 , further comprising a substrate, and a buffer layer and an etching stop layer located between the substrate and the first semiconductor layer. 3 . 3. The LED epitaxial structure according to claim 1, wherein the first semiconductor layer includes a stacked N-type ohmic contact layer, an N-type current spreading layer, and an N-type cladding layer. 4. The LED epitaxial structure according to claim 1, wherein the second semiconductor layer includes a stacked P-type cladding layer, a P-type current spreading layer, and a P-type ohmic contact layer. 5. The LED epitaxial structure according to claim 1, characterized in that: 0≤X1≤0.2, 0.5≤X2≤1. 6 . The LED epitaxial structure according to claim 1 , wherein: 5%≤((1-Y1)/Y1)-1≤20%, 5%≤(Y2/(1-Y2))-1≤20%. 7. The LED epitaxial structure according to claim 1, characterized in that: 1≤n≤50. 8. The LED epitaxial structure according to claim 1, characterized in that: along the bottom-up direction, the In content of the plurality of well layers gradually increases, and the In content of the plurality of barrier layers gradually decreases. 9. The LED epitaxial structure according to claim 1, characterized in that: the substrate of the LED epitaxial structure is GaAs, and the LED epitaxial structure radiates red light. 10. An LED chip, characterized in that the LED chip includes: LED epitaxial structure, the LED epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked from bottom to top; the active layer includes n layer pairs, and each layer pair includes a well layer and a The _{combination of} barrier layers _; the structural material of _the well layer is ₍ Al _1-X2 ) _Y2 In _1-Y2 P，0.4≤1-Y2≤0.5≤Y2≤0.6; N electrode and P electrode, wherein the N electrode forms an electrical connection with the first semiconductor layer, and the P electrode forms an electrical connection with the second semiconductor layer. 11. The LED chip according to claim 10, characterized in that: 0≤X1≤0.2, 0.5≤X2≤1. 12. The LED chip according to claim 10, characterized in that: 5%≤((1-Y1)/Y1)-1≤20%, 5%≤(Y2/(1-Y2))-1≤20 %. 13. The LED chip according to claim 10, characterized in that: 1≤n≤50. 14. The LED chip according to claim 10, characterized in that: along the bottom-up direction, the In content of the plurality of well layers gradually increases, and the In content of the plurality of barrier layers gradually decreases. 15. The LED chip according to claim 10, characterized in that: the LED chip radiates red light. 16. A light-emitting device, characterized in that the light-emitting device includes the LED chip according to any one of claims 10 to 15.