CN117792092A - Optimal efficiency self-adaptive adjusting circuit suitable for hysteresis direct-current voltage converter - Google Patents
Optimal efficiency self-adaptive adjusting circuit suitable for hysteresis direct-current voltage converter Download PDFInfo
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- CN117792092A CN117792092A CN202311829075.6A CN202311829075A CN117792092A CN 117792092 A CN117792092 A CN 117792092A CN 202311829075 A CN202311829075 A CN 202311829075A CN 117792092 A CN117792092 A CN 117792092A
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Abstract
The invention discloses an optimal efficiency self-adaptive adjusting circuit suitable for a hysteresis direct-current voltage converter, which comprises a reference power supply circuit, a current sampling circuit, a peak current comparator, a voltage comparator, a zero-crossing comparator, a main control module, an upper power tube MP, a lower power tube MN, an output circuit, a driving circuit and an N driving circuit, wherein the reference power supply circuit is connected with the current sampling circuit; the self-adaptive peak inductive current circuit is also included; the input end of the self-adaptive peak inductance current is respectively connected with an input voltage VIN, an output voltage VOUT, an output current ISEN of the current sampling circuit and a peak current setting current ISET; the output end of the self-adaptive peak inductance current is connected with a peak current comparator. According to the invention, the self-adaptive peak inductance current circuit is introduced into the input end of the peak current comparator, and the peak inductance current is regulated in a self-adaptive manner by checking the influence of the input voltage change, the ripple of the output voltage and the process and the temperature drift, so that the optimization of the converter efficiency is obtained.
Description
Technical Field
The invention relates to an analog integrated circuit technology, in particular to an optimal efficiency self-adaptive adjusting circuit which is suitable for a hysteresis direct-current voltage converter.
Background
A dc voltage converter is a very widely used circuit in the field of analog integrated circuits, and reduces or increases an input voltage according to a load, and generates a stable output voltage to a load circuit of a subsequent stage. The hysteresis direct-current voltage converter adopts a control method based on ripple waves, has the advantages of quick transient response and high efficiency, and can meet the design requirements of large slew rate and large load current range, so that the hysteresis direct-current voltage converter is widely applied to electronic equipment. The modulation signal of the hysteretic dc voltage converter is directly derived from the comparator without the use of any error amplifier. The transient response speed of the comparator is important and directly influences the efficiency of the converter. The peak current comparator controls the on time of the upper power tube by detecting the current of the inductance reaching the peak value, so as to realize the turn-off of the upper power tube MP, as shown in FIG. 1.
In the industry, a scheme for detecting whether the current of the inductor L reaches a peak value is generally to compare the SW voltage with a preset reference voltage VREF, and if the detected voltage of SW is higher than the VREF, the current of the inductor L is considered to reach the peak value, so as to turn off the upper power tube.
Specifically, after the upper power tube MP is turned on, the inductance current increases linearly, and the period of time from when the upper power tube MP is turned on to when the inductance current reaches a peak value is taken as the on time of the upper power tube MP, so that the on time of the upper power tube MP can be generated by the peak current comparator to control the turn-off of the upper power tube MP. The voltage or current is sampled, the sampled SW point signal is compared with a preset threshold voltage VREF, and if the sampled SW point signal is larger than the threshold value, the output control signal turns off the upper power tube MP.
The peak inductor current is manually adjustable (typically setting the maximum current initial value to 10-20 times the average load current), but there is theoretically an optimum peak inductor current when the converter is operating, so that the converter efficiency is maximized. The optimum peak inductor current may be represented by the relationship ilpeak=α (VIN/VOUT) T, where α is a scaling factor and T is temperature. Because the peak inductor current is related to the process, the temperature, the input voltage, the output voltage and the like, the peak inductor current corresponding to the optimal point can move along with the peak inductor current, and the efficiency of the converter is affected.
If the peak inductor current compared by the peak current comparator is not in the optimal peak inductor current state, the switching frequency after the dc converter is stabilized is not the switching frequency with optimal efficiency, and the overall efficiency difference may reach more than 10%.
Disclosure of Invention
The present invention aims to overcome the above-mentioned drawbacks of the prior art, and provides an adaptive adjustment circuit with optimal efficiency.
The technical purpose of the invention is realized by the following technical scheme:
the structure comprises: the self-adaptive peak inductor current circuit comprises a reference power supply circuit, a current sampling circuit, a self-adaptive peak inductor current circuit, a peak current comparator, a voltage comparator, a zero-crossing comparator, a main control module, an upper power tube MP, a lower power tube MN, an output circuit, a P driving circuit for controlling dead time and driving the upper power tube MP and an N driving circuit for controlling the dead time and driving the lower power tube MN;
the input port of the optimal efficiency self-adaptive adjusting circuit is used for inputting VIN signals, and the VIN signals are transmitted to the reference power supply circuit, the current sampling circuit, each input port of the self-adaptive peak inductance current circuit and a switch end of the upper power tube MP;
the upper power tube MP and the lower power tube MN are connected in series, the connected nodes are SW nodes, and the other switch end of the lower power tube MN is grounded;
the input end of the reference power supply circuit is connected with the VIN signal, and the output end of the reference power supply circuit is provided with a VREF port;
the VREF port outputs a reference voltage VREF to be provided to a reference voltage input end of the voltage comparator;
the input end of the current sampling circuit is respectively connected with the voltage signal and the VIN signal of the SW node, and the output end of the current sampling circuit outputs an ISEN signal and a VIMAX signal; the VIMAX signal is provided to the inverting input of the peak current comparator;
the self-adaptive peak inductance current circuit comprises an input port for respectively inputting an Vout signal, an ISET signal and an ISEN signal output by the current sampling circuit, and outputs a Viref signal to the homodromous input end of the peak current comparator; the output end of the peak current comparator outputs a Vp signal to the main control module;
the output circuit comprises an inductor L, a capacitor C, a load resistor RL, a first resistor R1 and a second resistor R2; the SW node is connected with the first end of the inductor L, and the second section of the inductor L is an output port of the self-adaptive adjusting circuit so as to output an Vout signal; the capacitor C is connected in parallel with the load resistor RL and then connected between the Vout signal and the ground, and the first resistor R1 and the second resistor R2 are connected in series and then connected between the Vout signal and the ground; the series node between the first resistor R1 and the second resistor R2 forms a feedback signal VFB;
the output end of the voltage comparator outputs a Vcom signal to the main control module; the non-inverting input end of the zero-crossing comparator is connected to the SW node, the inverting input end of the zero-crossing comparator is grounded, and the output end of the zero-crossing comparator is connected with the input end VZCD of the main control module.
One output end of the main control module drives the grid electrode of the upper power tube MP through a P driving circuit, and the other output end drives the grid electrode of the lower power tube MN through an N driving circuit.
Further, the adaptive peak inductor current circuit comprises a PTAT and current mirror circuit, a division amplifier and a V-I converter.
The input ends of the PTAT and the current mirror circuit are connected with an input port VIN, and the output of the PTAT drives a third power tube MP3 in the current mirror circuit; the third resistor R3 and the fourth resistor R4 are connected in series to divide the VIN signal and the ground, the first input end of the division amplifier is connected to the divided voltage VIN', and the second input end of the division amplifier is connected with the signal Vout; the output end of the division amplifier is connected with the V-I converter module; the input end of the V-I converter is connected with VIN; the bias current Ibias of the current mirror circuit, the output end output current ID of the V-I converter and the output ISEN of the current sampling current are added and then converted into voltage VIREF to be output through a fifth resistor R5.
Further, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are all adjustable resistors.
Further, the division amplifier includes: a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a multiplier, and an OP amplifier; one end of the sixth resistor R6 is connected with the voltage division Vin', and the other end of the sixth resistor R6 is connected with the inverting input end of the OP amplifier; the output end of the multiplier is connected to the inverting input end of the OP amplifier through a seventh resistor R7, one input end of the multiplier is connected with the Vout signal, the other end of the multiplier is connected with the output end of the OP amplifier and one input end of the V-I converter, and the node signal is a V signal; and the non-inverting input end of the OP amplifier is grounded through an eighth resistor R8.
Further, the V-I converter includes: fourth power tube MP4, fifth power tube MP5 and sixth power tube MN6, and ninth resistor R9, operational amplifier;
the grid electrodes of the fourth power tube MP4 and the fifth power tube MP5 are connected together and are in short circuit with a switch end of the fourth power tube MP 4; the other switch ends of the fourth power tube MP4 and the fifth power tube MP5 are connected with VIN signals, and the remaining switch ends of the fifth power tube MP5 form an output end of the V-I converter to output converted current ID;
the non-inverting input end of the operational amplifier inputs a V signal, the inverting input end of the operational amplifier is connected with a switch end of the sixth power tube MN6, and the output end of the operational amplifier is connected with the grid electrode of the sixth power tube MN 6; one switch end of the sixth power tube MN6 is connected to the other switch end of the fourth power tube MP4, and the other switch end is grounded through a ninth resistor R9.
By the technical scheme, the invention has the technical effects that the self-adaptive peak inductance current circuit is introduced into the input end of the peak current comparator, the threshold voltage of the peak current comparator is formed by checking the influence of the change of input voltage, the ripple of output voltage and the process and temperature drift, and the peak inductance current is regulated in a self-adaptive way, so that the optimization of the converter efficiency is obtained.
Drawings
The invention will be further described with reference to the accompanying drawings, in which embodiments do not constitute any limitation of the invention, and other drawings can be obtained by one of ordinary skill in the art without inventive effort from the following drawings.
Fig. 1 is a circuit diagram of a conventional hysteretic dc converter;
FIG. 2 is a circuit diagram of a hysteretic DC converter of the present invention;
FIG. 3 is a circuit diagram of an adaptive peak inductor current of the present invention;
FIG. 4 is a circuit diagram of a division amplifier in the adaptive peak inductor current circuit of the present invention of FIG. 3;
fig. 5 is a circuit diagram of a V-I converter in the adaptive peak inductor current circuit of the present invention of fig. 3.
Detailed Description
The following description of the embodiments of the present invention will be given with reference to the accompanying drawings, in which the technical solutions of the present invention are clearly and completely described, but the present invention is not limited to the following embodiments. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. Advantages and features of the invention will become more apparent from the following description and from the claims. It is noted that the drawings are in a very simplified form and use non-precise ratios for convenience and clarity in assisting in illustrating embodiments of the invention. All other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present invention.
This invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for the same elements throughout. In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The invention will be further described with reference to the following examples.
The embodiment of the invention suitable for the optimal efficiency self-adaptive adjustment circuit of the hysteresis direct-current voltage converter is shown in fig. 2, and the main modules comprise a reference power supply circuit, a current sampling circuit, a self-adaptive peak inductance current circuit, a peak current comparator, a voltage comparator, a zero-crossing comparator, a main control module, an upper power tube MP, a lower power tube MN, an output circuit, a P driving circuit for controlling dead time and driving the upper power tube and an N driving circuit for controlling the dead time and driving the lower power tube.
An input port is arranged at one switch end of the upper power tube MP to input a signal VIN; the other switch end of the upper power tube MP is connected with one switch end of the lower power tube MN; the other switch end of the lower power tube MN is grounded to GND; a connection node SW is arranged between the upper power tube MP and the lower power tube MN.
The output circuit includes an inductance L, an output capacitance Cout, and resistors RL, R1, and R2. The node SW is connected with the inductor L and the resistors R1 and R2 which are connected in series, and the output capacitor Cout and the load resistor RL are connected in parallel and connected between the output Vout and the ground in a bridging way; the node between the resistors R1 and R2 forms the feedback signal VFB.
The input end of the voltage comparator is respectively connected with the feedback signal VFB and the output voltage VREF of the reference power supply circuit, wherein the non-inverting input end of the voltage comparator is connected with the voltage VREF, and the inverting input end of the voltage comparator is connected with the feedback signal VFB. The output end of the voltage comparator is connected with the input end of the main control module to input the Vcom signal.
The input end of the zero-crossing comparator is respectively connected with the port GND and the node SW; the output end of the zero-crossing comparator is connected with the input end of the main control module to output a signal VZCD; the output end of the main control module is respectively connected with the P driving module and the N driving module, namely a P driving circuit for controlling dead time and driving the upper power tube and an N driving circuit for controlling the dead time and driving the lower power tube.
An adaptive peak inductor circuit for a hysteretic dc converter according to this embodiment, as shown in fig. 3, includes a PTAT and current mirror circuit, a division amplifier module, a V-I converter module, and an output module.
The input end of the self-adaptive peak inductance current circuit is respectively connected with the signal current ISET, the output current ISEN of the current sampling circuit, the input signal VIN and the output signal VOUT; the output end VIREF of the self-adaptive peak inductive current circuit is connected with the peak current comparator; and the output end VP of the peak current comparator is connected with the main control module.
In the embodiment, the self-adaptive peak inductor current circuit is introduced into the input end of the peak current comparator, and the threshold voltage of the peak current comparator is formed by checking the influence of the input voltage change, the ripple wave of the output voltage and the process and the temperature drift, so that the peak inductor current is regulated in a self-adaptive manner, and the optimization of the converter efficiency is obtained.
The input ends of the PTAT and the current mirror circuit are connected with an input signal VIN; the input end of the division amplifier is connected with the output signal VOUT and the input signal VIN after being divided by the adjustable resistors R3 and R4, and the node where the adjustable resistors R3 and R4 are connected is divided by VIN'; the output end of the division amplifier is connected with the V-I converter and outputs voltage V; the other input end of the V-I converter is connected with an input signal VIN; the PTAT and current mirror circuit, the dividing amplifier, the V-I converter and the output ISEN of the current sampling current are added and then converted into voltage VIREF output through an adjustable resistor R5.
Fig. 4 and 5 are internal block diagrams of the division amplifier and the V-I converter, respectively, in the adaptive peak inductor current circuit of fig. 3. The division amplifier includes: a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a multiplier, and an OP amplifier; one end of the sixth resistor R6 is connected with the voltage division Vin', and the other end of the sixth resistor R6 is connected with the inverting input end of the OP amplifier; the output end of the multiplier is connected to the inverting input end of the OP amplifier through a seventh resistor R7, one input end of the multiplier is connected with the Vout signal, the other end of the multiplier is connected with the output end of the OP amplifier and one input end of the V-I converter, and the node signal is a V signal; the output signal of the multiplier is V', and the non-inverting input end of the OP amplifier is grounded through an eighth resistor R8.
The V-I converter includes: fourth power tube MP4, fifth power tube MP5 and sixth power tube MN6, and ninth resistor R9 and operational amplifier. The V-I converter converts the output voltage V of the dividing amplifier into an output current ID.
When the circuit works, after the upper power tube MP is started, the current of the inductor L is linearly increased, and the time from the upper power tube MP to the peak value of the inductor current is taken as the conduction time of the upper power tube MP, so that the conduction time of the upper power tube MP can be generated through a peak current comparator to control the turn-off of the upper power tube MP. Firstly, the inductance current IL of the SW node is sampled, a smaller current ISEN=IL/K is output through a current sampling circuit, wherein K=2000 is a proportionality coefficient, and the inductance current IL can be obtained by adjusting the size proportion of a power tube and a mirror image tube in the current sampling circuit and is input into the self-adaptive peak inductance current circuit as a compensation signal. Because the peak inductance current is positively correlated with the input voltage VIN, the output voltage VOUT is negatively correlated, the input voltage VIN of the dividing amplifier is divided by the adjustable resistors R3 and R4, division operation is respectively realized with the output voltage VOUT, the output amplified voltage Vout is input into a V-I converter, the voltage V is converted into current ID through the V-I converter, and the magnitude of the current ID is adjusted by controlling the adjustable resistors R3 and R4 through the signal ISET. PTAT (Proportional To Absolute Temperature) the current source and the mirror circuit generate a stable bias current IBIAS to compensate the influence caused by temperature drift. The three currents ISEN, ID and IBIAS are added, and the output peak current comparator inputs a reference threshold voltage VIREF through an adjustable load resistor R5, and the magnitude of the reference threshold voltage VIREF is adjusted through a current ISET adjusting resistor R5. When the voltage of the SW node rises and the voltage of the SW node exceeds the threshold voltage VIREF, the peak voltage comparator outputs a signal VP to the main control module, the upper power tube MP is turned off through the P driving circuit, during the period, the self-adaptive peak inductance current circuit output VIREF reduces the magnitude of the threshold value VIREF of the peak current comparator according to the increase of the output voltage VOUT, the turnover of the comparator is accelerated, and the efficiency of the converter is improved.
Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. An optimal efficiency self-adaptive adjusting circuit suitable for a hysteresis direct current voltage converter is characterized in that: the self-adaptive peak inductor current circuit comprises a reference power supply circuit, a current sampling circuit, a self-adaptive peak inductor current circuit, a peak current comparator, a voltage comparator, a zero-crossing comparator, a main control module, an upper power tube MP, a lower power tube MN, an output circuit, a P driving circuit for controlling dead time and driving the upper power tube MP, and an N driving circuit for controlling the dead time and driving the lower power tube MN;
the input port of the optimal efficiency self-adaptive adjusting circuit is used for inputting VIN signals, and the VIN signals are transmitted to the reference power supply circuit, the current sampling circuit, each input port of the self-adaptive peak inductance current circuit and a switch end of the upper power tube MP;
the upper power tube MP and the lower power tube MN are connected in series, the connected nodes are SW nodes, and the other switch end of the lower power tube MN is grounded;
the input end of the reference power supply circuit is connected with the VIN signal, and the output end of the reference power supply circuit outputs reference voltage VREF;
the reference voltage VREF is provided for a reference voltage input end of the voltage comparator, and an inverting input end of the voltage comparator inputs a feedback signal VFB;
the input end of the current sampling circuit is respectively connected with the voltage signal and the VIN signal of the SW node, and the output end of the current sampling circuit outputs an ISEN signal and a VIMAX signal; the VIMAX signal is provided to the inverting input of the peak current comparator;
the self-adaptive peak inductance current circuit comprises an input port for respectively inputting an Vout signal, an ISET signal and an ISEN signal output by the current sampling circuit, and outputs a Viref signal to the homodromous input end of the peak current comparator; the output end of the peak current comparator outputs a Vp signal to the main control module;
the output circuit comprises an inductor L, a capacitor C, a load resistor RL, a first resistor R1 and a second resistor R2; the SW node is connected with the first end of the inductor L, and the second section of the inductor L is an output port of the self-adaptive adjusting circuit so as to output an Vout signal; the capacitor C is connected in parallel with the load resistor RL and then connected between the Vout signal and the ground, and the first resistor R1 and the second resistor R2 are connected in series and then connected between the Vout signal and the ground; the series node between the first resistor R1 and the second resistor R2 forms a feedback signal VFB;
the output end of the voltage comparator outputs a Vcom signal to the main control module; the non-inverting input end of the zero-crossing comparator is connected to the SW node, the inverting input end of the zero-crossing comparator is grounded, and the output end of the zero-crossing comparator is connected with the input end VZCD of the main control module;
one output end of the main control module drives the grid electrode of the upper power tube MP through a P driving circuit, and the other output end drives the grid electrode of the lower power tube MN through an N driving circuit.
2. The optimum efficiency adaptive adjustment circuit for a hysteretic dc voltage converter of claim 1 wherein: the self-adaptive peak inductance current circuit comprises a PTAT (positive temperature coefficient) and current mirror circuit, a division amplifier and a V-I (voltage-to-current) converter;
the input ends of the PTAT and the current mirror circuit are connected with an input port VIN, and the output of the PTAT drives a third power tube MP3 in the current mirror circuit; the third resistor R3 and the fourth resistor R4 are connected in series to divide the VIN signal and the ground, the first input end of the division amplifier is connected to the divided voltage VIN', and the second input end of the division amplifier is connected with the signal Vout; the output end of the division amplifier is connected with the V-I converter module; the input end of the V-I converter is connected with VIN; the bias current Ibias of the current mirror circuit, the output end output current ID of the V-I converter and the output ISEN of the current sampling current are added and then converted into voltage VIREF to be output through a fifth resistor R5.
3. The optimum efficiency adaptive adjustment circuit for a hysteretic dc voltage converter of claim 2 wherein: the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are all adjustable resistors.
4. The optimum efficiency adaptive adjustment circuit for a hysteretic dc voltage converter of claim 2 wherein: the division amplifier includes: a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a multiplier, and an OP amplifier; one end of the sixth resistor R6 is connected with the voltage division Vin', and the other end of the sixth resistor R6 is connected with the inverting input end of the OP amplifier; the output end of the multiplier is connected to the inverting input end of the OP amplifier through a seventh resistor R7, one input end of the multiplier is connected with the Vout signal, the other end of the multiplier is connected with the output end of the OP amplifier and one input end of the V-I converter, and the node signal is a V signal; and the non-inverting input end of the OP amplifier is grounded through an eighth resistor R8.
5. The optimum efficiency adaptive adjustment circuit for a hysteretic dc voltage converter of claim 2 wherein: the V-I converter includes: fourth power tube MP4, fifth power tube MP5 and sixth power tube MN6, and ninth resistor R9, operational amplifier;
the grid electrodes of the fourth power tube MP4 and the fifth power tube MP5 are connected together and are in short circuit with a switch end of the fourth power tube MP 4; the other switch ends of the fourth power tube MP4 and the fifth power tube MP5 are connected with VIN signals, and the remaining switch ends of the fifth power tube MP5 form an output end of the V-I converter to output converted current ID;
the non-inverting input end of the operational amplifier inputs a V signal, the inverting input end of the operational amplifier is connected with a switch end of the sixth power tube MN6, and the output end of the operational amplifier is connected with the grid electrode of the sixth power tube MN 6; one switch end of the sixth power tube MN6 is connected to the other switch end of the fourth power tube MP4, and the other switch end is grounded through a ninth resistor R9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311829075.6A CN117792092A (en) | 2023-12-28 | 2023-12-28 | Optimal efficiency self-adaptive adjusting circuit suitable for hysteresis direct-current voltage converter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311829075.6A CN117792092A (en) | 2023-12-28 | 2023-12-28 | Optimal efficiency self-adaptive adjusting circuit suitable for hysteresis direct-current voltage converter |
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| CN117792092A true CN117792092A (en) | 2024-03-29 |
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| CN202311829075.6A Pending CN117792092A (en) | 2023-12-28 | 2023-12-28 | Optimal efficiency self-adaptive adjusting circuit suitable for hysteresis direct-current voltage converter |
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| CN (1) | CN117792092A (en) |
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- 2023-12-28 CN CN202311829075.6A patent/CN117792092A/en active Pending
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