CN117790533A - High-power small-package TVS device and preparation method thereof - Google Patents

Abstract

The main purpose of the present invention is to design a high-power small-package TVS device and a preparation method thereof. Its structure is that the cathode and anode are on the same side and suitable for CSP-packaged TVS diodes with transistor clamps. This TVS integrates transistors and zener diodes. Integrated with the resistor, the avalanche current of the Zener diode triggers the transistor so that it can conduct a large current; the resistor size is adjusted so that it does not produce a large negative resistance breakdown, and the clamping voltage is guaranteed to be above the working voltage. The preparation method includes manufacturing a transistor with a resistor and a voltage regulator, and bringing the collector of the transistor to the upper surface, which is suitable for CSP packaging; adjusting the resistor is formed on the upper surface, which can accurately control the breakdown voltage of the transistor; using the relatively shallow diffusion on the back of a single wafer A high-concentration collector layer and bonded support wafer replace the epitaxial wafer.

Description

A high-power small package TVS device and its preparation method

Technical field

The invention belongs to the technical field of the design and preparation of semiconductor power device TVS, and in particular relates to a high-power small-package TVS device and its preparation method, which is suitable for CSP packaging, conducts large currents, and does not produce large negative resistance breakdown. TVS. At the same time, bonded diffusion sheets are used to replace epitaxial wafers to reduce costs.

Background technique

TVS diodes are widely used in the protection of electronic circuits. They are usually connected in parallel to the components to be protected. When external high pulse voltages, such as lightning strikes and static electricity (ESD), pass through, they can quickly discharge their current and maintain the voltage at Lower level to avoid high voltage damage to components. With the miniaturization of circuits, the frequency of use is getting higher and higher, and the speed is getting faster and faster. The capacitance of the external TVS must also be smaller and smaller, otherwise it will reduce the frequency of the entire circuit and increase losses; at the same time, the miniaturization of electronic products The trend requires supporting electronic devices to be both high-power and miniaturized.

There are usually two major types of ESD clamping structures used for TVS protection devices. The first type is reverse-biased PN junction diodes. This type of structure is simple to manufacture, has fast response speed, and has no negative breakdown resistance. The disadvantage is that there is a large voltage drop due to the existence of a high-resistance area and no conductance modulation mechanism. When clamping a large current, there is a large voltage rise, resulting in an increase in the power dissipation of the device; the Type 2 TVS structure includes The thyristor SCR structure triggered by CMOS or bipolar transistor. Due to the conductance modulation mechanism of this structure, in the clamping state, the voltage can be kept at a low level when passing a large current; the disadvantage is that it will produce a large negative resistance effect and the clamp The bit voltage is greatly reduced, and additional resistors need to be added to the external circuit. At the same time, the manufacturing process is also complicated.

In order to effectively reduce the shortcomings of the first two categories, a structure including a clamping diode, a transistor and a resistor is proposed, as shown in the circuit diagram in Figure 1. In this structure, when the voltage exceeds the reverse breakdown voltage of the voltage regulator tube, the voltage regulator tube conducts It can pass through and clamp the voltage; at the same time, the current generated by the breakdown triggers the transistor to conduct. Due to the conductance modulation effect caused by the injection of minority carriers, the conduction voltage drop is reduced, which can reduce the significant increase in the clamping voltage when clamping a large current. . Since there is an on-resistance between the base and the emitter, the clamping voltage drop caused by the large negative resistance effect is avoided. The chip cross-section is shown in Figure 2. By adjusting the resistivity and thickness of the N-region of the epitaxial layer, the resistance reaches an appropriate value to ensure that the negative resistance is not too large and the clamping voltage is guaranteed to be above the operating voltage.

This structure adjusts the size of the resistance by adjusting the concentration and thickness of the N-epitaxial layer. Because the epitaxial layer also affects the breakdown voltage, current amplification factor, and capacitance of the device, it is very difficult to achieve balanced optimization of multiple parameters. .

CSP chip scale packages are smaller and thinner. This structure requires the electrodes to be on the same side. The above structure is suitable for the packaging of upper and lower electrodes, but is not suitable for smaller CSP packaging forms.

Contents of the invention

The main purpose of the present invention is to design a high-power small-package TVS device and its preparation method. Its structure is that the cathode and anode are on the same side and suitable for CSP-packaged TVS diodes with transistor clamps. This TVS integrates transistors and zener diodes. Integrated with the resistor, the avalanche current of the zener diode triggers the transistor so that it can conduct a large current; the resistor size is adjusted so that it does not produce a large negative resistance breakdown.

The manufacturing method includes manufacturing a transistor with a resistor and a voltage regulator, and bringing the collector of the transistor to the upper surface, which is suitable for CSP packaging; adjusting the resistor is formed on the upper surface, which can accurately control the breakdown voltage of the transistor; using a single wafer with relatively shallow back diffusion A high-concentration collector layer and bonded support wafer replace the epitaxial wafer.

As shown in Figure 1, a Zener diode is integrated at the base and collector. When a negative voltage is applied to the emitter and the voltage exceeds the reverse breakdown voltage peak of the Zener diode, the Zener diode is turned on, and the on-current passes through the base region to form a base resistance. When the resistance is greater than 0.6V (the threshold voltage of the emitter region-base region), the emitter will inject minority carriers, which pass through the base region and reach the collector, forming a minority carrier injection effect, reducing the resistivity of the collector region, thereby reducing the on-resistance and forming a large on-current.

As shown in Figure 5, if only the voltage regulator tube with PN junction structure has reverse breakdown, as the reverse current increases, the voltage also increases, and the amplitude is larger, as shown in the figure of the voltage regulator tube curve; for triodes , if the transistor has an open circuit between EB, or the resistance between EB is very large, a large negative resistance phenomenon will be formed, such as VCER1; if CE is short-circuited, the curve will be like VCES; if the resistance between CE is appropriate, the ideal characteristics as shown in the figure can be achieved , the breakdown voltage is lower than the voltage regulator tube breakdown voltage and higher than the operating voltage.

The structural cross-sectional view of the present invention is shown in Figure 3. A heavily doped first conductive type layer is formed around the edges and bottom of a lightly doped first conductive type semiconductor chip, and a heavily doped first conductive type layer is partially formed on the upper part of the chip. A conductive type layer, a heavily doped second conductive type layer is formed around the heavily doped first conductive type layer, and a lightly doped first conductive type layer is formed around the heavily doped second conductive type layer. A doped second conductive type layer, the heavily doped second conductive type layer is locally connected to the lightly doped second conductive type layer, where the lightly doped second conductive type layer and the edge heavily doped second conductive type layer Between the conductive type layers is a lightly doped first conductive type layer. The heavily doped first conductive type layer is metallically connected to the lightly doped second conductive type layer on the upper surface through a local second conductive type layer. , the lightly doped second conductive type layer on the upper surface is connected to the heavily doped second conductive type layer in the base region on the other side; the heavily doped first conductive type layer on the upper surface and the surrounding heavily doped A lightly doped second conductive type layer is formed below the second conductive type layer, and any type of silicon wafer is bonded to the bottom of the substrate as a supporting layer.

In this example, the first conductivity type layer is N type, and the second conductivity type layer is P type, and vice versa.

The N+ region is diffused on the back of the N-type single chip as the collector area of the transistor. However, if the diffusion depth is too deep, it will take a long time and waste efficiency. The diffusion depth is shallow. Since the silicon wafer is thin, it is easy to be processed in the subsequent process. Chips are generated. In order to avoid chipping of the silicon wafer with a shallow diffusion depth, a support piece is bonded on the back side.

An N+ area is diffused in the edge area of the chip, connected to the N+ area of the collector area, and leads the current from the collector area to the front as an anode.

N+ is locally diffused on the upper surface as the emitter of the transistor and is also the cathode of this TVS. The voltage regulator tube diffuses concentrated boron around the N+ area of the cathode to form an N+P+ junction. The P+ concentration is determined according to the required voltage value of the voltage regulator tube. , a P- region is formed below the emitter region N+ and the voltage regulator region P+ on the N- region as the triode base region.

The P-type area is diffused on the upper surface as the inter-EB resistance. The P-type area connects the base area P+ area and the emitter area. The emitter area and the P-type area are connected through metal. According to the required resistance value, the strip width, strip length and concentration are coordinated, such as strip The width and strip length are determined, and the concentration can be easily adjusted to achieve the designed resistance value.

Metal layers are deposited on the cathode and anode areas. The metal is based on the requirements of CSP packaging, such as AL, TiNiAg, Au, etc. The outside of the metal is isolated by an insulating layer such as SiO2.

FIG4 is a schematic diagram of the chip layout. Of course, the layout can be changed into a comb shape, a grid shape, etc.

The N and P regions in the structure are interchangeable.

The distance from the side surface of the base region to the edge N+ region is greater than the distance from the bottom surface of the base region to the collector region N+.

The TVS manufacturing steps of the present invention include:

Take the N-type single crystal wafer→double-sided diffusion N+ area→bonding support sheet→positive film thinning and polishing→field oxidation→photolithography N+ area→diffusion N+ area→photolithography base area→diffusion P-base area→photolithography cathode N+ Area → Diffusion N+ area → Photolithography P+ area → Diffusion P+ area → Photolithography P-type area → Diffusion P-type area → Photolithography lead hole → Deposit metal → Photolithography metal → Test

The present invention uses a bonding diffusion sheet to replace the epitaxial sheet, thereby reducing the cost.

Picture description:

Figure 1 Schematic diagram of TVS with clamping Zener diode.

Figure 2 is a previously disclosed cross-sectional view.

Figure 3 is a cross-sectional view of the present invention,

Figure 4 is a schematic diagram of the layout of the present invention,

Figure 5 I-V curve.

Detailed ways

The present invention will be further described below through specific examples, but the examples do not limit the scope of the present invention.

Example - Taking a product with an operating voltage of 5V as an example, the TVS clamping voltage is designed to be 7V.

Chip area is 0.6mmx0.3mm, 8 times photolithography

Single crystal ρ: 5Ω.cm, thickness 300um, N type

N+ area R□<0.02Ω/□, junction depth: 50um

Support piece 300um, resistivity not included

After polishing, N-thickness is 15um, base area is ion implanted with boron, R□=90Ω/□, junction depth: 10um

Concentrated boron P+: R□=8Ω/□, junction depth: 5um

N+ cathode area: R□=0.5Ω/□, junction depth: 6um

Resistance P-type area: R□=120Ω/□, junction depth: 4um

Results: TVS turns at 42mA, negative resistance ΔV<0.5V, zero bias capacitance 8PF.

Judging from the results, the power capability per unit area has obvious advantages, and the negative resistance is completely controllable.

At the same time, using diffusion bonded wafers instead of epitaxial wafers is more cost-effective.

The chip electrodes are on the same side, which is suitable for CSP packaging and makes the device smaller.

Of course, those of ordinary skill in the art should realize that the above embodiments are only used to illustrate the present invention and are not intended to limit the present invention. As long as the above embodiments are within the scope of the essential spirit of the present invention, All changes and deformations will fall within the scope of the claims of the present invention.

Claims (13)

1. A high-power small package TVS device, the structure of which includes: forming a heavily doped first conductive type layer around the edges and bottom of a lightly doped first conductive type semiconductor chip, and forming a heavily doped layer on the upper part of the chip. A first conductivity type layer, a heavily doped second conductivity type layer is formed around the heavily doped first conductivity type layer, and a lightly doped first conductivity type layer is formed around the heavily doped second conductivity type layer. Type forms a lightly doped second conductive type layer, the heavily doped second conductive type layer is locally connected to the lightly doped second conductive type layer, where the lightly doped second conductive type layer and the edge are heavily doped Between the doped first conductive type layers is a lightly doped first conductive type layer. The heavily doped first conductive type layer and the lightly doped second conductive type layer on the upper surface pass through a local second conductive type layer. A metal connection is formed, and the lightly doped second conductive type layer on the upper surface is connected to the heavily doped second conductive type layer of the base region on the other side; the heavily doped first conductive type layer on the upper surface and the surrounding A lightly doped second conductive type layer is formed below the heavily doped second conductive type layer, and any type of silicon wafer is used as a supporting layer at the bottom of the substrate. 2. The device according to claim 1 is characterized in that the back side of the single crystal wafer of the lightly doped first conductive type layer is a heavily doped first conductive type layer region as the collector region of the transistor, the thickness of the collector region is less than 150 microns, and there is any type of silicon wafer as a supporting layer at the bottom of the substrate. 3. The device according to claim 1, characterized in that a heavily doped first conductive type layer is diffused in the edge area of the chip, connected to the collector area, and the current in the collector area is led to the front side as an anode. . 4. The device according to claim 1, characterized in that the locally diffused heavily doped first conductive type layer region on the upper surface serves as the emitter of the transistor and is also the cathode of the TVS, and the voltage stabilizing tube passes around the cathode region. Diffuse the heavily doped second conductive type layer region to form an N+P+ junction. The concentration of the heavily doped second conductive type layer region is determined according to the voltage value required by the voltage regulator tube. In the lightly doped first conductive type layer A lightly doped second conductive type layer region is formed below the heavily doped second conductive type layer region in the upper emitter region and the voltage stabilizing tube region as a triode base region. 5. The device according to claim 1, characterized in that, a lightly doped second conductivity type layer region is diffused on the upper surface as a resistor between the transistor emitter base and EB, and the lightly doped second conductivity type layer region is connected The base region and the emitter region, the emitter region and the lightly doped second conductivity type layer region are connected through metal. 6. The device of claim 1, wherein metal layers are deposited on the cathode and anode regions. 7. A method for preparing a high-power small-package TVS device. The steps include: diffusing a high-concentration area of the first impurity layer on the back of a low-concentration single-wafer of the first impurity layer as the collector area of the transistor. In order to ensure that the silicon wafer is It is not easy to fragment during the processing, and the support sheet is bonded on the back; a high-concentration area of the first impurity layer is diffused in the edge area of the chip, which is connected to the high-concentration area of the first impurity layer in the collector area, and leads the current in the collector area to The front side serves as the anode; a triode is formed using standard processes, and an N+P+ junction is formed by diffusing the high-concentration area of the second impurity layer around the high-concentration area of the first impurity layer of the cathode (emitter) to form a voltage regulator tube. The low-concentration second impurity type region is diffused as the inter-EB resistance. The low-concentration second impurity region connects the second impurity high-concentration region and the cathode (emitter) region. A metal layer is deposited on the cathode and anode regions. The metal layer of the cathode Connect P+/N+ together, and the outside of the metal is isolated by an insulating layer. 8. The device manufacturing method according to claim 7, characterized in that the silicon wafer used in the low concentration layer of the first impurity layer is a single crystal silicon wafer. 9. The device preparation method according to claim 7, wherein the triode collector region is formed by diffusing a high concentration of first-type impurities, and the diffusion junction depth is less than 150 microns. 10. The device manufacturing method according to claim 7, characterized in that the support layer below the triode is formed by directly bonding any type of silicon wafers. 11. The device preparation method according to claim 7, characterized in that the resistance value between EBs is determined by the implanted boron (phosphorus) ion concentration and diffusion depth. 12. The device manufacturing method according to claim 7, characterized in that the collector region of the triode is introduced to the upper surface by diffusing high concentrations of the same type of impurities. 13. The device manufacturing method according to claim 7, wherein the voltage of the voltage regulator tube is determined by the concentration of the high-concentration second impurity type region around the emitter.