CN117790328A

CN117790328A - Semiconductor packaging structure and packaging method

Info

Publication number: CN117790328A
Application number: CN202211152968.7A
Authority: CN
Inventors: 杨威源
Original assignee: SIPLP Microelectronics Chongqing Ltd
Current assignee: SIPLP Microelectronics Chongqing Ltd
Priority date: 2022-09-21
Filing date: 2022-09-21
Publication date: 2024-03-29

Abstract

The invention provides a semiconductor packaging structure and a packaging method, wherein a side wall conductive structure and a filling structure adjacent to the side wall conductive structure are formed on a carrier plate, and then the filling structure is removed by etching to expose the side wall of the side wall conductive structure, so that no extra equipment is required to expose the side wall of the side wall conductive structure, and the manufacturing cost can be reduced. Further, the filling structure is removed through etching to expose the side wall conductive structure, the process is simple and convenient and easy to control, and accordingly the quality and reliability of the semiconductor packaging process are improved.

Description

Semiconductor packaging structure and packaging method

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging structure and a packaging method.

Background

Currently, flat leadless packages provide near-chip scale packages that include sidewall conductive structures. In many cases, a land (also referred to as an outer lead) on the bottom surface of the package structure and a sidewall conductive structure on the side of the package structure provide electrical connection to another device or board, such as a Printed Circuit Board (PCB). Specifically, using Surface Mount Technology (SMT), the package structure is directly mounted on the surface of the PCB.

In the current board-level fan-out package, the sidewalls of the sidewall conductive structures are finally exposed, typically by mechanical cutting or drilling. The mechanical cutting has huge loss on the cutter, and the manufacturing cost is increased; the drilling is not easy to grasp the hole depth, the reliability of the process is reduced, or more manufacturing procedures or detecting procedures are needed, and the manufacturing cost is increased.

Therefore, how to optimize the semiconductor packaging process is a problem to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide a semiconductor packaging structure and a packaging method, which are used for solving the problems of higher cost or lower reliability of semiconductor packaging in the prior art.

In order to achieve the above object, the present invention provides a semiconductor packaging method comprising:

providing a carrier plate, and forming a side wall conductive structure and a filling structure adjacent to the side wall conductive structure on the carrier plate;

adhering a semiconductor bare chip on the carrier plate;

forming a rewiring structure on the semiconductor die to electrically connect the semiconductor die and the sidewall conductive structures; the method comprises the steps of,

and etching to remove the filling structure and expose the side wall of the side wall conductive structure.

Optionally, in the semiconductor packaging method, the materials of the side wall conductive structure and the filling structure are metal, and the materials of the lead frame structure and the filling structure are different.

Optionally, in the semiconductor packaging method, forming a sidewall conductive structure and a filling structure adjacent to the sidewall conductive structure on the carrier includes:

forming at least one side wall conducting layer on the carrier plate; the method comprises the steps of,

forming at least one filling layer on the carrier plate, wherein the number of layers of the filling layer is the same as that of the side wall conductive layers, and each filling layer is adjacent to the corresponding side wall conductive layer;

wherein the sidewall conductive structures include each of the sidewall conductive layers, and the fill structures include each of the fill layers.

Optionally, in the semiconductor packaging method, a plurality of side wall conductive layers are formed on the carrier, and outer side walls of at least two side wall conductive layers are staggered.

Optionally, in the semiconductor packaging method, a plurality of side wall conductive layers and a plurality of filling layers are formed on the carrier, each side wall conductive layer is in direct contact with the previous side wall conductive layer and has an overlapping area, and each filling layer is in direct contact with the previous filling layer and has an overlapping area.

Optionally, in the semiconductor packaging method, the at least one sidewall conductive layer includes a first sidewall conductive layer, and forming the first sidewall conductive layer on the carrier includes:

forming a first barrier layer on the carrier plate, wherein the first barrier layer is provided with a first opening, and part of the carrier plate is exposed out of the first opening; the method comprises the steps of,

the first sidewall conductive layer is formed in the first opening.

Optionally, in the semiconductor packaging method, the at least one filling layer includes a first filling layer;

forming the first filling layer on the carrier plate comprises:

removing a part of the first side wall conductive layer adjacent to the outer side wall of the first opening to form a first filling opening, wherein the first filling opening exposes a part of the carrier plate; the method comprises the steps of,

forming the first filling layer in the first filling port;

alternatively, forming the first filling layer on the carrier plate includes:

removing a portion of the first barrier layer adjacent to the outer sidewall of the first opening to form a first filling opening, wherein a portion of the carrier plate is exposed by the first filling opening; the method comprises the steps of,

and forming the first filling layer in the first filling port.

Optionally, in the semiconductor packaging method, the at least one sidewall conductive layer further includes a second sidewall conductive layer located on the first sidewall conductive layer, the second sidewall conductive layer being in direct contact with the first sidewall conductive layer and having an overlapping region, and after the first filling layer is formed, the second sidewall conductive layer is formed, and the forming method of the second sidewall conductive layer includes:

forming a second barrier layer on the first barrier layer, wherein the second barrier layer is provided with a second opening, and the second opening at least exposes part of the first side wall conductive layer; the method comprises the steps of,

the second sidewall conductive layer is formed in the second opening.

Optionally, in the semiconductor packaging method, the at least one filling layer further includes a second filling layer located on the first filling layer, and the second filling layer is in direct contact with the first filling layer and has an overlapping area;

the forming method of the second filling layer comprises the following steps:

removing a portion of the second sidewall conductive layer adjacent to the outer sidewall of the second opening to form a second fill opening, the second fill opening exposing at least a portion of the first fill layer; the method comprises the steps of,

Forming the second filling layer in the second filling port;

alternatively, the forming method of the second filling layer includes:

removing a portion of the second barrier layer adjacent to the outer sidewall of the second opening to form a second fill opening, the second fill opening exposing at least a portion of the first fill layer; the method comprises the steps of,

and forming the second filling layer in the second filling port.

Optionally, in the semiconductor packaging method, forming a rewiring structure on the semiconductor die to electrically connect the semiconductor die and the sidewall conductive structure, including: the rewiring structure exposes the filling structure.

Optionally, in the semiconductor packaging method, forming a rewiring structure on the semiconductor die to electrically connect the semiconductor die and the sidewall conductive structure, including:

forming a rewiring layer on the semiconductor bare chip, wherein the rewiring layer is electrically connected with the semiconductor bare chip and the side wall conductive structure;

forming a dielectric layer on the semiconductor bare chip, wherein the dielectric layer exposes part of the rewiring layer;

forming an outer pin on the exposed rewiring layer; the method comprises the steps of,

A portion of the rewiring structure is removed to expose the filling structure.

and removing part of the dielectric layer to expose the filling structure.

Optionally, in the semiconductor packaging method, before forming the sidewall conductive structure and the filling structure adjacent to the sidewall conductive structure on the carrier, the semiconductor packaging method further includes:

forming an adhesion layer on the carrier plate; the method comprises the steps of,

forming a seed layer on the adhesion layer;

the side wall conductive structure and the filling structure are formed on the seed layer.

The invention also provides a semiconductor packaging structure formed by the semiconductor packaging method, which comprises the following steps: a semiconductor die, a sidewall conductive structure, and a rewiring structure electrically connecting the semiconductor die and the sidewall conductive structure.

Optionally, in the semiconductor packaging structure, the side wall conductive structure includes multiple side wall conductive layers, and outer side walls of at least two side wall conductive layers are staggered.

In the semiconductor packaging structure and the packaging method provided by the invention, the side wall conductive structure and the filling structure adjacent to the side wall conductive structure are formed on the carrier plate, and the filling structure is removed by etching to expose the side wall of the side wall conductive structure, so that no extra equipment is required to expose the side wall of the side wall conductive structure, and the manufacturing cost can be reduced. Further, the filling structure is removed through etching to expose the side wall conductive structure, the process is simple and convenient and easy to control, and accordingly the quality and reliability of the semiconductor packaging process are improved.

Drawings

Fig. 1 is a flow chart of a semiconductor packaging method according to an embodiment of the invention.

Fig. 2 to 17 are schematic views illustrating a process of performing a semiconductor packaging method according to a first embodiment of the present invention to form a semiconductor package structure.

Fig. 18 to 36 are schematic views illustrating a process of performing a semiconductor packaging method according to a second embodiment of the present invention to form a semiconductor package structure.

Wherein reference numerals are as follows:

in fig. 2 to 17, 100-carrier plate; 110-an adhesion layer; 120-a first barrier layer; 130-a first opening; 140-a first sidewall conductive layer; 150-a first fill port; 160-a first filler layer; 170-a second barrier layer; 180-a second opening; 190-a second sidewall conductive layer; 200-a second fill port; 210-a second filling layer; 220-sidewall conductive structures; 230-filling the structure; 240-accommodating space; 250-semiconductor die; 260-plastic sealing layer; 270-rewiring structure; 271-a rewiring layer; 272-outer pins; 280-dielectric layer.

In fig. 18 to 36, 300-carrier plate; 310-an adhesion layer; 320-seed layer; 330-a first barrier layer; 340-a first opening; 350-a first sidewall conductive layer; 360-a first fill port; 370-a first filling layer; 380-a second barrier layer; 390-second opening; 400-a second sidewall conductive layer; 410-a second fill port; 420-a second filler layer; 430-sidewall conductive structures; 440-filling the structure; 450-accommodating space; 460-semiconductor die; 470-plastic sealing layer; 480-rewiring structure; 481-rewiring layer; 482-outer pins; 483—a first dielectric layer; 484-third fill port; 485-a third filling layer; 486-second dielectric layer.

Detailed Description

The semiconductor packaging structure and the packaging method provided by the invention are further described in detail below with reference to the accompanying drawings and the specific embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Unless defined otherwise herein, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms first, second and the like in the description and in the claims, are not used for any order, quantity or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. Unless otherwise indicated, the terms "upper" and/or "lower," "top" and/or "bottom" and the like are used for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

The core idea of the present invention is to provide a semiconductor package structure and a packaging method, in which a sidewall conductive structure and a filling structure adjacent to the sidewall conductive structure are formed on a carrier, and then the filling structure is removed by etching to expose the sidewall of the sidewall conductive structure, so that no additional equipment is required to expose the sidewall of the sidewall conductive structure, thereby reducing the manufacturing cost. Further, the filling structure is removed through etching to expose the side wall conductive structure, the process is simple and convenient and easy to control, and accordingly the quality and reliability of the semiconductor packaging process are improved.

Specifically, please refer to fig. 1, which is a flow chart illustrating a semiconductor packaging method according to an embodiment of the present invention. As shown in fig. 1, the semiconductor packaging method specifically includes the following steps:

step S10: providing a carrier plate, and forming a side wall conductive structure and a filling structure adjacent to the side wall conductive structure on the carrier plate;

step S11: adhering a semiconductor bare chip on the carrier plate;

step S12: forming a rewiring structure on the semiconductor die to electrically connect the semiconductor die and the sidewall conductive structures; the method comprises the steps of,

Step S13: and etching to remove the filling structure and expose the side wall of the side wall conductive structure.

Next, the semiconductor package structure and the packaging method provided by the present invention will be described in detail by the following two embodiments.

[ embodiment one ]

Fig. 2 to 17 are schematic views illustrating a process of performing a semiconductor packaging method according to a first embodiment of the invention to form a semiconductor package structure.

As shown in fig. 2, in the embodiment of the present application, first, a carrier 100 is provided, where the carrier 100 may be an alloy plate (e.g. a steel plate), or may be a glass carrier or a semiconductor carrier.

In this embodiment, an adhesive layer 110 is then formed on the carrier 100, where the adhesive layer 110 may be, for example, a hot melt adhesive layer or a UV (ultraviolet) adhesive layer.

Next, a sidewall conductive structure and a fill structure adjacent to the sidewall conductive structure are formed on the adhesion layer 110. Wherein the sidewall conductive structure comprises at least one sidewall conductive layer and the fill structure comprises at least one fill layer. In this embodiment of the present application, the sidewall conductive structure includes two sidewall conductive layers, which are a first sidewall conductive layer located on a first layer and a second sidewall conductive layer located on a second layer above the first layer; the filling structure comprises two filling layers, namely a first filling layer positioned on the first layer and a second filling layer positioned on the second layer. Further, the materials of the side wall conductive structure and the filling structure are metal, and the materials of the side wall conductive structure and the filling structure are different. Preferably, the materials of the side wall conductive layers are the same, and the materials of the filling layers are the same.

Specifically, referring to fig. 2, a first barrier layer 120 is formed on the adhesion layer 110, and a first opening 130 is formed in the first barrier layer 120, where the first opening 130 exposes a portion of the adhesion layer 110. In this embodiment, the material of the first barrier layer 120 may be photoresist, which may be formed by a spin-coating process; next, the first opening 130 is formed through photolithography and development processes. In other embodiments of the present application, the material of the first barrier layer 120 may also be a dielectric material, such as silicon oxide, silicon nitride, etc., which may be formed by a physical vapor deposition process or a chemical vapor deposition process; next, the first opening 130 is formed through an etching process.

In this embodiment of the present application, the carrier 100 may be configured to carry one or more semiconductor die, and accordingly, the carrier 100 may be divided into one or more package regions for carrying semiconductor die, where each package region forms a set of the first openings 130, and a set of the first openings 130 corresponds to one semiconductor die to finally form a semiconductor package structure. A set of first openings 130 may include one first opening 130, or may include two opposing first openings 130 (as shown in fig. 2), or may include more first openings 130, such as three first openings 130 arranged in a semi-surrounding manner, as not limited in this application. The projection of one of the first openings 130 on the carrier 100 may be rectangular, "L" or the like, which is not limited in this application. The embodiments of the present application will be mainly described by taking a semiconductor die packaging process as an example.

Next, as shown in fig. 3, the first sidewall conductive layer 140 is formed in the first opening 130, wherein an upper surface of the first sidewall conductive layer 140 is flush with an upper surface of the first barrier layer 120. In the embodiment of the present application, the material of the first sidewall conductive layer 140 is copper, and in other embodiments of the present application, other conductive materials may be used, for example, other metal materials, such as gold, silver, or aluminum.

In the embodiment of the present application, the first sidewall conductive layer 140 may be formed by a physical vapor deposition process or a chemical vapor deposition process as well as a chemical mechanical polishing process. In other embodiments of the present application, a first seed layer (not shown) may be formed in the first opening 130 by sputtering, and then the first sidewall conductive layer may be formed on the first seed layer by an electroplating process.

Referring to fig. 4, a portion of the first barrier layer 120 adjacent to the outer sidewall of the first opening 130 is removed to form a first filling opening 150, and in this embodiment, the first filling opening 150 exposes a portion of the adhesion layer 110, i.e. the first filling opening 150 penetrates through the first barrier layer 120. Preferably, a portion of the first blocking layer 120 is removed by a laser process, so that the size of the first filling opening 150 formed can be controlled very well. In this embodiment of the present application, for a package area, a semiconductor die will be attached to one side of the first opening 130, where a side close to the semiconductor die attached later is an inner sidewall of the first opening 130, and a side far from the semiconductor die attached later is an outer sidewall of the first opening 130.

As shown in fig. 5, a first filling layer 160 is then formed in the first filling port 150, wherein an upper surface of the first filling layer 160 is flush with an upper surface of the first sidewall conductive layer 140. Wherein the material of the first filling layer 160 is different from the material of the first sidewall conductive layer 140, for example, the material of the first filling layer 160 is another metal material different from the material of the first sidewall conductive layer 140, such as tin; the material of the first filling layer 160 may also be a non-metal material, such as a dielectric material different from that of the first barrier layer 120.

Next, referring to fig. 6, a second barrier layer 170 is formed on the first barrier layer 120, where the second barrier layer 170 has a second opening 180 therein, the second opening 180 exposes at least a portion of the first sidewall conductive layer 140, and the second opening 180 may also expose at least a portion of the first filling layer 160. The material of the second barrier layer 170 may be photoresist or dielectric material. Preferably, the material of the second barrier layer 170 is the same as that of the first barrier layer 120, i.e. the photoresist is used here.

The size of the second opening 180 may be the same as the size of the first opening 130, or may be smaller or larger than the size of the first opening 130. For example, the cross-sectional width of the second opening 180 may be the same as the cross-sectional width of the first opening 130, or may be smaller or larger than the cross-sectional width of the first opening 130, where it is only necessary to ensure that at least a portion of the first sidewall conductive layer 140 is exposed by the second opening 180.

Next, as shown in fig. 7, a second sidewall conductive layer 190 is formed in the second opening 180, wherein an upper surface of the second sidewall conductive layer 190 is flush with an upper surface of the second barrier layer 170. The material of the second sidewall conductive layer 190 may be, for example, a metal material, and preferably, the material of the second sidewall conductive layer 190 is the same as that of the first sidewall conductive layer 140, and is copper. Wherein the second sidewall conductive layer 190 may be formed by a physical vapor deposition process or a chemical vapor deposition process, and a chemical mechanical polishing process; the second sidewall conductive layer 190 may be formed by forming a seed layer in the second opening 180 by sputtering and then forming a conductive layer by an electroplating process.

Wherein the second sidewall conductive layer 190 is in direct contact with the first sidewall conductive layer 140 and has an overlapping region. Further, the cross-sectional width of the second sidewall conductive layer 190 may be the same as the cross-sectional width of the first sidewall conductive layer 190, and the cross-sectional width of the second sidewall conductive layer 190 may be greater than or less than the cross-sectional width of the first sidewall conductive layer 190. Still further, the inner sidewall of the second sidewall conductive layer 190 may be aligned with the inner sidewall of the first sidewall conductive layer 190, and the inner sidewall of the second sidewall conductive layer 190 may be closer to or farther from the subsequently formed semiconductor die than the inner sidewall of the first sidewall conductive layer 190. In addition, the outer sidewall of the second sidewall conductive layer 190 may be aligned with the outer sidewall of the first sidewall conductive layer 190, and the outer sidewall of the second sidewall conductive layer 190 may also be closer to or farther from the subsequently formed semiconductor die than the outer sidewall of the first sidewall conductive layer 190.

Next, as shown in fig. 8, a portion of the second barrier layer 170 adjacent to the outer sidewall of the second opening 180 is removed to form a second filling opening 200, where the second filling opening 200 exposes at least a portion of the first filling layer 160, and the second filling opening 200 may also expose a portion of the first barrier layer 120 and/or a portion of the first sidewall conductive layer 140. Preferably, a portion of the second blocking layer 170 is removed by a laser process, so that the size of the second filling port 200 formed can be controlled very well.

As shown in fig. 9, in the embodiment of the present application, a second filling layer 210 is then formed in the second filling port 200, where an upper surface of the second filling layer 210 is flush with an upper surface of the second sidewall conductive layer 190. Meanwhile, the second filling layer 210 is in direct contact with the first filling layer 160 and has an overlapping region. Wherein the material of the second filling layer 210 is different from the material of the second sidewall conductive layer 190, for example, the material of the second filling layer 210 is another metal material different from the material of the second sidewall conductive layer 190, such as tin; the material of the second filling layer 210 may also be a non-metal material, such as a dielectric material different from the material of the second barrier layer 170.

Thus, a sidewall conductive structure 220 and a fill structure 230 are formed on the carrier 100, the sidewall conductive structure 220 comprising the first sidewall conductive layer 140 and the second sidewall conductive layer 190 on the first sidewall conductive layer 140, the fill structure 230 comprising the first fill layer 160 and the second fill layer 210 on the first fill layer 160.

Next, referring to fig. 10, the second blocking layer 170 and the first blocking layer 120 are removed, and a portion of the adhesion layer 110 is exposed to form a receiving space 240 for receiving a semiconductor die. In an embodiment of the present application, an ashing process may be used to remove the second barrier layer 170 and the first barrier layer 120.

As shown in fig. 11, a semiconductor die 250 is attached to the carrier 100 in the accommodating space 240. Specifically, the first surface of the semiconductor die 250 is adhered to the carrier 100, and the second surface of the semiconductor die 250 is exposed, where the first surface is opposite to the second surface, for example, the first surface is a front surface of the semiconductor die 250, the second surface is a back surface of the semiconductor die 250, or the first surface is a back surface of the semiconductor die 250, and the second surface is a front surface of the semiconductor die 250. Preferably, the cross-sectional dimension of the accommodating space 240 is larger than the cross-sectional dimension of the semiconductor die 250, for example, the accommodating space 240 and the semiconductor die 250 are both rectangular, and then the length and the width of the accommodating space 240 are both larger than the length and the width of the semiconductor die 250. Further, the depth of the accommodating space 240 may be the same as the thickness of the semiconductor die 250, and the depth of the accommodating space 240 may be greater than or less than the thickness of the semiconductor die 250, which is not limited in this application.

As shown in fig. 12, in the embodiment of the present application, a molding process is then performed on the semiconductor die 250 to form a molding layer 260, and the molding layer 260 covers the semiconductor die 250, the sidewall conductive structures 220, the filling structures 230, and the exposed adhesive layer 110. The material of the plastic layer 260 may be, for example, EMC (epoxy molding compound), PI (polyimide), PBO (polybenzoxazole), PID (photo-imageable dielectric), pre-prege (prepreg), or the like, which has chemical and/or physical protection characteristics.

In the embodiment of the present application, the semiconductor die 250, the sidewall conductive structures 220, the filling structures 230, and the plastic layer 260 are then peeled off from the carrier 100, as shown in fig. 13. Here, the semiconductor die 250, the sidewall conductive structures 220, the filling structures 230, and the plastic layer 260 may be transferred to another carrier (not shown) to expose the first surface of the semiconductor die 250.

As shown in fig. 14, a re-wiring structure 270 is then formed on the semiconductor die 250, the re-wiring structure 270 electrically connecting the semiconductor die 250 and the sidewall conductive structures 220. Wherein the re-routing structure 270 may comprise, for example, a re-routing layer 271 and an outer pin 272 located on the re-routing layer 271. Preferably, the material of the rewiring structure 270 is the same as that of the sidewall conductive structure 220, and is copper metal.

Specifically, the re-wiring layer 271 may be formed on the semiconductor die 250, and the re-wiring layer 271 electrically connects the semiconductor die 250 and the sidewall conductive structure 220; next, a dielectric layer 280 is formed on the semiconductor die 250, and the dielectric layer 280 exposes a portion of the rewiring layer 271; next, an outer lead 272 is formed on the exposed rewiring layer 271, the surface of the outer lead 272 being flush with the surface of the dielectric layer 280.

Referring to fig. 15, in an embodiment of the present application, a portion of the dielectric layer 280 is removed to expose the filling structure 230. For example, portions of the dielectric layer 280 may be removed by a laser process.

As shown in fig. 16, the filling structure 230 may then be removed by an etching process, exposing the sidewalls of the sidewall conductive structures 220. For example, the filling structure 230 may be removed by a dry etching process or a wet etching process. Preferably, a wet etching process is used to remove the filling structure 230, and preferably, the etching solution used in the wet etching process has a better etching selectivity to the filling structure 230.

Further, after exposing the sidewall of the sidewall conductive structure 220, a surface treatment process may be performed on the sidewall of the sidewall conductive structure 220, for example, a tin-nickel-gold-tin composite structure (not shown in fig. 16) is plated to protect the sidewall conductive structure 220, thereby improving the quality and reliability of the sidewall conductive structure 220.

Therefore, the side walls of the side wall conductive structures 220 can be exposed in an etching manner, and cutting tools such as cutters are not needed, so that the manufacturing cost is reduced. Further, since the filling structure different from the sidewall conductive structure 220 is removed by the etching process, the etching process can be directly used without first adopting the processes such as exposure, thereby further simplifying the manufacturing process and reducing the manufacturing cost.

Further, the plastic layer 260 may be cut to form individual semiconductor packages, as shown in fig. 17. The semiconductor package structure includes: a semiconductor die 250, a sidewall conductive structure 220, and a rewiring structure 270, the rewiring structure 270 electrically connecting the semiconductor die 250 and the sidewall conductive structure 220. Preferably, the sidewall conductive structure 220 includes a plurality of sidewall conductive layers, and outer sidewalls of at least two of the sidewall conductive layers are staggered. Thereby, the exposed area of the sidewall conductive structure 220 may be increased, and thus the reliability of the electrical connection of the semiconductor package structure with other devices may be improved.

[ example two ]

Fig. 18 to 36 are schematic views illustrating a process of forming a semiconductor package structure by performing the semiconductor packaging method according to the second embodiment of the present invention.

As shown in fig. 18, in the embodiment of the present application, first, a carrier 300 is provided, where the carrier 300 may be an alloy plate (e.g. a steel plate), or may be a glass carrier or a semiconductor carrier.

Next, an adhesive layer 310 is formed on the carrier 300, where the adhesive layer 310 may be, for example, a hot melt adhesive layer or a UV (ultraviolet) adhesive layer.

In this embodiment, a seed layer 320 is then sputtered onto the adhesion layer 310, where the seed layer 320 is made of copper, for example. Preferably, the seed layer 320 is formed using a low temperature sputtering process, and preferably, the process temperature of the sputtering process is lower than 60 ℃, for example, the process temperature of the sputtering process is 58 ℃, 50 ℃, 45 ℃, or the like. Forming the seed layer 320 by a low-temperature sputtering process can avoid damage to the adhesion layer 310 and can also make film formation quality of a film layer (herein, a first barrier layer) formed thereon later better.

In this embodiment, two sidewall conductive layers are formed on the seed layer 320, where the two sidewall conductive layers are a first sidewall conductive layer and a second sidewall conductive layer, respectively. In this embodiment, the first sidewall conductive layer and the second sidewall conductive layer form the sidewall conductive structure, and further, the sidewall conductive structure may further include the seed layer 320.

Specifically, referring to fig. 18, a first barrier layer 330 is formed on the seed layer 320, and a first opening 340 is formed in the first barrier layer 330, where the first opening 340 exposes a portion of the seed layer 320. In this embodiment, the material of the first barrier layer 330 may be photoresist, which may be formed by a spin-coating process; next, the first opening 340 is formed through photolithography and development processes. In other embodiments of the present application, the material of the first barrier layer 330 may also be a dielectric material, such as silicon oxide, silicon nitride, etc., which may be formed by a physical vapor deposition process or a chemical vapor deposition process; next, the first opening 340 is formed through an etching process.

In this embodiment of the present application, the carrier 300 may be configured to carry one or more semiconductor die, and accordingly, the carrier 300 may be divided into one or more package regions for carrying semiconductor die, where each package region forms a set of the first openings 340, and a set of the first openings 340 corresponds to one semiconductor die to finally form a semiconductor package structure. The set of first openings 340 may include one first opening 340, or may include two opposing first openings 340 (as shown in fig. 18), or may include more first openings 340, such as three first openings 340 arranged in a semi-surrounding manner, as not limited in this application. The projection of one of the first openings 340 on the carrier 300 may be rectangular, "L" or the like, which is not limited in this application. The embodiments of the present application will be mainly described by taking a semiconductor die packaging process as an example.

Next, as shown in fig. 19, the first sidewall conductive layer 350 is formed in the first opening 340, where the upper surface of the first sidewall conductive layer 350 is flush with the upper surface of the first barrier layer 330, and in this embodiment, the material of the first sidewall conductive layer 350 is copper, and in other embodiments of this application, other conductive materials may be used, for example, other metal materials, such as gold, silver, or aluminum.

In the embodiment of the present application, since the seed layer 320 is already formed on the adhesion layer 310 by the low-temperature sputtering process, the first sidewall conductive layer 350 may be formed directly on the seed layer 320 by the electroplating process.

Referring to fig. 20, a portion of the first sidewall conductive layer 350 adjacent to the outer sidewall of the first opening 340 is removed to form a first filling opening 360, wherein in this embodiment, the first filling opening 360 exposes a portion of the seed layer 320, i.e., the first filling opening 360 penetrates through the first sidewall conductive layer 350. Preferably, a portion of the first sidewall conductive layer 350 is removed by a laser process, so that the size of the first filling opening 360 formed can be controlled very well. In this embodiment, for a package area, a semiconductor die will be attached to one side of the first opening 340, where a side close to the semiconductor die attached later is an inner sidewall of the first opening 340, and a side far from the semiconductor die attached later is an outer sidewall of the first opening 340.

Next, as shown in fig. 21, a first filling layer 370 is formed in the first filling opening 360, wherein an upper surface of the first filling layer 370 is flush with an upper surface of the first sidewall conductive layer 350. Wherein the material of the first filling layer 370 is different from the material of the first sidewall conductive layer 350, for example, the material of the first filling layer 370 is another metal material different from the material of the first sidewall conductive layer 350, such as tin; the material of the first filling layer 370 may also be a non-metal material, such as a dielectric material different from that of the first barrier layer 330.

As shown in fig. 22, a second barrier layer 380 is then formed on the first barrier layer 330, wherein the second barrier layer 380 has a second opening 390 therein, the second opening 390 exposes at least a portion of the first sidewall conductive layer 350, and the second opening 390 may also expose at least a portion of the first filling layer 370. The material of the second barrier layer 380 may be photoresist or dielectric material. Preferably, the material of the second barrier layer 380 is the same as that of the first barrier layer 330, i.e. the photoresist is used here.

The size of the second opening 390 may be the same as the size of the first opening 340, or may be smaller or larger than the size of the first opening 340. For example, the cross-sectional width of the second opening 390 may be the same as the cross-sectional width of the first opening 340, or may be smaller or larger than the cross-sectional width of the first opening 340, where it is only necessary to ensure that at least a portion of the first sidewall conductive layer 350 is exposed by the second opening 390.

Next, as shown in fig. 23, a second sidewall conductive layer 400 is formed in the second opening 390, wherein an upper surface of the second sidewall conductive layer 400 is flush with an upper surface of the second barrier layer 380. The material of the second sidewall conductive layer 400 may be, for example, a metal material, and preferably, the material of the second sidewall conductive layer 400 is the same as that of the first sidewall conductive layer 350, and is copper. Wherein, the second sidewall conductive layer 400 may be formed by a physical vapor deposition process or a chemical vapor deposition process, and a chemical mechanical polishing process; alternatively, a sub-layer may be formed in the second opening 390 by sputtering, and then a conductive layer may be formed by electroplating, so as to form the second sidewall conductive layer 400; the second sidewall conductive layer 400 may also be formed from the seed layer 320 by a conductive plating process. Wherein the second sidewall conductive layer 400 is in direct contact with the first sidewall conductive layer 350 and has an overlapping region.

Referring to fig. 24, a portion of the second sidewall conductive layer 400 adjacent to the outer sidewall of the second opening 390 is removed to form a second filling opening 410, wherein the second filling opening 410 exposes at least a portion of the first filling layer 370, and the second filling opening 410 may also expose a portion of the first barrier layer 330 and/or a portion of the first sidewall conductive layer 350. Preferably, a portion of the second sidewall conductive layer 400 is removed by a laser process, so that the size of the second filling opening 410 formed can be controlled very well.

In this embodiment, a second filling layer 420 is then formed in the second filling opening 410, as shown in fig. 25, where an upper surface of the second filling layer 420 is flush with an upper surface of the second sidewall conductive layer 400. Meanwhile, the second filling layer 420 is in direct contact with the first filling layer 370 and has an overlapping region. Wherein the material of the second filling layer 420 is different from the material of the second sidewall conductive layer 400, for example, the material of the second filling layer 420 is another metal material different from the material of the second sidewall conductive layer 400, such as tin; the material of the second filling layer 420 may also be a non-metal material, such as a dielectric material different from that of the second barrier layer 380.

Thus, a sidewall conductive structure 430 and a fill structure 440 are formed on the carrier 300, the sidewall conductive structure 430 comprising the first sidewall conductive layer 350 and the second sidewall conductive layer 400 on the first sidewall conductive layer 350, the fill structure 440 comprising a first fill layer 370 and a second fill layer 420 on the first fill layer 370.

Preferably, the material of the second filling layer 420 is different from the material of the second sidewall conductive layer 400 and the first sidewall conductive layer 350; the material of the first filling layer 370 is different from the material of the second sidewall conductive layer 400 and the first sidewall conductive layer 350. More preferably, the material of the second filling layer 420 is the same as that of the first filling layer 370, and the material of the second sidewall conductive layer 400 is the same as that of the first sidewall conductive layer 350.

In the sidewall conductive structure 430, the cross-sectional width of the second sidewall conductive layer 400 may be the same as the cross-sectional width of the first sidewall conductive layer 350, and the cross-sectional width of the second sidewall conductive layer 400 may be greater than or less than the cross-sectional width of the first sidewall conductive layer 350. Further, the inner sidewall of the second sidewall conductive layer 400 may be aligned with the inner sidewall of the first sidewall conductive layer 350, and the inner sidewall of the second sidewall conductive layer 400 may be closer to or farther from the semiconductor die formed later with respect to the inner sidewall of the first sidewall conductive layer 350. In addition, the outer sidewall of the second sidewall conductive layer 400 may be aligned with the outer sidewall of the first sidewall conductive layer 350, and the outer sidewall of the second sidewall conductive layer 400 may be closer to or further away from the semiconductor die formed later with respect to the outer sidewall of the first sidewall conductive layer 350, where only the direct contact between the second sidewall conductive layer 400 and the first sidewall conductive layer 350 and the overlapping region need be ensured.

As shown in fig. 26, the second barrier layer 380 and the first barrier layer 330 are removed to expose a portion of the seed layer 320, thereby forming a receiving space 450 for receiving a semiconductor die. In an embodiment of the present application, a plasma (plasma) process may be used to remove the second barrier layer 380 and the first barrier layer 330.

In this embodiment, further, the exposed seed layer 320 is etched. The seed layer 320 covered by the first sidewall conductive layer 350 and the first fill layer 370 remains. Here, the sidewall conductive structure 430 further includes the seed layer 320. Preferably, the exposed seed layer 320 is removed by a plasma etching process.

As shown in fig. 27, a semiconductor die 460 is then attached to the carrier 300 in the accommodating space 450. Here, the first surface of the semiconductor die 460 is adhered to the carrier 300, and the second surface of the semiconductor die 460 is exposed. The first surface is opposite to the second surface, for example, the first surface is a front surface of the semiconductor die 460, the second surface is a back surface of the semiconductor die 460, or the first surface is a back surface of the semiconductor die 460, and the second surface is a front surface of the semiconductor die 460. Preferably, the cross-sectional dimension of the accommodating space 450 is larger than the cross-sectional dimension of the semiconductor die 460, for example, the accommodating space 450 and the semiconductor die 460 are both rectangular, and then the length and the width of the accommodating space 450 are both larger than the length and the width of the semiconductor die 460. Further, the depth of the accommodating space 450 may be the same as the thickness of the semiconductor die 460, and the depth of the accommodating space 450 may be larger or smaller than the thickness of the semiconductor die 460, which is not limited in this application.

As shown in fig. 28, in the embodiment of the present application, a molding process is then performed on the semiconductor die 460 to form a molding layer 470, where the molding layer 470 covers the semiconductor die 460, the sidewall conductive structures 430, the filling structures 440, and the exposed adhesive layer 310. The material of the plastic layer 470 may be, for example, a material having chemical and/or physical protection characteristics such as EMC (epoxy molding compound), PI (polyimide), PBO (polybenzoxazole), PID (photo-imageable dielectric), pre-prege (prepreg), etc.

In the embodiment of the present application, the semiconductor die 460, the sidewall conductive structures 430, the filling structures 440, and the plastic layer 470 are then peeled off from the carrier 300, as shown in fig. 29. Here, the semiconductor die 460, the sidewall conductive structures 430, the filling structures 440, and the plastic layer 470 may be transferred to another carrier (not shown) to expose the first surface of the semiconductor die 460.

Referring next to fig. 30-34, a rewiring structure 480 is formed on the semiconductor die 460 to electrically connect the semiconductor die 460 and the sidewall conductive structures 430. The re-wiring structure 480 may include, for example, a re-wiring layer 481 and an outer pin 482 on the re-wiring layer 481. Preferably, the material of the rewiring structure 480 is the same as that of the sidewall conductive structure 430, and is copper metal.

Specifically, as shown in fig. 30, the rewiring layer 481 may be formed on the semiconductor die 460 first, and the rewiring layer 481 electrically connects the semiconductor die 460 and the sidewall conductive structure 430.

Next, as shown in fig. 31, a first dielectric layer 483 is formed on the semiconductor die 460, and in the embodiment of the present application, the first dielectric layer 483 exposes the rewiring layer 481.

As shown in fig. 32, in the embodiment of the present application, a laser process is then performed on the re-wiring layer 481 and the seed layer 320 to form a third filling opening 484 and expose the filling structure 440.

Next, as shown in fig. 33, a third filling layer 485 is formed in the third filling port 484, wherein an upper surface of the third filling layer 485 is flush with an upper surface of the rewiring layer 481. The material of the third filling layer 485 is different from that of the rewiring layer 481, and here, for example, the material of the third filling layer 485 is tin. Wherein the third filling layer 485 is in direct contact with the second filling layer 420 and has an overlapping area. With continued reference to fig. 3, a second dielectric layer 486 is formed on the first dielectric layer 483, and the second dielectric layer 486 exposes a portion of the rewiring layer 481; next, an outer lead 482 is formed on the exposed rewiring layer 481, the upper surface of the outer lead 482 being flush with the upper surface of the second dielectric layer 486. Therefore, the size of the conductive material exposed outside the plastic packaging material can be controlled, and the quality and reliability of the finally formed semiconductor packaging structure can be improved.

Further, as shown in fig. 34, the outer portion of the outer lead 482 is removed by a laser process to expose at least a portion of the third filling layer 485.

As shown in fig. 35, the filling structure 440 can then be removed by an etching process, exposing the sidewalls of the sidewall conductive structures 430. For example, the filling structure 440 may be removed by a dry etching process or a wet etching process. Preferably, a wet etching process is used to remove the filling structure 440, and preferably, the etching solution used in the wet etching process has a better etching selectivity to the filling structure 440.

Further, after exposing the sidewall of the sidewall conductive structure 430, a surface treatment process may be performed on the sidewall of the sidewall conductive structure 430, for example, a tin-nickel-gold-tin composite structure (not shown in fig. 35) is plated to protect the sidewall conductive structure 430, so as to improve the quality and reliability of the sidewall conductive structure 430.

Therefore, the side wall of the side wall conductive structure 430 can be exposed by etching, and a cutting tool such as a cutter is not needed, so that the manufacturing cost is reduced. Further, since the filling structure different from the sidewall conductive structure 430 is removed by the etching process, the etching process can be directly used without first adopting the processes such as exposure, thereby further simplifying the manufacturing process and reducing the manufacturing cost.

Further, the plastic layer 470 may be cut to form individual semiconductor packages, as shown in fig. 36. The semiconductor package structure includes: a semiconductor die 460, a sidewall conductive structure 430, and a rewiring structure 480, the rewiring structure 480 electrically connecting the semiconductor die 460 and the sidewall conductive structure 430. Preferably, the sidewall conductive structure 430 includes multiple sidewall conductive layers, and at least two of the sidewall conductive layers have outer sidewalls offset from each other. Thereby, the exposed area of the sidewall conductive structure 430 may be increased, and thus the reliability of the electrical connection of the semiconductor package structure with other devices may be improved.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description. For example, in forming the filling structure, one of the filling layers may be implemented by removing a portion of the barrier layer to form an opening and filling the opening, while the other filling layer in the filling structure is implemented by removing a portion of the sidewall conductive layer to form an opening and filling the opening, and so on. This is not explicitly recited in this application.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims

1. A semiconductor packaging method, characterized in that the semiconductor packaging method comprises:

adhering a semiconductor bare chip on the carrier plate;

2. The semiconductor packaging method of claim 1, wherein the sidewall conductive structures and the fill structures are both metal and the leadframe structures and the fill structures are different in material.

3. The semiconductor packaging method of claim 1, wherein providing a carrier plate, forming sidewall conductive structures and filling structures adjacent to the sidewall conductive structures on the carrier plate, comprises:

4. The semiconductor packaging method of claim 3, wherein a plurality of said sidewall conductive layers are formed on said carrier, and outer sidewalls of at least two of said sidewall conductive layers are offset.

5. The semiconductor packaging method of claim 3, wherein a plurality of said sidewall conductive layers and a plurality of said filler layers are formed on said carrier, each of said sidewall conductive layers being in direct contact with a previous one of said sidewall conductive layers and having an overlap region, each of said filler layers being in direct contact with a previous one of said filler layers and having an overlap region.

6. The semiconductor packaging method of claim 3, wherein the at least one sidewall conductive layer comprises a first sidewall conductive layer, forming the first sidewall conductive layer on the carrier plate comprising:

the first sidewall conductive layer is formed in the first opening.

7. The semiconductor packaging method of claim 6, wherein the at least one fill layer comprises a first fill layer;

forming the first filling layer on the carrier plate comprises:

forming the first filling layer in the first filling port;

alternatively, forming the first filling layer on the carrier plate includes:

and forming the first filling layer in the first filling port.

8. The semiconductor packaging method according to claim 7, wherein the at least one side wall conductive layer further includes a second side wall conductive layer on the first side wall conductive layer, the second side wall conductive layer being in direct contact with the first side wall conductive layer and having an overlap region, the second side wall conductive layer being formed after the first filling layer is formed, the second side wall conductive layer forming method comprising:

the second sidewall conductive layer is formed in the second opening.

9. The semiconductor packaging method of claim 8, wherein the at least one fill layer further comprises a second fill layer on the first fill layer, the second fill layer in direct contact with the first fill layer and having an overlap region;

the forming method of the second filling layer comprises the following steps:

forming the second filling layer in the second filling port;

alternatively, the forming method of the second filling layer includes:

and forming the second filling layer in the second filling port.

10. The semiconductor packaging method of any one of claims 1-8, wherein forming a rewiring structure on the semiconductor die to electrically connect the semiconductor die and the sidewall conductive structure comprises: the rewiring structure exposes the filling structure.

11. The semiconductor packaging method of any one of claims 1-8, wherein forming a rewiring structure on the semiconductor die to electrically connect the semiconductor die and the sidewall conductive structure comprises:

a portion of the rewiring structure is removed to expose the filling structure.

12. The semiconductor packaging method of any one of claims 1-8, wherein forming a rewiring structure on the semiconductor die to electrically connect the semiconductor die and the sidewall conductive structure comprises:

and removing part of the dielectric layer to expose the filling structure.

13. The semiconductor packaging method according to any one of claims 1 to 8, wherein before forming a sidewall conductive structure and a filling structure adjoining the sidewall conductive structure on the carrier, the semiconductor packaging method further comprises:

forming a seed layer on the adhesion layer;

14. A semiconductor package structure formed by the semiconductor packaging method according to any one of claims 1 to 13, characterized in that the semiconductor package structure comprises: a semiconductor die, a sidewall conductive structure, and a rewiring structure electrically connecting the semiconductor die and the sidewall conductive structure.

15. The semiconductor package according to claim 14, wherein the sidewall conductive structure comprises a plurality of sidewall conductive layers, outer sidewalls of at least two of the sidewall conductive layers being offset.