CN117785114A - A matrix multiplication execution method, device, electronic equipment and storage medium - Google Patents

Abstract

The embodiment of the invention discloses a matrix multiplication operation execution method, a device, electronic equipment and a storage medium. The method comprises the following steps: responding to a matrix multiplication operation instruction, and acquiring a first matrix to be operated, a second matrix to be operated and an initial matrix to be updated; determining a block step of matrix block according to the buffer space capacity, and performing matrix block on the matrix to respectively obtain a first sub-matrix of a first matrix to be operated, a second sub-matrix of a second matrix to be operated and a third sub-matrix of an initial matrix to be updated; according to the block stride, a stored vector register and a pre-stored vector register can be selected from the vector registers; and sequentially acquiring corresponding submatrices from the stored vector register and the pre-stored vector register to perform matrix multiplication operation until the operation ending condition is met, so as to obtain a matrix multiplication operation result. According to the technical scheme provided by the embodiment of the invention, the operation efficiency of matrix multiplication is improved by optimizing the function performance.

Description

A matrix multiplication execution method, device, electronic equipment and storage medium

Technical field

Embodiments of the present invention relate to the technical field of numerical analysis, and in particular to a matrix multiplication execution method, device, electronic device and storage medium.

Background technique

Numerical computing is an important tool for scientific research, and high-performance computing based on numerical computing has now become one of the important scientific and technological elements representing the country's comprehensive strength, whether in atomic physics, computational chemistry, bioinformatics, atmospheric science and Fields such as artificial intelligence are of great significance. Numerical linear algebra is the most important core computing method in the field of numerical computing. It uses matrices as the main data representation form and matrix operations as the ultimate goal of problem solving.

Since numerical linear algebra has a wide range of applications in scientific and engineering computing, researchers have continuously developed powerful numerical linear algebra libraries, among which the more well-known is BLAS (Basic Linear Algebra Subprograms). The linear algebra operations in BLAS are mainly divided into three aspects, among which vector-vector is called Level-1 BLAS, vector-matrix is called Level-2 BLAS, and matrix-matrix is called Level-3 BLAS.

In the existing technology, matrix multiplication is performed by dot-multiplying a column of matrix B by a row of matrix A and then updating the corresponding matrix element of C. However, no matter whether the matrix is stored in the memory in a row-first storage format or a column-first storage format, , when the cache (Cache) fetches a row of matrix A or a column of matrix B from main memory, a large number of cache misses (Cache Miss) and translation buffer (Cache Miss) will occur on either side due to discontinuous addresses. Translation Lookaside Buffer, TLB) is lost (TLB miss), which will reduce the calculation memory access ratio and have a great impact on the calculation speed. In addition, in the existing technology, due to the reduction in calculation speed, the calculation efficiency of numerical linear algebra is not high enough, and there is a problem of slow running speed.

Contents of the invention

The invention provides a matrix multiplication operation execution method, device, electronic equipment and storage medium to improve the operation efficiency of matrix multiplication.

In a first aspect, embodiments of the present invention provide a matrix multiplication operation execution method, which method includes:

In response to the matrix multiplication operation instruction, obtain the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated;

Determine the blocking stride used for matrix blocking according to the cache space capacity;

According to the blocking step, the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated are divided into matrix blocks to obtain the first sub-matrix of the first matrix to be operated and the second sub-matrix of the second matrix to be operated respectively. matrix and the third sub-matrix of the initial matrix to be updated;

According to the block stride, a storage vector register and a pre-stored vector register are selected from each vector register; the storage vector register is used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; the pre-stored vector register is used to store the first sub-matrix and the second sub-matrix in the next operation cycle;

The corresponding sub-matrices are obtained from the storage vector register and the pre-stored vector register in turn and the matrix multiplication operation is performed until the operation end condition is met, and the matrix multiplication operation result is obtained.

In a second aspect, embodiments of the present invention also provide a matrix multiplication execution device, which includes:

A matrix acquisition module, configured to acquire the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated in response to the matrix multiplication operation instruction;

The blocking stride determination module is used to determine the blocking stride for matrix partitioning based on the cache space capacity;

The sub-matrix obtaining module is used to divide the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix into matrix blocks according to the blocking step, and obtain the first sub-matrix and the second sub-matrix of the first to-be-operated matrix respectively. The second sub-matrix of the matrix to be operated on and the third sub-matrix of the initial matrix to be updated;

The register selection module is used to select the storage vector register and the pre-stored vector register from each vector register according to the block step; the storage vector register is used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle. Matrix; the pre-stored vector register is used to store the first sub-matrix and the second sub-matrix in the next operation cycle;

The result obtaining module is used to sequentially obtain corresponding sub-matrices from the storage vector register and the pre-stored vector register to perform matrix multiplication operation until the operation end condition is met to obtain the matrix multiplication operation result.

In a third aspect, embodiments of the present invention also provide an electronic device, including:

at least one processor; and

a memory communicatively connected to at least one processor; wherein,

The memory stores a computer program that can be executed by at least one processor, and the computer program is executed by at least one processor, so that at least one processor can execute a matrix multiplication execution method according to any embodiment of the present invention.

In a fourth aspect, embodiments of the present invention also provide a storage medium containing computer-executable instructions. When executed by a computer processor, the computer-executable instructions enable the computer processor to execute any matrix provided by the embodiments of the present invention. Method for performing multiplication operations.

The embodiment of the present invention obtains the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix by responding to the matrix multiplication operation instruction; determines the blocking step for matrix blocking according to the cache space capacity; according to the According to the blocking step, the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix are divided into matrix blocks to obtain the first sub-matrix and the first sub-matrix of the first to-be-operated matrix respectively. The second sub-matrix of the second matrix to be operated and the third sub-matrix of the initial matrix to be updated; select a storage vector register and a pre-stored vector register from each vector register according to the block step; the storage vector The register is used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; the pre-stored vector register is used to store the first sub-matrix and the second sub-matrix in the next operation cycle; from The corresponding sub-matrix is obtained from the storage vector register and the pre-stored vector register and the matrix multiplication operation is performed until the operation end condition is met, and the matrix multiplication operation result is obtained. The technical solution provided by the embodiment of the present invention improves the operational efficiency of matrix multiplication by optimizing function performance.

It should be understood that what is described in this section is not intended to identify key or important features of the embodiments of the invention, nor is it intended to limit the scope of the invention. Other features of the present invention will become easily understood from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

Figure 1 is a flow chart of a matrix multiplication execution method provided according to Embodiment 1 of the present invention;

Figure 2 is a flow chart of another matrix multiplication execution method provided according to Embodiment 2 of the present invention;

FIG3 is a schematic diagram of the structure of a matrix multiplication operation execution device provided according to Embodiment 3 of the present invention;

FIG. 4 is a schematic structural diagram of an electronic device according to a matrix multiplication execution method provided in Embodiment 4 of the present invention.

Detailed ways

In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

In addition, it should be noted that in the technical solution of the present invention, the collection, storage, use, processing, transmission, provision and disclosure of relevant data are in compliance with relevant laws and regulations and do not violate public order and good customs. .

Embodiment 1

Figure 1 is a flow chart of a matrix multiplication operation execution method provided by Embodiment 1 of the present invention. This embodiment can be applied to the situation where function performance is optimized to improve the operational efficiency of matrix multiplication. The method can be executed by a matrix multiplication operation execution device. The matrix multiplication operation execution device can be implemented in the form of hardware and/or software. The matrix multiplication operation execution device can be configured in an electronic device, which can be a terminal device or a server, etc. The embodiment of the present invention does not limit this.

As shown in Figure 1, a matrix multiplication execution method provided by an embodiment of the present invention specifically includes the following steps:

S110. In response to the matrix multiplication operation instruction, obtain the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated.

Specifically, in response to the numerical calculation requirement for matrix multiplication, after responding to the matrix multiplication operation instruction, the first to-be-operated matrix, the second to-be-operated matrix, and the initial to-be-updated matrix can be obtained. In particular, the embodiment of the present invention does not limit the response mode of the matrix multiplication operation instruction. In addition, the embodiment of the present invention does not limit the acquisition method of the first to-be-operated matrix, the second to-be-operated matrix, and the initial to-be-updated matrix.

The first matrix to be operated and the second matrix to be operated can be understood as matrices to be operated upon in response to the matrix multiplication operation instruction. For example, when performing matrix multiplication, it can be implemented through Single Precision General Matrix-matrix Multiplication (SGEMM) in the Level-3 BLAS numerical calculation library. SGEMM is a general matrix multiplication that can be implemented through Modify function arguments to multiply arbitrary matrices. When performing matrix multiplication operations through SGEMM, the following formula can be used:

C = alpha × op(A) × op(B) + beta × C;

Among them, alpha and beta are scalar factors, A, B and C are operation matrices, and it should be noted that A and B are the first matrix to be operated and the second matrix to be operated obtained in response to the matrix multiplication operation instruction. The initial matrix to be updated can be obtained based on the obtained A and B and according to the above formula. At this time, the calculated output matrix C can be used as the initial matrix to be updated.

In response to the matrix multiplication operation instruction, the first to-be-operated matrix, the second to-be-operated matrix, and the initial to-be-updated matrix can be obtained, so as to carry out numerical calculations of subsequent matrices based on the obtained operation matrix and the initial to-be-updated matrix.

S120. Determine the blocking step for matrix blocking according to the cache space capacity.

Specifically, according to the limitation of the cache space capacity in the computer memory, the blocking step for matrix blocking can be determined. It should be noted that the computer storage hierarchy includes three levels of storage structures: main memory, cache, and registers from bottom to top. The storage space size and access clock cycle of each level are also different. The embodiment of the present invention does not limit the method of determining the block step size for matrix block based on the cache space capacity.

The buffer space capacity is used to determine the blocking step of dividing the matrix into blocks to facilitate subsequent matrix calculations.

S130. According to the blocking step, divide the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated into matrix blocks to obtain the first sub-matrix of the first matrix to be operated and the second sub-matrix of the second matrix to be operated respectively. The second sub-matrix and the third sub-matrix of the initial matrix to be updated.

Specifically, according to the determined block stride, the first matrix to be operated, the second matrix to be operated, and the initial matrix to be updated can be matrix-blocked, and then a first sub-matrix of the first matrix to be operated, a second sub-matrix of the second matrix to be operated, and a third sub-matrix of the initial matrix to be updated can be obtained. In particular, when the first matrix to be operated, the second matrix to be operated, and the initial matrix to be updated are matrix-blocked, the selected matrix-blocking method is not limited.

It should be noted that in the computer storage hierarchy, generally speaking, the Central Processing Unit (CPU), which is the computing and control core of the computer system, has different access speeds to registers, cache, main memory and hard disk. . Generally, registers can be used to store temporary data and instructions. Since the CPU can directly read and write data in the registers, the access speed is very fast, usually at the nanosecond level, so it is the fastest storage medium inside the CPU; the cache is located between the CPU and The storage medium between the main memories can be used to speed up access to the main memory. The cache can be divided into multiple levels such as L1, L2 and L3. Among them, the L1 cache is closest to the CPU, so it is very fast, while the L3 cache is far away from the CPU. , so the speed is relatively slow. Generally speaking, the access speed of cache is generally between a few nanoseconds and more than ten nanoseconds; main memory is the main storage medium used to store programs and data in computer systems, and usually refers to random access. Random Access Memory (RAM) is an internal memory that directly exchanges data with the CPU. It can be read and written at any time and is very fast. It can usually be used as a temporary data storage medium for the operating system or other running programs. When RAM is working, information can be written (i.e., stored) or read (i.e., taken out) from any specified address at any time. The difference from read-only memory (Read-Only Memory, ROM) lies in the volatility of data. That is to say, the stored data will be lost once the power is cut off. RAM can be used to temporarily store programs, data and intermediate results in computers and digital systems. However, compared with registers and caches, the access speed of main memory is slower, generally between tens of nanoseconds and hundreds of nanoseconds. As a device used to permanently store data in computer systems, hard disks are the slowest storage media. The access speed of the hard disk is significantly lower than that of the main memory, generally on the millisecond level or even longer.

Optionally, perform matrix partitioning on the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix according to the blocking step, to obtain the first sub-matrix and the second to-be-operated matrix of the first to-be-operated matrix respectively. After the second sub-matrix of the matrix and the third sub-matrix of the initial matrix to be updated, it also includes: storing the first sub-matrix of the first matrix to be operated based on a preset row storage method; and, storing the second matrix to be operated The second sub-matrix is stored based on the preset column storage method.

Specifically, according to the blocking step, when the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated are divided into matrix blocks, the first sub-matrix and the second sub-matrix of the first matrix to be operated can be obtained respectively. The second sub-matrix of the operation matrix and the third sub-matrix of the initial matrix to be updated. After that, the first sub-matrix of the first matrix to be operated can also be stored based on the preset row storage method, and the second sub-matrix to be operated can be stored based on the preset row storage method. The second submatrix of the matrix is stored based on the preset column storage method. In particular, the embodiment of the present invention does not limit the specific storage method of the preset row storage method and the preset column storage method.

According to the blocking step, the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated can be divided into matrix blocks to obtain the first sub-matrix of the first matrix to be operated and the second sub-matrix of the second matrix to be operated respectively. sub-matrix and the third sub-matrix of the initial matrix to be updated. After that, the first sub-matrix of the first matrix to be operated can also be stored based on the preset row storage method, and the second sub-matrix of the second matrix to be operated can be stored. Matrices are stored based on preset column storage methods. For example, to sum up, the matrix located in the memory can be divided by the matrix blocking method, so that the smaller sub-matrices obtained by the division can be stored in the cache, so that the CPU can directly Obtain elements from the cache for calculation, thereby achieving fast access to elements in the matrix.

S140. According to the block step, select a storage vector register and a pre-stored vector register from each vector register; the storage vector register is used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; the pre-stored vector The register is used to store the first sub-matrix and the second sub-matrix in the next operation cycle.

Specifically, according to the block stride, a storage vector register and a pre-stored vector register can be selected from the vector registers, wherein the storage vector register can be used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; the pre-stored vector register can be used to store the first sub-matrix and the second sub-matrix in the next operation cycle.

By selecting a storage vector register and a pre-stored vector register from each vector register, the selected storage vector register can be used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; the selected pre-stored vector register The vector register can be used to store the first sub-matrix and the second sub-matrix in the next operation cycle, so that subsequent work can be carried out based on the sub-matrices in the stored vector register and pre-stored vector register. By reading the sub-matrices, the accuracy of the calculation can be improved. Computational efficiency of matrices.

S150. Obtain the corresponding sub-matrices from the storage vector register and the pre-stored vector register in sequence and perform matrix multiplication until the operation end condition is met, and the matrix multiplication result is obtained.

Specifically, by sequentially obtaining the corresponding sub-matrices from the storage vector register and the pre-stored vector register, and performing matrix multiplication operations based on the obtained sub-matrices, when the operation end conditions are met, the matrix multiplication operation results can be obtained. In particular, the embodiment of the present invention does not limit the operation end conditions.

According to the storage vector register and the pre-stored vector register, the corresponding sub-matrix is selected to perform the matrix multiplication operation. When the operation end condition is met, the final matrix multiplication operation result can be obtained. By performing matrix multiplication operations on sub-matrices and obtaining the results of the matrix multiplication operations when the operation end conditions are met, the calculation efficiency of matrices can be effectively improved.

The embodiment of the present invention obtains the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix by responding to the matrix multiplication operation instruction; determines the blocking step for matrix blocking according to the cache space capacity; according to the According to the blocking step, the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix are divided into matrix blocks to obtain the first sub-matrix and the first sub-matrix of the first to-be-operated matrix respectively. The second sub-matrix of the second matrix to be operated and the third sub-matrix of the initial matrix to be updated; select a storage vector register and a pre-stored vector register from each vector register according to the block step; the storage vector The register is used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; the pre-stored vector register is used to store the first sub-matrix and the second sub-matrix in the next operation cycle; from The corresponding sub-matrix is obtained from the storage vector register and the pre-stored vector register and the matrix multiplication operation is performed until the operation end condition is met, and the matrix multiplication operation result is obtained. The technical solution provided by the embodiment of the present invention improves the operational efficiency of matrix multiplication by optimizing function performance.

Embodiment 2

Figure 2 is a flow chart of another matrix multiplication execution method provided in Embodiment 2 of the present invention. The technical solution of the embodiment of the present invention is further optimized based on the above optional technical solutions.

Further, "determine the blocking step for matrix blocking according to the cache space capacity" is further refined to "according to the matrix dimension size of the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated. , determine the number of matrix blocks; according to the cache space capacity, determine the block steps of the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated in different dimensions under each matrix block number, so as to improve the matrix The efficiency of multiplication operations. It should be noted that for parts that are not described in this embodiment, reference may be made to the relevant expressions in other embodiments, which will not be described again here.

As shown in Figure 2, another matrix multiplication execution method provided by an embodiment of the present invention specifically includes the following steps:

S210. In response to the matrix multiplication operation instruction, obtain the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated.

S220. Determine the number of matrix blocks according to the matrix dimension sizes of the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated.

Specifically, in response to the matrix multiplication operation instruction, the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated can be obtained, and then the number of matrix partitions can be determined according to the obtained matrix size. In particular, the embodiment of the present invention does not limit the number of matrix partitions.

After responding to the matrix multiplication operation instruction, the number of matrix block divisions may be determined based on the obtained sizes of the first matrix to be operated, the second matrix to be operated on, and the initial matrix to be updated. In order to obtain the sub-matrices of each matrix according to the number of matrix blocks of each matrix, and then carry out subsequent work based on the obtained sub-matrices.

S230. According to the cache space capacity, determine the blocking steps of the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated in different dimensions under each matrix blocking number.

S240, performing matrix blocking on the first matrix to be operated, the second matrix to be operated, and the initial matrix to be updated according to the blocking stride, to obtain a first sub-matrix of the first matrix to be operated, a second sub-matrix of the second matrix to be operated, and a third sub-matrix of the initial matrix to be updated, respectively.

Specifically, according to the cache space capacity, the blocking steps of the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated in different dimensions can be determined for each matrix blocking number. According to the determined blocking step, the first to-be-operated matrix, the second to-be-operated matrix, and the initial to-be-updated matrix can be divided into matrix blocks, and then the corresponding first sub-matrix and third sub-matrix of the first to-be-operated matrix can be obtained. The second sub-matrix of the matrix to be operated on and the third sub-matrix of the initial matrix to be updated.

It should be noted that according to the blocking step, when the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix are divided into matrix blocks, each of the above matrices can be divided into blocks by rows or columns. Then the corresponding sub-matrix is obtained. The embodiment of the present invention does not limit the matrix blocking method selected when the matrix is divided into blocks.

Optionally, perform matrix partitioning on the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix according to the blocking step, to obtain the first sub-matrix and the second to-be-operated matrix of the first to-be-operated matrix respectively. The second sub-matrix of and the third sub-matrix of the initial matrix to be updated include: the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated in different dimensions according to the number of blocks of each matrix. Amplitude, perform matrix partitioning on the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix, and obtain the first block matrix of the first to-be-operated matrix and the second to-be-operated matrix under each matrix blocking number. The second block matrix and the third block matrix of the initial matrix to be updated; determine the first block matrix of the first matrix to be operated under the last matrix block number as the first sub-matrix, and the second matrix to be operated The second block matrix of is determined as the second sub-matrix, and the third block matrix of the initial matrix to be updated is determined as the third sub-matrix.

Specifically, according to the blocking step, when the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated are divided into matrix blocks, the first sub-matrix and the second sub-matrix of the first matrix to be operated can be obtained respectively. The specific acquisition method of the second sub-matrix of the operation matrix and the third sub-matrix of the initial matrix to be updated can be based on the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated according to the number of blocks of each matrix. The block strides in different dimensions, for the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix in different dimensions, for the first to-be-operated matrix, the second to-be-operated matrix and The initial matrix to be updated is divided into matrix blocks, and then the first block matrix of the first matrix to be operated, the second block matrix of the second matrix to be operated and the third block matrix of the initial matrix to be updated can be obtained for each matrix block number. Partitioned Matrix.

According to the blocking steps of different matrices in different dimensions according to the number of matrix blocking times, each matrix can be divided into matrix blocks, and then the blocking matrix of each matrix under each matrix blocking number can be obtained. In addition, the last matrix partitioning can be The first block matrix of the first matrix to be operated at the block number is determined as the first sub-matrix, the second block matrix of the second matrix to be operated is determined as the second sub-matrix, and the third block matrix of the initial matrix to be updated is determined The block matrix is determined as the third sub-matrix, so that subsequent work such as matrix calculation can be carried out based on each sub-matrix obtained at this time.

S250. According to the block step, select a storage vector register and a pre-stored vector register from each vector register; the storage vector register is used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; the pre-stored vector The register is used to store the first sub-matrix and the second sub-matrix in the next operation cycle.

Specifically, according to the acquired block stride, a storage vector register and a pre-stored vector register can be selected from each vector register, wherein the storage vector register can be used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; the pre-stored vector register can be used to store the first sub-matrix and the second sub-matrix in the next operation cycle.

Optionally, select a storage vector register and a pre-stored vector register from each vector register according to the blocking step, including: the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix according to the last matrix blocking times block step, determine the storage vector registers used to store the first sub-matrix, second sub-matrix and third sub-matrix in the current operation cycle; according to the number of registers to store vector registers, select from each vector register for The pre-stored vector register stores the first sub-matrix and the second sub-matrix in the next operation cycle.

Specifically, according to the blocking steps of the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated in the last matrix blocking times, it is determined to store the first sub-matrix and the second sub-matrix in the current operation cycle. Storage vector registers for the matrix and the third sub-matrix; according to the number of registers for storing vector registers, a pre-stored vector register for storing the first sub-matrix and the second sub-matrix in the next operation cycle is selected from each vector register. In particular, the embodiment of the present invention does not limit the selection method of selecting the storage vector register and the pre-stored vector register from each vector register according to the block step size.

Optionally, according to the blocking steps of the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated in the last matrix blocking times, determine the first sub-matrix and the second sub-matrix in the current operation cycle. The storage vector register of the sub-matrix and the third sub-matrix includes: determining the first sub-matrix used to store the first sub-matrix in the current operation cycle according to the block step of the first matrix to be operated on in the last matrix block count. Storage vector register; Determine the second storage vector register used to store the second sub-matrix in the current operation cycle based on the blocking stride of the second matrix to be operated on in the last matrix blocking count; Determine the second storage vector register according to the last matrix blocking The block stride of the initial matrix to be updated in times is determined to determine the third storage vector register used to store the third sub-matrix in the current operation cycle; combine the first storage vector register, the second storage vector register and the third storage vector The register is identified as a storage register.

Specifically, based on the blocking steps of the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix in the last matrix blocking times, it is determined to store the first sub-matrix and the second sub-matrix in the current operation cycle. When storing the vector registers of the sub-matrix and the third sub-matrix, the first step for storing the first sub-matrix in the current operation cycle can be determined based on the block step of the first matrix to be operated on in the last matrix block count. Store vector register. According to the blocking stride of the second matrix to be operated on for the last matrix blocking count, the second storage vector register used to store the second sub-matrix in the current operation cycle can be determined; according to the last matrix blocking count The block stride of the initial matrix to be updated can determine the third storage vector register used to store the third sub-matrix in the current operation cycle. In addition, the first storage vector register, the second storage vector register, and the third storage vector register may be determined as storage registers. In particular, the embodiment of the present invention does not limit the method of determining the storage vector register corresponding to each sub-matrix in the current operation cycle. Wherein, each sub-matrix described includes a first sub-matrix, a second sub-matrix and a third sub-matrix, and each storage vector register corresponding to each sub-matrix includes a first storage vector register, a second storage vector register and a third storage vector register. Three storage vector registers.

Among them, according to the register quantity of the storage vector register, the pre-stored vector register for storing the first sub-matrix and the second sub-matrix in the next operation cycle is selected from each vector register, including: according to the first register quantity of the first storage vector register, the first pre-stored vector register for storing the first sub-matrix in the next operation cycle is selected from each vector register; according to the second register quantity of the second storage vector register, the second pre-stored vector register for storing the second sub-matrix in the next operation cycle is selected from each vector register.

Specifically, when selecting the pre-stored vector register for storing the first sub-matrix and the second sub-matrix in the next operation cycle from each vector register according to the number of registers of the storage vector register, the number of the first storage vector register can be The number of first registers, the first pre-stored vector register used to store the first sub-matrix in the next operation cycle is selected from each vector register; according to the number of second registers for storing the second vector register, it can be selected from each vector register A second pre-stored vector register used to store the second sub-matrix in the next operation cycle. In particular, the embodiment of the present invention does not limit the selection method of selecting from each vector register a pre-stored vector register corresponding to each sub-matrix in the next operation cycle based on the number of registers for each storage vector register. It should be noted that each storage vector register described at this time includes a first storage vector register and a second storage vector register; the pre-stored vector register includes a first pre-stored vector register and a second pre-stored vector register.

According to the blocking step of the first matrix to be operated in the last matrix blocking count, the first storage vector register used to store the first sub-matrix in the current operation cycle can be determined; according to the last matrix blocking count The block stride of the second matrix to be operated determines the second storage vector register used to store the second sub-matrix in the current operation cycle; according to the block stride of the initial matrix to be updated in the last matrix block count, Determine a third storage vector register used to store the third sub-matrix in the current operation cycle; determine the first storage vector register, the second storage vector register and the third storage vector register as storage registers. Among them, the storage vector register can be used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; according to the number of first registers in the first storage vector register, select from each vector register to store the next The first pre-stored vector register of the first sub-matrix in one operation cycle; according to the number of second registers of the second storage vector register, select the second vector register for storing the second sub-matrix in the next operation cycle from each vector register. Prestored vector registers. In order to facilitate the reading of each sub-matrix from each vector memory, and then carry out the numerical calculation of each sub-matrix.

S260: Obtain the corresponding sub-matrices from the storage vector register and the pre-stored vector register in sequence and perform matrix multiplication until the operation end condition is met, and the matrix multiplication result is obtained.

Specifically, by sequentially obtaining corresponding sub-matrices from the storage vector register and the pre-stored vector register to perform matrix multiplication operations, the corresponding matrix multiplication operation results can be obtained when the operation end conditions are met. In summary, the technical solution described above can obtain the final matrix multiplication operation result.

In the implementation of an optional embodiment, a matrix A with a size of m×k, a matrix B with a size of k×n, and a matrix C with a size of m×n are given as examples, where the A and B matrices are both is the input matrix, and C is the output matrix to be updated.

Based on the above three matrices A, B and C that have been obtained, the matrix is divided into blocks. The specific blocking method can be, in the n-dimensional direction with nc as the step size, the matrix B is divided into blocks by columns, which can be obtained Submatrix b with a size of k×nc; with nc as the step size in the n-dimensional direction, divide the matrix C into columns by columns to obtain a submatrix c with a size of m×nc; with kc as the step size in the k-dimensional direction, Divide the matrix A into blocks by columns to obtain sub-matrix a with a size of m×kc; in the k-dimensional direction with kc as the step size, divide each sub-matrix b into blocks by rows to obtain a sub-matrix with a size of kc×nc. bb; in the m-dimensional direction, use mc as the step size, divide the sub-matrix a by rows, and obtain the sub-matrix aa of size mc×kc; in the m-dimensional direction, use mc as the step size, divide the sub-matrix c by rows Divide into blocks to obtain a submatrix cc with a size of mc×nc; in the nc-dimensional direction with nr as the step size, divide the sub-matrix bb into columns by columns to obtain a sub-matrix bbb with a size of kc×nr; in the nc-dimensional direction with nr is the step size, and the submatrix cc is divided into columns by columns to obtain the submatrix ccc with a size of mc×nr; in the mc dimension direction, mr is the step size, and the submatrix aa is divided into rows by rows to obtain a size of mr Submatrix aaa of

In particular, after completing the above matrix partitioning operation, the sizes of sub-matrix A, sub-matrix B and sub-matrix C obtained at this time are mr×kc, kc×nr and mr×nr respectively. After this, the submatrix C can be calculated through the vector register combined with the Level-1 (ie L1) level cache. Among them, the blocking parameters such as mc, kc, nc, mr and nr described above all depend on the cache space size of the specific processor for reasonable division. In the present invention, considering that the blocking parameters are limited to Level-1 Level cache limitations, such as the small space of L1, etc. When making reasonable divisions, the following formulas (1) and (2) should be satisfied. The details of the two formulas are as follows:

Among them, mc, kc, nc, mr and nr cannot exceed the L1 size. In summary, mc, kc, nc, mr and nr can be 96kb, 96kb, 64kb, 16kb and 4kb respectively.

Secondly, when rearranging the data of the obtained sub-matrices, after the block is divided, since the floating point numbers stored in the two matrices A and B are discontinuous in the memory addresses, this will seriously affect the cache hit rate. , resulting in the Cache not being able to obtain consecutive data every time it accesses data from the main, which will generate a large number of Cache Misses, thus affecting computing efficiency. In order to avoid the above situation, the obtained sub-matrix B (ie bb) with size kc×nc and the obtained sub-matrix A (ie aa) with size mc×kc can be rearranged in the kc direction. , to ensure that the data inside have consecutive addresses to improve the cache hit rate. First, divide the kc×nc submatrix B into several kc×4 small matrices by columns, store these small matrices by rows, and then connect several small matrices in order; secondly, mc×kc Submatrix A is divided into several 16×kc small matrices by rows, these small matrices are stored in columns, and then these small matrices are connected in order.

Then, when allocating vector registers for the above-mentioned sub-matrix that has undergone data rearrangement, vector registers are mainly used for vectorized accelerated calculations. Generally speaking, the more vector registers are used, the lower the computing performance. The improvement has also increased accordingly, so it is necessary to rationally allocate the use strategy of vector registers under the limit of the limited number of vector registers so that they can be maximized. In the present invention, since the bit width of the hardware vector register used is 128 bits and can store 4 single-precision floating point numbers, mr (16 in the above example)/4 vector registers are used to store the A matrix elements, nr ( In the above example, 4)/4 vector registers are used to store the B matrix elements, mr×nr/4 vector registers are used to store the C matrix elements, and 4 vector registers are used to store the prefetched 16 A For matrix elements, 1 vector register is used to store the 4 prefetched B matrix elements, so the total number of vector registers used is 26.

Then, when rearranging the above obtained data, the required data can be loaded into the cache in advance, and the data can be obtained directly from the cache during calculation, reducing the time of waiting for the data to be loaded from the memory, and data prefetching You can also Cache Miss, thereby greatly improving computing efficiency. When writing assembly calculation code, it is necessary to try to avoid processor pipeline stalls caused by conflicts such as data dependencies. Therefore, the present invention combines the characteristics of hardware pipelines to avoid pipeline stalls caused by RAW-type conflicts in pipeline conflicts, and reorganizes the assembly instructions. row, thereby efficiently utilizing the computing power of the processor, filling the pipeline, and improving the computing efficiency of GEMM.

The technical solution adopted in the embodiment of the present invention greatly improves the calculation efficiency by vectorizing the matrix multiplication, and can be calculated on a processor that supports the RISC-V vector extended instruction set (version 0.7.1). Additional hardware configuration is required. In addition, the present invention redesigns the calculation kernel for matrix dimensions and implements it using manual assembly code. By combining the characteristics of the hardware processor, the optimal matrix blocking strategy, matrix blocking parameters, and register allocation strategy can be calculated and determined. Therefore, compared with the most original triple circulant matrix multiplication calculation method, the optimization method implemented by the present invention has a greatly improved calculation speed.

The embodiment of the present invention obtains the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated by responding to the matrix multiplication operation instruction, and determines the number of matrix blocks according to the matrix dimension size of the above matrix; according to the cache space capacity, Determine the blocking steps of each of the above matrices in different dimensions under each matrix blocking number, and perform matrix blocking on the first to-be-operated matrix, the second to-be-operated matrix, and the initial to-be-updated matrix to obtain the number of matrix blocking times. The first block matrix of the first matrix to be operated on, the second block matrix of the second matrix to be operated on and the third block matrix of the initial matrix to be updated; divide the first block matrix of the last matrix to be operated on The first block matrix of the matrix is determined as the first sub-matrix, the second block matrix of the second matrix to be operated is determined as the second sub-matrix, and the third block matrix of the initial matrix to be updated is determined as the third sub-matrix. Matrix; determine the first storage vector register used to store the first sub-matrix in the current operation cycle based on the blocking step of the first matrix to be operated on the last matrix blocking count; determine the first storage vector register for storing the first sub-matrix in the current operation cycle; based on the last matrix blocking count The block stride of the second matrix to be operated is determined to determine the second storage vector register used to store the second sub-matrix in the current operation cycle; the block stride of the initial matrix to be updated is based on the last number of matrix blocks. , determine the third storage vector register used to store the third sub-matrix in the current operation cycle; determine the first storage vector register, the second storage vector register and the third storage vector register as storage registers; according to the first storage vector register According to the number of first registers, the first pre-stored vector register used to store the first sub-matrix in the next operation cycle is selected from each vector register; according to the number of second registers for storing the second vector register, selected from each vector register The second pre-stored vector register is used to store the second sub-matrix in the next operation cycle; the storage vector register is used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; the pre-stored vector register is used To store the first sub-matrix and the second sub-matrix in the next operation cycle; sequentially obtain the corresponding sub-matrices from the storage vector register and the pre-stored vector register to perform matrix multiplication until the operation end condition is met, and the matrix multiplication operation result is obtained. The technical solution provided by the embodiment of the present invention improves the operational efficiency of matrix multiplication by optimizing function performance.

Embodiment 3

FIG. 3 is a schematic structural diagram of a matrix multiplication execution device provided in Embodiment 3 of the present invention. As shown in Figure 3, this matrix multiplication operation execution device includes: a matrix acquisition module 310, a block step determination module 320, a sub-matrix acquisition module 330, a register selection module 340 and a result acquisition module 350. in:

The matrix acquisition module 310 is configured to acquire the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated in response to the matrix multiplication operation instruction;

The blocking stride determination module 320 is used to determine the blocking stride for matrix partitioning according to the cache space capacity;

The sub-matrix obtaining module 330 is used to divide the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated into matrix blocks according to the blocking step, and obtain the first sub-matrix and the first sub-matrix of the first matrix to be operated respectively. The second sub-matrix of the matrix to be operated on and the third sub-matrix of the initial matrix to be updated;

The register selection module 340 is used to select a storage vector register and a pre-stored vector register from each vector register according to the block step; the storage vector register is used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle. Sub-matrix; the pre-stored vector register is used to store the first sub-matrix and the second sub-matrix in the next operation cycle;

The result obtaining module 350 is used to sequentially obtain the corresponding sub-matrices from the storage vector register and the pre-stored vector register and perform the matrix multiplication operation until the operation end condition is met to obtain the matrix multiplication operation result.

The embodiment of the present invention obtains the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix by responding to the matrix multiplication operation instruction; determines the blocking step for matrix blocking according to the cache space capacity; according to the According to the blocking step, the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix are divided into matrix blocks to obtain the first sub-matrix and the first sub-matrix of the first to-be-operated matrix respectively. The second sub-matrix of the second matrix to be operated and the third sub-matrix of the initial matrix to be updated; select a storage vector register and a pre-stored vector register from each vector register according to the block step; the storage vector The register is used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; the pre-stored vector register is used to store the first sub-matrix and the second sub-matrix in the next operation cycle; from The corresponding sub-matrix is obtained from the storage vector register and the pre-stored vector register and the matrix multiplication operation is performed until the operation end condition is met, and the matrix multiplication operation result is obtained. The technical solution provided by the embodiment of the present invention improves the operational efficiency of matrix multiplication by optimizing function performance.

Optional, block stride determination module 320 includes:

A unit for determining the number of matrix blocks according to the matrix dimensions of the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix;

The block stride determination unit is used to determine the block strides of the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix in different dimensions according to the cache space capacity for each matrix block number.

Optionally, the block stride determination module 320 includes a matrix block unit, specifically used for:

According to the block stride, the first matrix to be operated, the second matrix to be operated, and the initial matrix to be updated are matrix-blocked to obtain a first sub-matrix of the first matrix to be operated, a second sub-matrix of the second matrix to be operated, and a third sub-matrix of the initial matrix to be updated, respectively, including:

The sub-units obtained by dividing the matrix into blocks are used to calculate the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-operated matrix in different dimensions according to the block steps of the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix under different matrix blocking times. The second matrix to be operated and the initial matrix to be updated are divided into matrix blocks to obtain the first block matrix of the first matrix to be operated, the second block matrix of the second matrix to be operated and the initial block matrix to be updated for each matrix block number. The third block matrix of the matrix;

The sub-matrix determination subunit is used to determine the first block matrix of the first matrix to be operated on the last matrix block number as the first sub-matrix, and determine the second block matrix of the second matrix to be operated as the second block matrix. two sub-matrices, and determine the third block matrix of the initial matrix to be updated as the third sub-matrix.

Optionally, the block step determination module 320 includes a register selection unit, specifically used for:

According to the block step, the storage vector register and the pre-stored vector register are selected from each vector register, including:

The storage register determines the subunit, which is used to determine the first subunit for storing the current operation cycle based on the block steps of the first to-be-operated matrix, the second to-be-operated matrix and the initial to-be-updated matrix in the last matrix block number. Storage vector registers for the matrix, second sub-matrix and third sub-matrix;

The pre-stored register determines the sub-unit, which is used to select the pre-stored vector register from each vector register for storing the first sub-matrix and the second sub-matrix in the next operation cycle according to the number of registers storing the vector register.

Optional, the storage register determines the subunit, specifically used for:

Determine the first storage vector register used to store the first sub-matrix in the current operation cycle according to the block stride of the first matrix to be operated on in the last matrix block count;

Determine the second storage vector register used to store the second sub-matrix in the current operation cycle according to the block stride of the second matrix to be operated on at the last matrix block count;

Determine the third storage vector register used to store the third sub-matrix in the current operation cycle according to the block stride of the initial matrix to be updated in the last matrix block count;

The first storage vector register, the second storage vector register and the third storage vector register are determined as storage registers.

Optional, the pre-stored register determines the subunit, specifically used for:

Select the first pre-stored vector register for storing the first sub-matrix in the next operation cycle from each vector register according to the number of first registers of the first storage vector register;

According to the second register quantity of the second storage vector register, a second pre-stored vector register for storing the second sub-matrix in the next operation cycle is selected from each vector register.

Optionally, the sub-matrix obtaining module 330 also includes a matrix storage unit, including:

A row storage subunit, used to store the first sub-matrix of the first matrix to be operated based on a preset row storage method; and,

The column storage subunit is used to store the second sub-matrix of the second matrix to be operated based on a preset column storage method.

A matrix multiplication execution device provided by an embodiment of the present invention can execute a matrix multiplication execution method provided by any embodiment of the present invention, and has functional modules and beneficial effects corresponding to the execution method.

Embodiment 4

FIG. 4 shows a schematic structural diagram of an electronic device 400 that can be used to implement embodiments of the present invention. Electronic devices are intended to refer to various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic devices may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices (eg, helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are examples only and are not intended to limit the implementation of the invention described and/or claimed herein.

As shown in Figure 4, the electronic device 400 includes at least one processor 410, and a memory communicatively connected to the at least one processor 410, such as a read-only memory (ROM) 420, a random access memory (RAM) 430, etc., wherein the memory stores There is a computer program that can be executed by at least one processor. The processor 410 can perform the operation according to the computer program stored in the read-only memory (ROM) 420 or the computer program loaded from the storage unit 480 into the random access memory (RAM) 430. Perform various appropriate actions and processing. In the (RAM) 430, various programs and data required for the operation of the electronic device 400 may also be stored. The processor 410, (RAM) 420, and (RAM) 430 are connected to each other through a bus 440. An input/output (I/O) interface 450 is also connected to bus 440.

A number of components in the electronic device 400 are connected to the I/O interface 450, including: an input unit 460, such as a keyboard, a mouse, etc.; an output unit 470, such as various types of displays, speakers, etc.; a storage unit 480, such as a disk, an optical disk, etc.; and a communication unit 490, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 490 allows the electronic device 400 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks.

Processor 410 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 410 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors that run machine learning model algorithms, digital signal processing processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 410 performs various methods and processes described above, such as a matrix multiplication operation execution method.

In some embodiments, a matrix multiplication operation execution method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 480. In some embodiments, part or all of the computer program may be loaded and/or installed on the electronic device 400 via (RAM) 420 and/or the communication unit 490. When the computer program is loaded into (RAM) 430 and executed by the processor 410, one or more steps of the matrix multiplication operation execution method described above may be performed. Alternatively, in other embodiments, the processor 410 may be configured to execute a matrix multiplication operation execution method in any other appropriate manner (e.g., by means of firmware).

Various implementations of the systems and techniques described above may be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip implemented in a system (SOC), load programmable logic device (CPLD), computer hardware, firmware, software, and/or a combination thereof. These various embodiments may include implementation in one or more computer programs executable and/or interpreted on a programmable system including at least one programmable processor, the programmable processor The processor, which may be a special purpose or general purpose programmable processor, may receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device. An output device.

Computer programs for implementing the methods of the invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that the computer program, when executed by the processor, causes the functions/operations specified in the flowcharts and/or block diagrams to be implemented. A computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. Computer-readable storage media may include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any suitable combination of the foregoing. Alternatively, the computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, laptop disks, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.

To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having a display device (eg, a CRT (cathode ray tube) or LCD (liquid crystal display)) for displaying information to the user monitor); and a keyboard and pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and may be provided in any form, including Acoustic input, voice input or tactile input) to receive input from the user.

The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., A user's computer having a graphical user interface or web browser through which the user can interact with implementations of the systems and technologies described herein), or including such backend components, middleware components, or any combination of front-end components in a computing system. The components of the system may be interconnected by any form or medium of digital data communication (eg, a communications network). Examples of communication networks include: local area network (LAN), wide area network (WAN), blockchain network, and the Internet.

Computing systems may include clients and servers. Clients and servers are generally remote from each other and typically interact over a communications network. The relationship of client and server is created by computer programs running on corresponding computers and having a client-server relationship with each other. The server can be a cloud server, also known as cloud computing server or cloud host. It is a host product in the cloud computing service system to solve the problems of difficult management and weak business scalability in traditional physical hosts and VPS services. defect.

It should be understood that various forms of the process shown above may be used, with steps reordered, added or deleted. For example, each step described in the present invention can be executed in parallel, sequentially, or in different orders. As long as the desired results of the technical solution of the present invention can be achieved, there is no limitation here.

The above-mentioned specific embodiments do not constitute a limitation on the scope of the present invention. It will be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions are possible depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims (10)

1. A method of performing a matrix multiplication operation, comprising:

responding to a matrix multiplication operation instruction, and acquiring a first matrix to be operated, a second matrix to be operated and an initial matrix to be updated;

determining a block dividing step for dividing the matrix according to the capacity of the buffer memory space;

according to the block stride, performing matrix block on the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated to respectively obtain a first sub-matrix of the first matrix to be operated, a second sub-matrix of the second matrix to be operated and a third sub-matrix of the initial matrix to be updated;

Selecting a stored vector register and a pre-stored vector register from the vector registers according to the block stride; the storage vector register is used for storing a first submatrix, a second submatrix and a third submatrix in the current operation period; the pre-stored vector register is used for storing a first submatrix and a second submatrix in the next operation period;

and sequentially acquiring corresponding submatrices from the stored vector register and the pre-stored vector register to perform matrix multiplication operation until the operation ending condition is met, so as to obtain a matrix multiplication operation result.

2. The method of claim 1, wherein determining a block stride for matrix block based on the buffer space capacity comprises:

determining matrix blocking times according to the matrix dimension sizes of the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated;

and determining the block steps of the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated under different dimensions according to the buffer space capacity.

3. The method according to claim 2, wherein performing matrix partitioning on the first to-be-operated matrix, the second to-be-operated matrix, and the initial to-be-updated matrix according to the partitioning step to obtain a first sub-matrix of the first to-be-operated matrix, a second sub-matrix of the second to-be-operated matrix, and a third sub-matrix of the initial to-be-updated matrix, respectively, includes:

According to the block steps of a first matrix to be operated, a second matrix to be operated and an initial matrix to be updated under different dimensions of each matrix block number, performing matrix block on the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated to obtain a first block matrix of the first matrix to be operated, a second block matrix of the second matrix to be operated and a third block matrix of the initial matrix to be updated under each matrix block number;

determining a first blocking matrix of a first matrix to be operated under the last matrix blocking times as a first sub-matrix, determining a second blocking matrix of a second matrix to be operated as a second sub-matrix, and determining a third blocking matrix of an initial matrix to be updated as a third sub-matrix.

4. The method of claim 2, wherein selecting a stored vector register and a pre-stored vector register from among the vector registers according to the block stride comprises:

determining storage vector registers for storing a first submatrix, a second submatrix and a third submatrix in a current operation period according to the block steps of a first matrix to be operated, a second matrix to be operated and an initial matrix to be updated under the last matrix block times;

And selecting a pre-stored vector register for storing the first submatrix and the second submatrix in the next operation period from each vector register according to the register number of the stored vector registers.

5. The method of claim 4, wherein determining the storage vector registers for storing the first sub-matrix, the second sub-matrix, and the third sub-matrix for the current operation cycle according to the block stride of the first to-be-operated matrix, the second to-be-operated matrix, and the initial to-be-updated matrix for the last number of matrix blocks comprises:

determining a first storage vector register for storing a first submatrix under the current operation period according to the block stride of a first matrix to be operated under the last matrix block times;

determining a second storage vector register for storing a second submatrix under the current operation period according to the block step of the second matrix to be operated under the last matrix block times;

determining a third storage vector register for storing a third submatrix under the current operation period according to the block stride of the initial matrix to be updated under the last matrix block times;

the first, second, and third storage vector registers are determined to be storage registers.

6. The method of claim 5, wherein selecting a pre-stored vector register from each vector register for storing the first sub-matrix and the second sub-matrix for a next operation cycle according to the number of registers storing the vector register, comprises:

selecting a first pre-stored vector register for storing a first submatrix in a next operation period from each vector register according to the first register number of the first stored vector registers;

and selecting a second pre-stored vector register for storing a second submatrix in the next operation period from the vector registers according to the second register number of the second stored vector registers.

7. The method of claim 1, wherein after performing matrix partitioning on the first to-be-operated matrix, the second to-be-operated matrix, and the initial to-be-updated matrix according to the partitioning step, respectively obtaining a first sub-matrix of the first to-be-operated matrix, a second sub-matrix of the second to-be-operated matrix, and a third sub-matrix of the initial to-be-updated matrix, further comprising:

storing a first sub-matrix of the first matrix to be operated based on a preset row storage mode; the method comprises the steps of,

And storing a second submatrix of the second matrix to be operated based on a preset column storage mode.

8. A matrix multiplication execution apparatus, comprising:

the matrix acquisition module is used for responding to the matrix multiplication operation instruction to acquire a first matrix to be operated, a second matrix to be operated and an initial matrix to be updated;

the block stride determination module is used for determining a block stride for matrix block according to the buffer space capacity;

the submatrix obtaining module is used for performing matrix blocking on the first matrix to be operated, the second matrix to be operated and the initial matrix to be updated according to the blocking step, so as to respectively obtain a first submatrix of the first matrix to be operated, a second submatrix of the second matrix to be operated and a third submatrix of the initial matrix to be updated;

the register selecting module is used for selecting a stored vector register and a pre-stored vector register from the vector registers according to the block stride; the storage vector register is used for storing a first submatrix, a second submatrix and a third submatrix in the current operation period; the pre-stored vector register is used for storing a first submatrix and a second submatrix in the next operation period;

The result obtaining module is used for sequentially obtaining corresponding submatrices from the stored vector register and the pre-stored vector register to carry out matrix multiplication operation until the operation ending condition is met, and obtaining a matrix multiplication operation result.

9. An electronic device, comprising:

one or more processors;

a memory for storing one or more programs;

when executed by the one or more processors, causes the one or more processors to implement a matrix multiplication operation performing method as claimed in any one of claims 1 to 7.

10. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements a matrix multiplication operation performing method according to any of claims 1-7.