CN117783841B - FPGA wiring coverage rate testing method, device, equipment and medium - Google Patents
FPGA wiring coverage rate testing method, device, equipment and medium Download PDFInfo
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Abstract
The invention relates to the technical field of chip testing, and discloses a method, a device, equipment and a medium for testing the wiring coverage rate of an FPGA, wherein the method comprises the following steps: acquiring a target wiring area of the FPGA chip, and cutting the target wiring area to obtain a target test area; determining a test path according to the wiring of the target test area; according to the invention, the target wiring area of the FPGA chip is cut to test the target testing area obtained after cutting, so that the process of establishing a test model and a test vector is omitted, the test path is determined according to the wiring of the target testing area, and the automatic coverage test is directly carried out on the target testing area according to the test path, thereby realizing the automatic coverage test and improving the test efficiency.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a method, a device, equipment and a medium for testing the wiring coverage rate of an FPGA.
Background
The FPGA (Field Programmable GateArray ) is a product developed further on the basis of a programmable device, and all units in the FPGA can be communicated through wiring resources, so that the programmable resources, clock control resources and the like in the FPGA device are connected into a whole. The integrity of the FPGA wiring is the basis of the testability of the internal resources of the whole FPGA device, so that the testing of the FPGA wiring coverage rate is very important.
In the prior art, a test model is often built aiming at various functional modules and net results in the FPGA, and a test vector is generated to test the wiring coverage rate. However, as the functions of the programmable devices are more and more, wiring resources inside the FPGA are more and more, and the FPGA is completely tested, the process of building a test model and the process of producing a test vector consume a lot of time, resulting in lower test efficiency.
Disclosure of Invention
In view of the above, the invention provides a method, a device, equipment and a medium for testing the wiring coverage rate of an FPGA, which are used for solving the problems of low testing efficiency caused by consuming a great deal of time when testing by using a test model and a test vector in the prior art.
In a first aspect, the present invention provides a method for testing coverage rate of wirings of an FPGA, the method comprising:
Acquiring a target wiring area of the FPGA chip, and cutting the target wiring area to obtain a target test area;
determining a test path according to the wiring of the target test area;
And performing automatic coverage rate test on the target test area based on the test path to obtain a coverage rate test result.
According to the invention, the target wiring area of the FPGA chip is cut, so that the target test area obtained after cutting is tested, the process of establishing a test model and a test vector is omitted, a test path is determined according to the wiring of the target test area, and the automatic coverage rate test is directly carried out on the target test area according to the test path, so that the automatic coverage rate test is realized, and the test efficiency is improved.
In an alternative embodiment, cutting the target wiring area to obtain a target test area includes:
Acquiring a preset cutting width and a preset cutting height, and cutting the target wiring area based on the preset cutting width and the preset cutting height to obtain a plurality of first target test areas;
Determining connection areas among the first target test areas based on the first target test areas, and establishing a second target test area based on the connection areas;
and determining a target test area based on the plurality of first target test areas and the plurality of second target test areas.
According to the invention, the target wiring area is divided by first cutting according to the preset cutting width and the preset cutting height to obtain a plurality of first target test areas, and a second target test area is established based on the connection area between the first target test areas so as to cover the connection area part between the first target test areas, thereby improving the integrity of the target test areas.
In an alternative embodiment, the FPGA chip is provided with an IO output interface, and the automatic coverage test is performed on the target test area based on the test path to obtain a coverage test result, including:
And carrying out automatic coverage rate test on the target test area based on the test path, and receiving a coverage rate test result through the IO output interface.
According to the coverage rate test method and device, the coverage rate test result is received through the IO output interface, so that the coverage rate test result is directly obtained, and the test result collection efficiency is improved.
In an alternative embodiment, determining a test path from the routing of the target test area includes:
Generating a directed wiring resource diagram corresponding to the target test area;
extracting a vertex set of the directed wiring resource graph, and determining the vertex set as an interconnection line resource in the FPGA chip;
extracting a middle edge set of the directed wiring resource graph, and determining the middle edge set as a programmable interconnection switch among interconnection line resources of the FPGA chip;
a routing tree is established based on the interconnect line resources and the programmable interconnect switches between the interconnect line resources, and a test path is determined based on the structure of the routing tree.
According to the method and the device, the target test area is tested according to the test path by generating the directed wiring resource diagram of the target test area and determining the test path according to the directed wiring resource diagram.
In an alternative embodiment, the automatic coverage test for the target test area based on the test path includes:
Extracting the interconnection relation of the wiring of the target test area;
Modeling the target test areas based on the interconnection relation, and generating test images corresponding to the target test areas;
and according to the test path, sequentially performing automatic coverage rate test on the test images of the target test area based on the flow algorithm.
According to the invention, the interconnection relation of the wiring of the target test area is extracted to generate the test images corresponding to each target test area, so that the test images are tested in sequence according to the test sequence of the test path, and the automatic coverage rate test is realized.
In an alternative embodiment, the streaming algorithm comprises a breadth-first search algorithm or a depth-first search algorithm.
According to the coverage rate testing method and the coverage rate testing device, coverage rate testing is conducted on the target testing area through the flow algorithm, so that the efficiency and accuracy of coverage rate testing are improved.
In an alternative embodiment, a plurality of test nodes are arranged on the test image, and the automatic coverage rate test is performed on the test image of the target test area based on a flow algorithm, including:
traversing the test nodes on the test image based on a flow algorithm, and performing automatic coverage rate test on the test nodes;
And stopping the coverage rate test of the test node when the completion of the traversal of the test node is detected.
According to the method, the test nodes on the test image are traversed through the flow algorithm, and the progress of coverage rate test is determined according to the traversing progress of the test nodes, so that the coverage rate test is automatically stopped.
In a second aspect, the present invention provides an FPGA wiring coverage testing apparatus, the apparatus comprising:
the cutting module is used for obtaining a target wiring area of the FPGA chip, cutting the target wiring area and obtaining a target test area;
the determining module is used for determining a test path according to the wiring of the target test area;
And the test module is used for carrying out automatic coverage rate test on the target test area based on the test path to obtain a coverage rate test result.
In a third aspect, the present invention provides a computer device comprising: the FPGA wiring coverage test method comprises a memory and a processor, wherein the memory and the processor are in communication connection, the memory stores computer instructions, and the processor executes the computer instructions so as to execute the FPGA wiring coverage test method of the first aspect or any corresponding implementation mode.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to execute the FPGA wiring coverage testing method of the first aspect or any of the embodiments corresponding thereto.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow diagram of a method for testing FPGA wire coverage according to an embodiment of the invention;
FIG. 2 is a schematic diagram of an FPGA chip for region division according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a secondary dicing of an FPGA chip into partitioned areas according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a secondary cut dividing region when an FPGA row is cut according to an embodiment of the present invention;
FIG. 5 is a block diagram of a configuration of an FPGA wire coverage test apparatus according to an embodiment of the present invention;
Fig. 6 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The programmable interconnection lines are vital resources in the FPGA device, a programmable switch array exists between the interconnection lines in the FPGA device, and connection or insulation between the interconnection lines is carried out according to the requirements of users, so that the function of designing the device is realized. In order to reduce or eliminate wiring faults in an FPGA device, the product is guaranteed to have higher programming reliability, and the method plays an extremely important role in testing the wiring coverage rate.
According to an embodiment of the present invention, there is provided an FPGA wire coverage testing method embodiment, it should be noted that the steps shown in the flowchart of the drawings may be performed in a computer system such as a set of computer executable instructions, and that although a logic sequence is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than what is shown herein.
In this embodiment, a method for testing the coverage rate of an FPGA wire is provided, fig. 1 is a flowchart of a method for testing the coverage rate of an FPGA wire according to an embodiment of the present invention, and as shown in fig. 1, the flowchart includes the following steps:
step S101, obtaining a target wiring area of the FPGA chip, and cutting the target wiring area to obtain a target test area.
In the embodiment of the invention, cutting is performed on the target wiring area of the FPGA chip, the target wiring area is divided into a plurality of target test areas by performing row cutting and column cutting on the target wiring area, and the cut areas are determined as target test areas. As shown in fig. 2, fig. 2 is a connection diagram of the FPGA chip 3*3. In fig. 2, the FPGA chip is cut into 9 regions, B (1, 3), B (2, 3), B (3, 3), B (1, 2), B (2, 2), B (3, 2), B (1, 1), B (2, 1), B (3, 1), respectively.
Specifically, the line type of the FPGA has attributes such as length and direction, for example, the direction attributes include easting, westward, southward, northing, 1-fold length, 2-fold length … … -fold length, etc. The number of rows and columns of the target test area is required to be larger than the maximum length of the connecting line, for example, the maximum line length in the FPGA chip is L times longer, and then the number of rows and columns of the target test area are both larger than L.
Step S102, determining a test path according to the wiring of the target test area.
In the embodiment of the invention, a path is selected according to the wiring mode in the target test area, and a coverage rate test path is generated so as to perform coverage rate test according to the test path.
And step S103, performing automatic coverage rate test on the target test area based on the test path to obtain a coverage rate test result.
In the embodiment of the invention, the FPGA chip is provided with an IO input interface and an IO output interface, and a test signal is input into a target test area through the IO input interface and is used as a test excitation signal to be input. And taking the test signal as a starting signal of coverage rate test, starting to perform automatic coverage rate test on the target test area according to the test path when the input of the test signal is detected, and receiving a coverage rate test result through the IO output interface.
And the coverage rate test result is received through the IO output interface, so that the coverage rate test result is directly obtained, and the test result acquisition efficiency is improved.
According to the FPGA wiring coverage rate testing method, the target wiring area of the FPGA chip is cut, so that the target testing area obtained after cutting is tested, the process of building a testing model and a testing vector is omitted, a testing path is determined according to the wiring of the target testing area, automatic coverage rate testing is directly conducted on the target testing area according to the testing path, automatic coverage rate testing is achieved, and testing efficiency is improved.
Specifically, in an embodiment, the step S101 of cutting the target wiring area to obtain the target test area specifically includes the following steps:
Step S1011, obtaining a preset cutting width and a preset cutting height, and cutting the target wiring area based on the preset cutting width and the preset cutting height to obtain a plurality of first target test areas.
Step S1012, determining connection areas between the first target test areas based on the plurality of first target test areas, and establishing a second target test area based on the connection areas.
In step S1013, a target test area is determined based on the plurality of first target test areas and the plurality of second target test areas.
In the embodiment of the invention, the preset cutting width and cutting height are obtained, and the target wiring area is cut for the first time. The preset cutting width and the preset cutting height may be preset, or may be set correspondingly according to the size of the FPGA chip, which is not limited herein.
And performing column cutting on the target wiring area based on a preset cutting width, performing row cutting on the target wiring area based on a preset cutting height, taking n rows and m columns of cutting on the target wiring area as an example, wherein the cut target wiring area has m x n first target test areas.
After the first cutting is completed, since the connection line between the areas in the first target test area is not covered, a second target test area is established based on the connection area between the first target test areas, as shown in fig. 3, the area selected by the white thickened line in fig. 3 is the second target test area, and the second target test area covers the connection line area between the areas in the first target test area. And determining the first target test areas and the second target test areas as target test areas.
As shown in fig. 4, fig. 4 is an example of cutting an FPGA CHIP into four rows, namely, block0, block1, block2, and Block3, in the first time of cutting, block4 is established based on a connection region between Block0 and Block1, block5 is established based on a connection region between Block1 and Block2, and Block6 is established based on a connection region between Block2 and Block3, in the second time of cutting. Fig. 4 is only an example of performing row dicing on FPGA CHIP, and in practical application, column dicing may be performed according to FPGA CHIP, or both row and column dicing may be performed.
Wherein the width and height of the second target test area are related to the maximum line length supported by the FPAG chip. For example, if the maximum line length supported by the FPGA chip is 12 times of the line length, the width and the height of the second target test area are not less than 24 rows or 24 columns.
The target wiring areas are divided by performing first cutting according to the preset cutting width and the preset cutting height to obtain a plurality of first target test areas, and a second target test area is established based on the connection areas among the first target test areas so as to cover the connection area parts among the first target test areas, so that the integrity of the target test areas is improved.
Specifically, in one embodiment, the determining a test path according to the wiring of the target test area in the step S102 specifically includes the following steps:
step S1021, generating a directed wiring resource map corresponding to the target test area.
Step S1022, extracting a vertex set of the directed wiring resource graph, and determining the vertex set as the interconnection line resource in the FPGA chip.
Step S1023, extracting a middle edge set of the directed wiring resource diagram, and determining the middle edge set as a programmable interconnection switch between interconnection line resources of the FPGA chip.
Step S1024, build a routing tree based on the interconnect line resources and the programmable interconnect switches between the interconnect line resources, and determine a test path based on the structure of the routing tree.
In the embodiment of the invention, the target test area of the FPGA is abstracted, and the hardware resources in the target test area are abstracted into a directed wiring resource graph (Routing Resource Graph, RRG), G= (V, E). And extracting vertexes V, V epsilon V in the directed wiring resource diagram, wherein V represents a vertex set, and the vertex set represents interconnection line resources or pins of logic units inside the FPGA chip. And extracting middle edges E, E E and E in the directed wiring resource diagram, wherein the middle edges E and E represent middle edge sets, and the middle edge sets represent programmable interconnection switches between interconnection line resources of the FPGA chip or programmable interconnection switches between logic resource pins and the interconnection line resources.
The directional wiring resource diagram is used as a link between a wiring algorithm and FPGA hardware, the FPGA wiring problem is converted into a solution problem of the shortest path in the graph theory, the wiring algorithm directly executes wiring operation on a circuit wire net on the directional wiring resource diagram, and a wiring Tree (RT) of the wire net N i is built based on a vertex set V and a middle edge set E, namelyThe test path is determined based on the logic cell order of the wiring tree structure, and a path formed by the arrangement order of the logic cells may be sequentially determined as the test path in the horizontal direction from the first logic cell of the wiring tree.
And determining a test path according to the directed wiring resource diagram by generating the directed wiring resource diagram of the target test area so as to test the target test area according to the test path.
Specifically, in an embodiment, the step S103 performs an automatic coverage test on the target test area based on the test path to obtain a coverage test result, and specifically includes the following steps:
Step S1031, extracting the interconnection relationship of the target test area wiring.
Step S1032, modeling the target test areas based on the interconnection relation, and generating test images corresponding to the target test areas.
Step S1033, according to the test path, the automatic coverage rate test is sequentially carried out on the test images of the target test area based on the flow algorithm.
In the embodiment of the invention, the interconnection relation of the wiring in the target test area is extracted, the interconnection relation is modeled into a graph, and a test image of each target test area is generated. And determining the test sequence of the test images according to the test path, and sequentially performing automatic coverage rate test on the test images according to the test sequence based on a flow algorithm after determining the test sequence.
Specifically, since each target test area is independent, when the automatic coverage rate test is performed on the target test area based on the stream algorithm, the stream algorithms of different test areas can be run in parallel.
And extracting the interconnection relation of the wiring of the target test area to generate test images corresponding to each target test area, and sequentially testing the test images according to the test sequence of the test path, thereby realizing automatic coverage rate test.
Specifically, in an embodiment, the step S1033 of automatically testing the coverage rate of the test image of the target test area based on the flow algorithm sequentially includes the following steps:
Step S10331, traversing the test nodes on the test image based on the flow algorithm, and performing automatic coverage rate test on the test nodes.
And step S10332, stopping the coverage rate test of the test node when the completion of the test node traversal is detected.
In the embodiment of the invention, the streaming algorithm comprises a breadth-First-Search (BFS) algorithm or a Depth-First-Search (DFS) algorithm, and the two streaming algorithms are Search algorithms adopted in graph theory. And a plurality of test nodes are arranged on the test image, the flow algorithm traverses the test nodes until the test node traverses are completed, and the coverage rate test of the test nodes is stopped.
And carrying out coverage rate test on the target test area through a flow algorithm to improve the efficiency and accuracy of the coverage rate test, and determining the progress of the coverage rate test according to the traversing progress of the test node so as to realize automatic coverage rate test stopping.
Specifically, when the breadth-first search algorithm is adopted, firstly starting from the starting point of the test node, traversing the test node on the test image layer by layer until the target node is found, namely completing the traversal of the detection node. When the depth-first search algorithm is adopted, starting from the starting point of the test node, traversing to the bottom along a test path until the target node is found, and completing the traversal of the detection node.
Taking an FPGA with m×n test areas as an example, each block has l wires, and the chip has m×n×l wires, and the complexity of the flow algorithm running is O ((m×n×l)/(2)). When the FPGA chip is cut into four rows and four columns respectively, namely, the FPGA chip is divided into 16 areas, the operation complexity of the flow algorithm is O ((m x n l/16)/(2)), namely, the operation time is changed into 1/256 originally, and the time cost is greatly reduced.
The embodiment also provides an FPGA wiring coverage rate testing device, which is used for implementing the foregoing embodiments and preferred implementations, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The embodiment provides an FPGA wiring coverage rate testing device, as shown in fig. 5, including:
The cutting module 501 is configured to obtain a target wiring area of the FPGA chip, and cut the target wiring area to obtain a target test area.
A determining module 502, configured to determine a test path according to the wiring of the target test area.
And the test module 503 is configured to perform an automatic coverage rate test on the target test area based on the test path, so as to obtain a coverage rate test result.
In some alternative embodiments, the cutting module 501 includes:
the cutting unit is used for acquiring a preset cutting width and a preset cutting height, and cutting the target wiring area based on the preset cutting width and the preset cutting height to obtain a plurality of first target test areas.
The first determining unit is used for determining connection areas among the first target test areas based on the first target test areas, and establishing a second target test area based on the connection areas.
And the second determining unit is used for determining the target test area based on the plurality of first target test areas and the second target test area.
In some alternative embodiments, the test module 503 includes:
and the receiving unit is used for carrying out automatic coverage rate test on the target test area based on the test path and receiving the coverage rate test result through the IO output interface.
In some alternative embodiments, the determining module 502 includes:
and the generating unit is used for generating a directed wiring resource diagram corresponding to the target test area.
And the first extraction unit is used for extracting the vertex set of the directed wiring resource graph and determining the vertex set as the interconnection line resource in the FPGA chip.
And the second extraction unit is used for extracting the middle edge set of the directed wiring resource graph and determining the middle edge set as a programmable interconnection switch among interconnection line resources of the FPGA chip.
And a third determining unit for establishing a wiring tree based on the interconnection line resources and the programmable interconnection switches between the interconnection line resources, and determining a test path based on the structure of the wiring tree.
In some alternative embodiments, the test module 503 further includes:
and a third extraction unit for extracting an interconnection relation of the target test area wiring.
And the modeling unit is used for modeling the target test areas based on the interconnection relation and generating test images corresponding to the target test areas.
And the test unit is used for sequentially carrying out automatic coverage rate test on the test images of the target test area based on the flow algorithm according to the test path.
In some alternative embodiments, the test unit includes:
and the traversing subunit is used for traversing the test nodes on the test image based on the flow algorithm and carrying out automatic coverage rate test on the test nodes.
And the stopping test subunit is used for stopping the coverage rate test of the test node when the completion of the traversal of the test node is detected.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The FPGA wiring coverage test device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application SPECIFIC INTEGRATED Circuit) Circuit, a processor and a memory that execute one or more software or firmware programs, and/or other devices that can provide the above functions.
The embodiment of the invention also provides computer equipment, which is provided with the FPGA wiring coverage rate testing device shown in the figure 5.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 6, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 6.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform a method for implementing the embodiments described above.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The computer device further comprises input means 30 and output means 40. The processor 10, memory 20, input device 30, and output device 40 may be connected by a bus or other means, for example in fig. 6.
The input means 30 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the computer device, such as a touch screen or the like. The output means 40 may comprise a display device or the like.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (9)
1. The FPGA wiring coverage rate testing method is characterized by comprising the following steps of:
Acquiring a target wiring area of an FPGA chip, and cutting the target wiring area to obtain a target test area;
determining a test path according to the wiring of the target test area;
performing automatic coverage rate test on the target test area based on the test path to obtain a coverage rate test result;
The step of cutting the target wiring area to obtain a target test area includes:
acquiring a preset cutting width and a preset cutting height, and cutting the target wiring area based on the preset cutting width and the preset cutting height to obtain a plurality of first target test areas;
Determining connection areas among the first target test areas based on the first target test areas, and establishing a second target test area based on the connection areas;
and determining a target test area based on the plurality of first target test areas and the second target test area.
2. The method of claim 1, wherein the FPGA chip is provided with an IO output interface, and the automatic coverage test is performed on the target test area based on the test path to obtain a coverage test result, including:
And carrying out automatic coverage rate test on the target test area based on the test path, and receiving a coverage rate test result through the IO output interface.
3. The method of claim 1, wherein the determining a test path from the routing of the target test area comprises:
Generating a directed wiring resource diagram corresponding to the target test area;
Extracting a vertex set of the directed wiring resource graph, and determining the vertex set as an interconnection line resource in an FPGA chip;
Extracting a middle edge set of the directed wiring resource graph, and determining the middle edge set as a programmable interconnection switch between interconnection line resources of an FPGA chip;
And establishing a wiring tree based on the interconnection line resource and the programmable interconnection switch between the interconnection line resources, and determining a test path based on the structure of the wiring tree.
4. The method of claim 2, wherein the automatically testing the target test area for coverage based on the test path comprises:
extracting the interconnection relation of the target test area wiring;
Modeling the target test areas based on the interconnection relation, and generating test images corresponding to the target test areas;
and according to the test path, sequentially performing automatic coverage rate test on the test images of the target test area based on a flow algorithm.
5. The method of claim 4, wherein the streaming algorithm comprises a breadth-first search algorithm or a depth-first search algorithm.
6. The method of claim 4, wherein the test image has a plurality of test nodes, and the automatic coverage test for the test image of the target test area based on a streaming algorithm comprises:
Traversing the test nodes on the test image based on a flow algorithm, and performing automatic coverage rate test on the test nodes;
And stopping the coverage rate test of the test node when the completion of the traversal of the test node is detected.
7. An FPGA wiring coverage test apparatus, the apparatus comprising:
The cutting module is used for obtaining a target wiring area of the FPGA chip, cutting the target wiring area and obtaining a target test area;
A determining module, configured to determine a test path according to the wiring of the target test area;
The test module is used for carrying out automatic coverage rate test on the target test area based on the test path to obtain a coverage rate test result;
The cutting module is specifically used for:
acquiring a preset cutting width and a preset cutting height, and cutting the target wiring area based on the preset cutting width and the preset cutting height to obtain a plurality of first target test areas;
Determining connection areas among the first target test areas based on the first target test areas, and establishing a second target test area based on the connection areas;
and determining a target test area based on the plurality of first target test areas and the second target test area.
8. A computer device, comprising:
A memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the FPGA wire coverage testing method of any of claims 1-6 by executing the computer instructions.
9. A computer-readable storage medium having stored thereon computer instructions for causing a computer to execute the FPGA wire coverage testing method of any one of claims 1 to 6.
Priority Applications (1)
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| CN101881811B (en) * | 2009-05-08 | 2012-10-24 | 复旦大学 | Fault testing method for interconnection resource of programmable logic device |
| CN116029254B (en) * | 2023-01-06 | 2024-04-12 | 中山大学 | A method and system for automatic wiring of integrated circuit layout based on path optimization |
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| CN108051729A (en) * | 2017-12-06 | 2018-05-18 | 西安智多晶微电子有限公司 | FPGA connects up coverage rate test method |
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