CN117747593A - Semiconductor package assembly - Google Patents

Abstract

The invention discloses a semiconductor packaging component, including: a first semiconductor die and a second semiconductor die arranged side by side, wherein the first semiconductor die includes: a first interface; and a second interface arranged on the first a second edge of a semiconductor die close to the second semiconductor die, and the second edge is connected to the first edge; and a third semiconductor die stacked on the first semiconductor die and on the second semiconductor die, wherein the third semiconductor die is electrically connected to the first semiconductor die through the first interface, and wherein the first semiconductor die is electrically connected through the second interface connected to the second semiconductor die. The present invention can electrically connect the first semiconductor die to the memory package in a shorter path, thereby minimizing the wiring length between different components and improving the flexibility of the channel design of the semiconductor package component.

Description

Semiconductor packaging components

Technical field

The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor packaging component.

Background technique

As the demand for smaller devices with more functions continues to increase, package-on-package (PoP) technology has become increasingly popular. PoP technology vertically stacks two or more packages and minimizes trace lengths between different components such as controllers and storage devices. This provides better electrical performance because shorter interconnect traces produce faster signal propagation and reduce noise and crosstalk defects.

Although existing semiconductor packaging components are generally adequate, they are not satisfactory in every aspect. For example, meeting the channel requirements for integrating different components into a package is a challenge. Therefore, there is a need for further improvements in semiconductor packaging components to provide flexibility in channel design.

Contents of the invention

In order to solve the above problems, the present invention provides a semiconductor packaging component to solve the above problems.

According to a first aspect of the present invention, a semiconductor packaging component is disclosed, including:

A first semiconductor die and a second semiconductor die stacked on each other, wherein the first semiconductor die includes a first interface that overlaps and electrically connects a second interface disposed on the second semiconductor die. a second interface; and a third interface arranged on the first edge of the first semiconductor die; and

A memory package is located next to the first semiconductor die, wherein the memory package is electrically connected to the first semiconductor die through the third interface.

Further, the first semiconductor die has a first critical dimension and the second semiconductor die has a second critical dimension, wherein the first critical dimension is narrower than the second critical dimension. As a result, the more advanced first semiconductor die is used as the die to control the third semiconductor die and its corresponding packaging, so that it can be applied to higher-speed scenarios and enable the semiconductor package components to have more efficient processing capabilities.

Further, the first semiconductor die includes a fourth interface arranged on a second edge of the first semiconductor die and connected to the first edge, wherein the memory package is electrically connected through the fourth interface. Connected to the first semiconductor die and the second semiconductor die. This allows for more connection paths, making the connection channel more flexible.

Further, the first semiconductor die and the memory package are arranged side by side along a first direction, and wherein the first semiconductor die is stacked on the second package along a second direction different from the first direction. on semiconductor dies. Thus, it is possible, for example, for the first semiconductor die and the memory package to be arranged side by side in the horizontal direction, while the first semiconductor die is stacked on the second semiconductor die in the vertical direction.

Further, the third interface is arranged adjacent to the first interface and between the first interface and the memory package along the first direction. The interface design thus formed can make the connection paths between the first semiconductor die and the second semiconductor die, between the first semiconductor die and the memory package, and between the second semiconductor die and the memory package shorter.

Further, the second semiconductor die includes:

A first via (TV) interconnect disposed in the second semiconductor die and overlapping and electrically connected to the third interface of the first semiconductor die; and

A second TV interconnect is disposed within the second interface and electrically connected to the first interface of the first semiconductor die. Therefore, the first semiconductor die and the memory package are electrically connected through the first TV interconnection, the first semiconductor die and the second semiconductor die are electrically connected through the second TV interconnection, and the first semiconductor die can also be electrically connected through the second TV interconnection. The die, the second semiconductor die, and the memory package are electrically connected.

Further, the second semiconductor die includes a trench capacitor embedded in the second semiconductor die and electrically connected to the memory package through a third interface of the first semiconductor die. Thus, the capacitance value of the semiconductor package component can be increased in a more space-saving manner.

According to a second aspect of the present invention, a semiconductor packaging component is disclosed, including:

A first semiconductor die and a second semiconductor die stacked on each other, wherein the first semiconductor die includes a first interface that overlaps and electrically connects a second interface disposed on the second semiconductor die. a second interface; a third interface arranged on the first edge of the first semiconductor die; and

a memory package located next to the second semiconductor die, wherein the memory package is electrically connected to the first semiconductor die through the third interface;

The second semiconductor die and the memory package are arranged side by side in a first direction, and wherein the second semiconductor die and the memory package are stacked in the second direction in a second direction different from the first direction. on the first semiconductor die. In this way, the first semiconductor die located underneath can be used to control the memory package. The electrical connection path between the first semiconductor die and the memory package is short, thereby minimizing the trace length between different components. , provide better electrical performance, faster signal propagation, and reduce noise and crosstalk defects, and improve the flexibility of channel design of semiconductor package components; and because the second semiconductor die is arranged side by side with the memory package, the second semiconductor die The thickness of the grains can be larger, thereby improving the thermal properties of the second semiconductor die.

Further, the third interface is arranged to overlap the memory package along the second direction. Therefore, the electrical connection path between the first semiconductor die and the memory package is shorter.

Further, the first interface is arranged on a third edge of the first semiconductor die and the third edge is opposite to the first edge. This allows the first semiconductor die to set interfaces with different functions on two opposite edges respectively, while meeting a short communication path for the second semiconductor die and the memory package.

Further, the first semiconductor die includes:

A first through-hole (TV) interconnect disposed within the third interface and electrically connected to the memory package; and

A second TV interconnect is disposed within the first interface and electrically connected to the second interface of the second semiconductor die. The first semiconductor die is thereby connected to the memory package and the second semiconductor die respectively.

Further, the memory package includes first conductive structures arranged in groups and having first distribution areas, and the first TV interconnects have second distribution areas corresponding to and at least partially overlapping the first distribution areas. This allows the first semiconductor die to be connected to the memory package and the conductive structure of the memory package with a shorter electrical or communication path.

Further, the first TV interconnection is arranged in a first column and a second column adjacent to the first column, and includes:

Ground TV interconnections, arranged in said first column only; and

Signal TV interconnections, arranged in said first column and said second column, wherein the signal TV interconnections in said first column are interleaved with ground TV interconnections, and the signal TV interconnections in the second column are interleaved with Ground TV interconnection is adjacent. Thereby reducing crosstalk between adjacent signal TV interconnects.

Further, the first semiconductor die includes a trench capacitor embedded in the third interface and electrically connected to the memory package. Thus, the overall capacitance value of the semiconductor package component is increased without almost increasing the planar area of the package.

Furthermore, it also includes:

A fan-out package includes the first semiconductor die, the second semiconductor die and the memory package, wherein the fan-out package further includes:

A first redistribution layer (RDL) structure is disposed between the first semiconductor die and the second semiconductor die, wherein the first RDL structure is electrically connected to the first interface, the second interface, the third interface and the memory package;

a second redistribution layer (RDL) structure electrically connected to the first RDL structure and separated from the memory package by the first RDL structure;

A first molding compound covering the first RDL structure and the memory package;

a second molding compound filling the space between the first RDL structure and the second RDL structure;

a third TV interconnect passing through the second molding compound and electrically connected to the first RDL structure and the second RDL structure; and

The second conductive structure is in contact with and electrically connected to the second RDL structure. The third TV interconnect may be a via through the molding compound to make a connection such as power or ground.

Further, the first semiconductor die includes a fifth interface arranged adjacent to the third interface and closer to the first edge than the third interface. The fifth interface can be an input/output interface, so that interfaces with different functions can be configured to meet needs.

Further, the fifth interface is electrically connected to the second conductive structure outside the first edge through the second RDL structure instead of the first RDL structure. As a result, the input/output interface is connected to external or substrate components via a shorter communication or electrical connection path, resulting in higher communication efficiency and less interference.

According to a third aspect of the present invention, a semiconductor packaging component is disclosed, including:

Fan-out packaging, including:

memory packaging;

A first semiconductor die arranged next to the memory package along a first direction; and

A second semiconductor die is arranged next to the memory package along a second direction, wherein the first semiconductor die includes: a first interface that overlaps with a second interface arranged on the second semiconductor die and electrically connecting the second interface; and a third interface disposed close to the memory package and electrically connected to the memory package. Using this method can make the electrical connection path between the second semiconductor die and the memory package shorter, thereby minimizing the trace length between different components and providing better electrical performance and faster signal propagation. , and reduce noise and crosstalk defects, and improve the flexibility of channel design of semiconductor package components; and because the first semiconductor die and the memory package are arranged side by side, the thickness of the first semiconductor die can be larger, thereby improving the first semiconductor die. Thermal properties of particles.

Further, the first semiconductor die includes a fourth interface, wherein the third interface and the fourth interface are arranged on adjacent edges of the first semiconductor die, wherein the memory package passes through A fourth interface of a semiconductor die is electrically connected to the first semiconductor die. As a result, the first semiconductor die has more diverse and different communication or electrical connection paths with the memory package, and the design flexibility is higher.

Furthermore, it also includes:

A first redistribution layer (RDL) structure is disposed between the first semiconductor die and the second semiconductor die, wherein the first RDL structure is electrically connected to the first interface, the second interface, the third interface and the memory package; and

A second redistribution layer (RDL) structure is electrically connected to the first RDL structure and is separated from the memory package by the first RDL structure. To meet the communication and electrical connections in the package and between the package and other components.

Further, the first semiconductor die is disposed between the first RDL structure and the second RDL structure and includes a through-hole (TV) interconnect disposed in the first interface and the third interface. even. To perform electrical connection between the first RDL structure and the second RDL structure.

Further, the memory package includes first conductive structures arranged in groups and having first distribution areas; and the TV interconnect arranged within the third interface has a second distribution area, the second distribution area corresponding to The first distribution areas overlap at least partially. Thereby shortening the electrical connection path between the semiconductor die and the memory package.

Further, the TV interconnection provided in the third interface is arranged in a first column and a second column adjacent to the first column, and includes:

Ground TV interconnections, arranged in said first column only; and

Signal TV interconnections, arranged in said first column and said second column, wherein the signal TV interconnections in said first column are interleaved with ground TV interconnections, and the signal TV interconnections in the second column are interleaved with Ground TV interconnection is adjacent. Thereby reducing crosstalk between adjacent signal TV interconnects.

Further, the first semiconductor die includes the fifth interface adjacent to the third interface and arranged on the first edge of the first semiconductor die, such that the third interface is along the The second direction is arranged between the first interface and the fifth interface. This makes interface layout more flexible.

Further, the fifth interface is electrically connected to the second conductive structure, the second conductive structure contacts and is electrically connected to the second redistribution layer structure through the second RDL structure instead of the first RDL structure, and the The second conductive structure is located outside the first edge. This results in a shorter path to the memory package and its conductive structures.

Further, the first semiconductor die includes a trench capacitor embedded in the third interface and electrically connected to the memory package through the first RDL structure. To increase the capacitance value without increasing the lateral area of the package as much as possible.

Further, the second semiconductor die is disposed between the first RDL structure and the second RDL structure and includes overlap with the first interface and the third interface of the first semiconductor die. through-hole (TV) interconnects. to electrically connect the first RDL structure and the second RDL structure.

Further, the second semiconductor die includes a trench capacitor embedded in the second semiconductor die, wherein the trench capacitor overlaps the third interface and is electrically connected to the memory package. To increase the capacitance value without increasing the lateral area of the package as much as possible.

According to a fourth aspect of the present invention, a semiconductor packaging component is disclosed, including:

Fan-out packaging, including:

A first redistribution layer (RDL) structure and a second RDL structure stacked on each other;

a top semiconductor die and a memory package disposed on a first redistribution layer (RDL) structure, wherein the top semiconductor die includes a first interface; and

A bottom semiconductor die disposed between the first RDL structure and the second RDL structure, wherein the bottom semiconductor die includes: a second interface overlapping the first interface; and a first via ( TV) interconnect disposed within the second interface and electrically connected to the first interface through the first RDL structure, and

wherein the memory package is electrically connected to the top semiconductor die and the bottom semiconductor die through the first RDL structure rather than the second RDL structure. The top semiconductor die can be electrically connected to the memory package in a shorter path, minimizing trace lengths between different components, providing better electrical performance, faster signal propagation, and reduced noise and crosstalk defects, and improves the flexibility of channel design of semiconductor package components; and because the top semiconductor die is disposed side by side with the memory package, the thickness of the top semiconductor die can be larger, thereby improving the thermal performance of the top semiconductor die.

Further, the top semiconductor die includes a third interface located next to the first interface and close to the memory package, wherein the memory package is electrically connected to the top semiconductor die through the third interface. This increases the connection paths and channels to the memory package and makes the design more flexible.

Further, the bottom semiconductor die includes a second via (TV) interconnect overlapping the third interface and electrically connected to the third interface through the first RDL structure. Thereby electrical connections are made through via (TV) interconnections.

Further, the bottom semiconductor die includes a fourth interface overlapping the memory package, wherein the memory package is electrically connected to the bottom semiconductor die through the fourth interface. This allows the bottom semiconductor die to be connected to the memory package via a shorter path.

Further, the bottom semiconductor die includes a fifth interface arranged adjacent to the fourth interface and located on a first edge of the bottom semiconductor die, such that the fourth interface is disposed on the second interface and the fifth interface. This makes interface configuration more flexible and comprehensive.

Further, the bottom semiconductor die includes a third via (TV) interconnect disposed within the fourth interface and electrically connected to the memory package. Thereby shortening the electrical connection path.

Further, the third TV interconnection is arranged in the first column and the second column adjacent to the first column, and includes:

Ground TV interconnections, arranged in said first column only; and

Signal TV interconnections, arranged in said first column and said second column, wherein the signal TV interconnections in said first column are interleaved with ground TV interconnections, and the signal TV interconnections in the second column are interleaved with Ground TV interconnection is adjacent. Thereby reducing crosstalk between adjacent signal TV interconnects.

Further, the bottom semiconductor die includes a trench capacitor embedded in the bottom semiconductor die and electrically connected to the memory package. To increase the capacitance value without increasing the lateral area of the package as much as possible.

The semiconductor package component of the present invention includes: a first semiconductor die and a second semiconductor die stacked on each other, wherein the first semiconductor die includes: a first interface, and a first interface arranged on the second semiconductor die. A second interface overlaps and electrically connects the second interface; and a third interface is arranged on the first edge of the first semiconductor die; and a memory package is located next to the first semiconductor die, wherein the A memory package is electrically connected to the first semiconductor die through the third interface. Using the above-mentioned solution of the present invention, the first semiconductor die can be electrically connected to the memory package in a shorter path, thereby minimizing the wiring length between different components, providing better electrical performance, faster signal propagation, reducing noise and crosstalk defects, and improving the flexibility of channel design of semiconductor package components; and because the first semiconductor die is arranged side by side with the memory package, the thickness of the first semiconductor die can be larger, thereby improving the Thermal properties of a semiconductor die.

Description of drawings

1A is a cross-sectional view of a semiconductor package assembly in accordance with some embodiments of the present specification;

1B and 1C are bottom perspective views of a fan-out package in a semiconductor package assembly according to some embodiments of the present specification, showing the interface arrangement of the top and bottom semiconductor chips and the through vias of the bottom semiconductor chip. TV) interconnection;

2A is a cross-sectional view of a semiconductor package assembly in accordance with some embodiments of the present specification;

2B, 2C, and 2D are bottom perspective views of a fan-out package in a semiconductor package assembly showing interface arrangements of top and bottom semiconductor chips and through-hole (TV) interconnections of the bottom semiconductor chip in accordance with some embodiments of the present specification;

2E is an enlarged plan view of a bottom semiconductor chip of a fan-out package in a semiconductor package assembly according to some embodiments of the present disclosure, showing the arrangement of through-hole (TV) interconnects of the bottom semiconductor chip;

3A is a cross-sectional view of a semiconductor package assembly in accordance with some embodiments of the present specification;

3B is a bottom perspective view of a fan-out package in a semiconductor package assembly, showing the interface arrangement of the top and bottom semiconductor chips, the through-hole (TV) interconnects of the bottom semiconductor chip, and the conductive conductors of the semiconductor package assembly in accordance with some embodiments of the present disclosure. structure;

4 is a cross-sectional view of a semiconductor package assembly in accordance with some embodiments of the present specification;

Figure 5 is a cross-sectional view of a semiconductor package assembly in accordance with some embodiments of the present specification;

6 is an enlarged cross-sectional view of a semiconductor package assembly showing a trench capacitor embedded in the bottom semiconductor chip of the fan-out package, in accordance with some embodiments of the present disclosure.

Detailed ways

In the following detailed description of one embodiment according to the invention, reference is made to the accompanying drawings, which form a part hereof and in which show by way of illustration specific embodiments in which the invention may be practiced. Preferred embodiment. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and mechanical, structural and structural changes may be made without departing from the spirit and scope of the invention. and procedural changes. this invention. Accordingly, the following detailed description is not to be construed as limiting, and the scope of one embodiment in accordance with the invention is defined only by the appended claims. The drawings described are illustrative only and not restrictive. In the drawings, the dimensions of some elements may be exaggerated and not drawn to scale for illustrative purposes. In the practice of the invention, dimensions and relative dimensions do not correspond to actual dimensions.

It will be understood that, although the terms "first," "second," "third," "primary," "secondary," etc. may be used herein to describe various components, components, regions, layers and/or sections , but these components, components, regions, layers and/or portions shall not be limited by these terms. These terms are only used to distinguish one component, component, region, layer or section from another region, layer or section. Thus, a first or primary component, component, region, layer or section discussed below could be termed a secondary or secondary component, component, region, layer or section without departing from the teachings of the inventive concept.

In addition, for convenience of description, terms such as “below”, “under”, “below”, “above”, “between” may be used herein. Spatially relative terms such as "on" to describe the relationship of a component or feature to it. Another component or feature as shown in a figure. In addition to the orientation depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a "layer" is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terms "about", "approximately" and "approximately" generally mean ±20% of a stated value, or ±10% of a stated value, or ±5% of a stated value, or ±3% of a stated value , or within the range of ±2% of the specified value, or ±1% of the specified value, or ±0.5% of the specified value. The values specified in this invention are approximate. When not specifically described, stated values include the meanings of "about," "approximately," and "approximately." The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular terms "a", "an" and "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be understood that when a "component" or "layer" is referred to as being "on," "connected to," "coupled to" or "adjacent" another component or layer, it can be directly on the other component or layer Intermediate components or layers may be present on, connected to, coupled to, or adjacent thereto. In contrast, when a component is referred to as being "directly on," "directly connected to," "directly coupled to" or "immediately adjacent" another component or layer, there are no intervening components or layers present.

Note: (i) like features will be designated by the same reference numerals throughout the Figures and will not necessarily be described in detail in every Figure in which they appear, and (ii) a series of Figures may show a single item Each aspect is associated with various reference labels that may appear throughout the sequence, or may appear only in selected plots of the sequence.

Figure 1A is a cross-sectional view of a semiconductor package assembly 500A in accordance with some embodiments of the invention. 1B and 1C are perspective bottom views (plan views) of fan-out package 300A of semiconductor package assembly 500A of FIG. 1A illustrating the interface of semiconductor dies 102A and 132A and semiconductor die 132A, in accordance with some embodiments of the invention. Arrangement of through-hole (TV) interconnects 132TV1 and 132TV2. In some embodiments, semiconductor package 500A is a three-dimensional (3D) chiplet or chiplet package. Semiconductor package assembly 500A may include a wafer-level semiconductor package, such as fan-out package 300A including at least two vertically stacked semiconductor dies 102A and 132A and memory package 400 mounted on substrate 200 .

As shown in Figure 1A, the substrate 200, such as a printed circuit board (PCB), may be made of polypropylene (PP), prepreg (Pre-preg), FR-4 and/or other epoxy layers Pressed material is formed. It should also be noted that the substrate 200 may be a single-layer or multi-layer structure. A plurality of pads 202 and/or conductive traces (not shown) are provided on the substrate 200 . In one embodiment, the conductive traces may include signal trace segments and/or ground trace segments, and the conductive traces are used for input/output (I/O) connections of the fan-out package 300A. Furthermore, the fan-out package 300A mounts directly on the conductive traces. In some other embodiments, pads 202 are provided on substrate 200 and connected to different terminals of conductive traces. Pad 202 is for fan-out package 300A mounted directly on pad 202 .

As shown in FIG. 1A , the fan-out package 300A is mounted on the substrate 200 through a bonding process. Fan-out package 300A is mounted on substrate 200 using conductive structures 322 . The fan-out package 300A is a three-dimensional (3D) semiconductor package. The fan-out package 300A includes semiconductor dies 102A and 132A, redistribution layer (RDL) structures 316 and 366, molding compounds 312 and 362, and through-hole (TV) interconnects. Connection 314 and conductive structure 322. Conductive structure 322 is in contact with and electrically connected to RDL structure 316 . Additionally, conductive structure 322 is electrically connected to substrate 200 . In some embodiments, conductive structure 322 includes a conductive ball structure such as a copper ball, a conductive bump structure such as a copper bump or solder bump structure, or a conductive pillar structure such as a copper pillar structure.

In some embodiments, fan-out package 300A uses a chiplet (chiplet, or die) architecture to divide a large single semiconductor die into multiple smaller functional semiconductor dies fabricated in different technology nodes. pellets (called chiplets or core pellets). Each chiplet (or die) can have improved device performance and manufacturing yield. Additionally, fan-out package 300A may have reduced manufacturing costs. As shown in FIG. 1A , fan-out package 300A includes at least two semiconductor dies, such as semiconductor dies 102A and 132A (also referred to as chiplets 102A and 132A) stacked on each other along direction 120 (eg, vertical direction). . Semiconductor die 102A is disposed on RDL structure 366 and is disposed alongside memory package 400 in a direction 100 that is different from direction 120 (eg, a lateral direction). Semiconductor die 132A is disposed between RDL structures 316 and 366 and partially overlaps semiconductor die 102 and memory package 400 in direction 120 . Because semiconductor die 102A and semiconductor die 132A are respectively proximate to top surface 300TS and bottom surface 300BS of fan-out package 300A, semiconductor die 102A and semiconductor die 132A may also be referred to as top semiconductor die 102A and bottom semiconductor die 132A.

Semiconductor die 102A has an active surface 102as and a backside surface 102bs opposite the active surface 102as. Semiconductor die 132A has an active surface 132as and a backside surface 132bs opposite the active surface 132as. In some embodiments, semiconductor die 102A and semiconductor die 132A are fabricated through flip-chip technology. Semiconductor die 132A may be flipped to be disposed on RDL structure 316 opposite conductive structure 322 . Additionally, semiconductor die 132A may be flipped to be disposed on RDL structure 316 opposite conductive structure 322 . In some embodiments, semiconductor dies 102A and 132A each independently include a system-on-chip (SoC) die, a logic device, a memory device, a radio frequency (RF) device, etc., or any combination thereof. . For example, the first semiconductor die 102 and the second semiconductor die 132 may each independently include a micro control unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (power management integrated circuit, PMIC) chips, global positioning system (GPS) equipment, central processing unit (CPU) chips, graphics processing unit (GPU) chips, input and output (IO) chips such as dynamic Random access memory (dynamic random access memory, DRAM) IP core, static random access memory (static random-access memory, SRAM), high bandwidth memory (high bandwidth memory, HBM), etc. or any combination thereof. In some embodiments, semiconductor dies 102A and 132A have different functions.

In some embodiments, semiconductor die 132A also includes through-via (TV) interconnects 132TV1 and 132TV2 formed through semiconductor die 132A. Therefore, semiconductor die 132A may also be referred to as TV die 132A. TV interconnects 132TV1 and 132TV2 may be exposed from backside surface 132bs of semiconductor die 132A. Additionally, TV interconnects 132TV1 and 132TV2 have substantially vertical sidewalls and extend from the top surface of active surface 132as and backside surface 132bs of semiconductor die 132A, but the invention is not limited thereto. TV interconnects 132TV1 and 132TV2 in semiconductor die 132A may have other configurations and numbers. In some embodiments, TV interconnects 132TV1 and 132TV2 may be formed from a conductive material such as metal. For example, TV interconnects 132TV1 and 132TV2 may be formed from copper.

Semiconductor dies 102A and 132A may be manufactured in different technology nodes. In some embodiments, semiconductor die 102A has a first critical dimension (CD) and semiconductor die 132A has a second critical dimension that is different from the first CD to provide different functionality at reduced cost. That is, the first semiconductor die 102A and the second semiconductor die 132A have different wafer manufacturing nodes. For example, the first critical dimension is narrower than the second critical dimension. As an example and not a limitation, for example, the first critical dimension is 5 nm, and the second critical dimension is 7 nm; for example, the first critical dimension is 7 nm, and the second critical dimension is 12 nm; and so on. Therefore, the semiconductor dies 102A and 132A may be respectively arranged with various interfaces to meet the internal and external signal transmission requirements of the fan-out package 300A.

RDL structure 316 is disposed on active surface 132as of semiconductor die 132A. In other words, semiconductor die 132A is disposed on RDL structure 316 . Additionally, RDL structure 316 is disposed along direction 120 between semiconductor die 132A and substrate 200 . Pad 134 on active surface 132as of semiconductor die 132A is electrically connected to RDL structure 316 using conductive structure 142. In some embodiments, conductive structure 142 includes a conductive material, such as metal. The conductive structure 142 may include micro-bumps, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, etc. or combinations thereof. As shown in FIG. 1A , RDL structure 316 may include one or more conductive traces 320 and one or more vias 318 disposed in one or more dielectric layers 317 . In some embodiments, conductive traces 320 and vias 318 include conductive materials, such as metals including copper, gold, silver, or other suitable metals. The dielectric layer 317 may include an extra-low K (ELK) dielectric and/or an ultra-low K (ULK) dielectric. Additionally, dielectric layer 317 may include epoxy. Semiconductor die 132A is electrically connected to substrate 200 using vias 318 and conductive traces 320 of RDL structures 316 and corresponding conductive structures 322 . It should be noted that the number of through holes 318, the number of conductive lines 320, and the number of dielectric layers 317 shown in FIG. 1A are only examples and are not limitations of the present invention.

Through-hole (TV) interconnects 314 are provided on RDL structure 316 and beside semiconductor die 132A. As shown in FIG. 1A , TV interconnect 314 is electrically connected to via 318 and conductive trace 320 of RDL structure 316 . In some embodiments, TV interconnect 314 is electrically connected to semiconductor die 132A using vias 318 and conductive traces 320 within RDL structure 316 . TV interconnect 314 may be a through-hole connection structure through molding compound 312 for power and ground connections.

As shown in FIG. 1A , molding compound 312 is disposed on and in contact with RDL structure 316 . Molding compound 312 surrounds and contacts semiconductor die 132A and TV interconnects 314 . Additionally, TV interconnect 314 passes through molding compound 312 . The backside surface 132bs of the second semiconductor die 132A may be exposed from the molding compound 312 . In some embodiments, molding compound 312 may be formed from a non-conductive material, such as epoxy, epoxy, epoxy, etc. Resins, moldable polymers, etc. Molding compound 312 may be applied while substantially liquid and may then be cured by a chemical reaction, such as in an epoxy or resin. In some other embodiments, the molding compound 312 may be an ultraviolet (UV) or thermoset polymer applied as a gel or malleable solid that can be disposed around the semiconductor die 132A, and the UV or heat may then be used. Curing process to cure. Molding compound 312 can be cured using a mold.

RDL structure 366 is disposed on active surface 102as of semiconductor die 102A. Additionally, RDL structure 366 is disposed along direction 120 between active surface 102as of semiconductor die 102A and backside surface 132bs of second semiconductor die 132A and is electrically connected to TV interconnect 314 . As shown in FIG. 1A , semiconductor die 132A is separated from memory package 400 by RDL structure 366 . Molding compound 312 fills the space between RDL structures 316 and 366 (not shown) and abuts the sidewalls of semiconductor die 132A and adjacent surfaces of RDL structures 316 and 366 . RDL structures 316 and 366 respectively contact opposite ends of TV interconnect 314. In other words, semiconductor die 132A and TV interconnect 314 are sandwiched between RDL structures 316 and 366 . Pad 104 on active surface 102as of semiconductor die 102A is electrically connected to RDL structure 366 using conductive structure 112 . In embodiments, conductive structures 112 and 142 may include the same or similar materials and structures. In some embodiments, RDL structure 366 is electrically connected to semiconductor die 132A through TV interconnects 132TV1 and 132TV2, TV interconnect 314, and RDL structure 316. Because RDL structure 366 and RDL structure 316 are respectively proximate to the top surface 300TS and bottom surface 300BS of the fan-out package 300A, the RDL structure 366 and the RDL structure 316 may also be referred to as the top RDL structure 366 and the bottom RDL structure 316.

In some embodiments, RDL structure 366 includes one or more conductive traces 370 and one or more vias 368 disposed in one or more dielectric layers 367 . In some embodiments, the material of conductive traces 370 may be similar to the material of conductive traces 320 . The material of via 368 may be similar to the material of via 318 . Additionally, the material of dielectric layer 367 may be similar to the material of dielectric layer 317 . It should be noted that the number of vias 368, the number of conductive traces 370, and the number of dielectric layers 367 shown in FIG. 1A are only examples and are not limitations of the present invention.

As shown in Figure 1A, memory package 400 is disposed on RDL structure 366 through a bonding process. In some embodiments, memory package 400 includes a dynamic random access memory (DRAM) package or another suitable memory package. In some embodiments, memory package 400 includes substrate 418, at least one semiconductor die (eg, two semiconductor dies 402 and 404 stacked on substrate 418), and conductive structure 422. In some embodiments, each of semiconductor dies 402 and 404 includes a dynamic random access memory (DRAM) die (eg, a double data rate 4 (DDR4) DRAM die, Low-power DDR4 (LPDDR4) DRAM die, double data rate (DDR) synchronous dynamic random access memory (SDRAM) die, etc.) or another suitable memory grains. In some other embodiments, semiconductor dies 402 and 404 may include the same or different devices. In some embodiments, top package 400 also includes one or more passive components (not shown), such as resistors, capacitors, inductors, etc., or combinations thereof.

In this embodiment, as shown in FIG. 1A , two semiconductor dies 402 and 404 are mounted on a substrate 418 with a paste (not shown). Semiconductor dies 402 and 404 have corresponding pads 408 and 410 respectively. Pads 408 and 410 of semiconductor dies 402 and 404 may be electrically connected to substrate 418 using bonding wires 414 and 416, respectively. However, the number of stacked memory dies is not limited to the disclosed embodiments. Alternatively, semiconductor dies 402 and 404 as shown in FIG. 1A may be arranged side by side and mounted on substrate 418 with a paste (not shown). Alternatively, semiconductor dies 402 and 404 may be fabricated via flip chip technology and electrically connected to substrate 418 without the use of bonding wires 414 and 416.

As shown in FIG. 1A , substrate 418 may include circuitry 428 disposed in one or more ultra-low K (ELK) and/or ultra-low K (ULK) dielectric layers (not shown) and contact pads 420 and 430 . Contact pad 420 is disposed on top of circuit 428, near the top surface (die attachment surface) of substrate 418. Additionally, bond wires 414 and 416 are electrically connected to corresponding contact pads 420 . Pad 430 is disposed on the bottom of circuit 428 near the bottom surface (bump attachment surface) of substrate 418 . Contact pads 430 are electrically connected to corresponding contact pads 420 . In some embodiments, bonding wires 414 and 416, contact pads 420 and 430, and circuitry 428 include conductive materials, such as metals including copper, gold, silver, or other suitable metals.

As shown in FIG. 1A , conductive structure 422 is disposed on the bottom surface of substrate 418 opposite semiconductor dies 402 and 404 . Conductive structures 422 are electrically connected (or in contact) with corresponding contact pads 430 and RDL structures 366 of substrate 418 . In some embodiments, conductive structure 422 includes a conductive ball structure such as a copper ball, a conductive bump structure such as a copper bump or solder bump structure, or a conductive pillar structure such as a copper pillar structure.

In some embodiments, as shown in FIG. 1A , molding compound 412 covers substrate 418 to encapsulate semiconductor dies 402 and 404 and bonding wires 414 and 416. The top surface of molding compound 412 may serve as top surface 400T of memory package 400 . In some embodiments, molding compounds 312 and 412 may include the same or similar materials and manufacturing processes.

As shown in FIG. 1A , molding compound 362 covers RDL structure 366 , semiconductor die 102A, and memory package 400 . Molding compound 362 surrounds semiconductor die 102A and memory package 400 . Molding compound 362 is in contact with the backside surface 102bs and sidewalls (not shown) of semiconductor die 102A and the top surface 400TS and sidewalls (not shown) of memory package 400 . Additionally, the top surface of the molding compound 362 forms the top surface 300TS of the fan-out package 300A of the semiconductor package assembly 500A. Additionally, top surface 400TS of memory package 400 is adjacent to top surface 300TS of semiconductor package assembly 500A. In some embodiments, molding compounds 312, 362, and 412 may include the same or similar materials and manufacturing processes. In some embodiments, edge 312E of molding compound 312 is flush with corresponding edge 316E of RDL structure 316 and corresponding edge 366E of RDL structure 366 . Edges 362E of molding compound 362 are flush with corresponding edges 366E of RDL structure 366 . Thus, edges 312 of molding compound 312 , edges 362E of molding compound 362 , edges 316E of RDL structures 316 , and edges 366E of RDL structures 366 may collectively serve as package edges for fan-out package 300A.

As shown in FIG. 1A , fan-out package 300A may also include filling a gap (not shown) between RDL structure 316 and semiconductor die 132A, a gap (not shown) between RDL structure 336 and semiconductor die 102A. ), and the gap (not shown) between RDL structure 336 and memory package 400. In some embodiments, underfill surrounds and contacts portions of conductive structures 112 , 142 , and 422 . RDL structures 316 and 336 to further reduce thermal resistance from semiconductor die 132A to RDL structure 316 and from semiconductor die 102A and memory package 400 to RDL structure 366. Additionally, underfill may be provided to compensate for different coefficients of thermal expansion (CTE) between semiconductor dies 102A and 132A, RDL structures 316 and 366, and conductive structures 112, 142, and 422. In some embodiments, the underfill includes capillary underfill (CUF), molded underfill (MUF), or a combination thereof.

Because the semiconductor die 102A and the memory package 400 are side-by-side on the top RDL structure 366 of the fan-out package 300A, the thickness 362T of the molding compound 362 (from the top surface 300TS of the fan-out package 300A to between the molding compound 362 and the top RDL structure 366 (thickness at the interface) may depend primarily on the thickness 400T of the memory package 400. Accordingly, the thickness 102T of the semiconductor die 102A may be increased to the same or similar thickness 400T of the memory package 400 to improve thermal performance (e.g., a thicker thickness of the semiconductor die 102A formed primarily of silicon may improve heat dissipation capabilities, and The coefficient of thermal expansion (CTE) mismatch between the semiconductor die 102A and different materials in the semiconductor package assembly 500A may be improved). In one embodiment, the thickness of the semiconductor die 102A is greater than the thickness of the semiconductor die 132A, thereby improving the thermal performance of the semiconductor die 102A and increasing the heat storage capacity of the semiconductor die 102A, thereby making it difficult for the semiconductor die 102A to reach A higher temperature is used to prevent the semiconductor die 102A from quickly reducing its performance due to temperature rise, and to ensure that the semiconductor die 102A can be in a high-performance operating state for a longer period of time.

As shown in FIG. 1A , fan-out package 300A also includes electronic components 330 mounted on RDL structure 316 opposite semiconductor die 132A. In some embodiments, electronic component 330 has pad 332 on electronic component 330 and pad 332 is electrically connected to conductive trace 320 of RDL structure 316 . In some embodiments, electronic components 330 are disposed between conductive structure(s) 322 . The electronic component 330 may not be covered by the molding compound. In some embodiments, electronic component 330 includes an integrated passive device (IPD), which includes capacitors, inductors, resistors, or combinations thereof. In some embodiments, electronic component 330 includes DRAM dies.

As shown in FIGS. 1A-1C , semiconductor die 102A and semiconductor die 132A in fan-out package 300A of semiconductor package assembly 500A may include interfaces at the edges of semiconductor dies 102A and 132A. In some embodiments, the interfaces of fan-out package 300A as used herein may include circuitry and input/output connections disposed on active surface 102as of semiconductor die 102A and active surface 132as of semiconductor die 132A (e.g., Pads 104 and 134). In some embodiments, the interfaces of semiconductor dies 102A and 132A are used between different semiconductor dies 102A and 132A, between semiconductor die 102A and memory package 400, and between semiconductor die 132A and memory package 400. signal (data) and power transmission and ground paths. It should be noted that FIGS. 1B and 1C only show the semiconductor dies 102A and 132A, the molding material 312/362 and the conductive structure 422 of the memory package 400 for illustration, and the remaining features can be shown in the cross-sectional schematic diagram of FIG. 1A . It should be understood that, although some features are shown in some embodiments but not in other embodiments, wherever possible these features may (or may not) be present in other embodiments. For example, although each illustrated embodiment shows a specific arrangement of the interfaces of semiconductor dies 102A and 132A and the conductive structures 422 of memory package 400, any other combination of arrangements of the interfaces of semiconductor dies 102A and 132A and as long as Where applicable, conductive structures 422 of memory package 400 may also be used.

As shown in FIG. 1B , semiconductor dies 102A and 132A may have a rectangular plan view shape. Semiconductor die 102A may have opposing edges 102E1 and 102E3 extending substantially along direction 110 and opposing edges 102E2 and 102E4 extending substantially along direction 100 . Semiconductor die 132A may have opposing edges 132E1 and 132E3 extending substantially along direction 110 and edges 132E4 and 132E4 extending substantially along direction 100 . Edge 102E1 of semiconductor die 102A is close to edge 132E3 of semiconductor die 132A. Edge 102E2 of semiconductor die 102A connected between (or adjacent to) edges 102E1 and 102E3 is adjacent to (or immediately adjacent to) edge 132E2 of semiconductor die 132A connected between edges 132E1 and 132E3. Edge 102E4 of semiconductor die 102A connected between (or adjacent to) edges 102E1 and 102E3 is adjacent to (or immediately adjacent to) edge 132E4 of semiconductor die 132A connected between edges 132E1 and 132E3. Edge 102E3 of semiconductor die 102A connected between edges 102E2 and 102E4 is away from edge 132E1 of semiconductor die 132A connected between edges 132E2 and 132E4.

In some embodiments, the top semiconductor die may be used to control the memory package and include various interfaces for electrical connection to the bottom semiconductor die and the memory package inside the fan-out package. The bottom semiconductor die fabricated with TV interconnects may only include interfaces for electrical connection to the top semiconductor die of the fan-out package. For example, semiconductor die (top semiconductor die) 102A may include interfaces 102DDR (including interfaces 102DDR-1, 102DDR-2, 102DDR-3, 102DDR-4) extending along direction 110, for example at least one of which is the first semiconductor The third interface of the die) and 102DTD are arranged side by side along the 100 direction. The interface 102DDR is disposed close to the edge 102E1 of the memory package 400 . Interface 102DTD (eg, the first interface of the first semiconductor die) is disposed adjacent interface 102DDR and relative to edge 102E1 such that interface 102DDR is disposed in direction 100 between interface 102DTD and memory package 400 . Additionally, semiconductor die (bottom semiconductor die) 132A with TV interconnects 132TV1 and 132TV2 may include a single interface 132DTD disposed on edge 132E3 and overlapping interface 102DTD along direction 120 (eg, a second interface 102DTD of a second semiconductor die). interface). When the semiconductor die 102A is a SOC die, the memory package 400 is a double data rate 4 (DDR4) DRAM package, and the interfaces 102DDR-1, 102DDR-2, 102DDR-3, 102DDR-4 can be used to control the memory package 400 A Double Data Rate 4 (DDR4) interface (eg, transferring data to/from a memory controller in semiconductor die 102A). In some embodiments, interfaces 102DDR-1, 102DDR-2, 102DDR-3, 102DDR-4 are electrically connected to memory package 400 through RDL structure 366 rather than RDL structure 316. In addition, the interface 102DTD of the semiconductor die 102A and the interface 132DTD of the semiconductor die 132A may be die to die (die to die, DTD) interfaces, including two different semiconductor die 102A and 132A for data transmission. Any suitable direct conductive electrical coupling. In some embodiments, TV interconnect 132TV1 is disposed within interface 132DTD disposed on semiconductor die 132A and is electrically connected to interfaces 102DDR-1, 102DDR-2, 102DDR-3, 102DDR-4 through RDL structure 366 Interface 102DTD disposed on semiconductor die 102A. In some embodiments, TV interconnect 132TV2 may be disposed within other interfaces (not shown) of semiconductor die 132A that overlap interface 102DDR of semiconductor die 102A. TV interconnect 132 TV2 is electrically connected to interface 102DDR of semiconductor die 102A through RDL structure 366 to provide additional power (power) transfer and ground paths from interface 102DDR to base (substrate) 200 .

In some embodiments, the conductive structures 422 of a memory package 400 (eg, a DDR4 DRAM package) are arranged according to a given arrangement. For example, the conductive structures 422 of the memory package 400 are arranged into two groups 422G1 and 422G2 (including single or multiple columns of conductive structures 422) along the direction 100, as shown in FIG. 1B. Each group 422G1 and 422G2 of conductive structures 422 may provide two data channels for conductive structures 422 . To reduce the length of wiring paths between top package 400 and bottom package 300 , interfaces 102DDR-1 , 102DDR-2 , 102DDR-3 , 102DDR-4 of semiconductor die 102A may correspond to the arrangement of conductive structures 422 of memory package 400 to decorate. Since the semiconductor die 102A and the memory package 400 including the interface 102DDR are in a side-by-side arrangement without any RDL structures interposed therebetween, the interfaces 102DDR-1, 102DDR-2 of the semiconductor die 102A may be arranged close to the group 422G1 of the conductive structures 422. Interfaces 102DDR-3 and 102DDR-4 of semiconductor die 102A may be arranged proximate group 422G2 of conductive structures 422, as shown in Figure IB. In one embodiment, in plan view, TV interconnect 132TV1 and TV interconnect 132TV2 are located between edge 102E1 of semiconductor die 102A and edge 132E3 of semiconductor die 132A, thereby allowing semiconductor dies 102A to be connected in a shorter path (electrical connection, communication connection) to the semiconductor die 132A, and a shorter path connects the semiconductor die 102A, the semiconductor die 132A and the memory package 400 .

Based on the arrangement of interfaces 102DDR and 102DTD of semiconductor die 102A and interface 132DTD and TV interconnects 132TV1 and 132TV2 of semiconductor die 132A, memory package 400 passes through conductive structure 422, interface 102DDR and RDL structure 366 instead of TV interconnects 314 and RDL Structure 316 is electrically connected to semiconductor die 102A for signal transmission. Additionally, interfaces 102DTD and 132DTD are electrically connected to substrate 200 through conductive structure 422, interface 102DDR, RDL structures 316 and 366, and TV interconnect 132TV2 for power (power) transmission and grounding. RDL structure 366 is electrically connected to interfaces 102DDR, 102DTD and 132DTD and TV interconnects 132TV1 and 132TV2. Therefore, memory package 400 may be electrically connected to semiconductor die 132A through conductive structure 422, interfaces 102DDR, 102DTD, and 132DTD, RDL structure 366, and TV interconnect 132TV1 instead of TV interconnect 314 and RDL structure 316. In the embodiment of FIG. 1B , interfaces 102DDR-1, 102DDR-2, 102DDR-3, 102DDR-4 (eg, at least one thereof) of semiconductor die 102A may be electrically connected to memory package 400 (or semiconductor die 402 ,404). In one embodiment, connection to memory package 400 (or semiconductor die 402, 404) may be through input/output connections (eg, pads) located within interfaces 102DDR-1, 102DDR-2, 102DDR-3, 102DDR-4 . In one embodiment, the interfaces 102DDR-1, 102DDR-2, 102DDR-3, 102DDR-4 are located closest to the edge of the memory package 400 (edge 102E1), and thus can be routed from the semiconductor die in a more direct and shorter path. 102A electrical connection (communication connection) to the memory package 400 (or semiconductor die 402, 404), thereby minimizing trace lengths between different components, providing better electrical performance, faster signal propagation, and Reduce noise and crosstalk defects and increase channel design flexibility for semiconductor package components.

In some embodiments, interface 102DDR may be disposed on three adjacent edges of semiconductor die 102A. As shown in FIG. 1C , which shows another implementation of the embodiment of the present invention, the interface 102DDR-1' of the semiconductor die 102A may be arranged on the edge 102E4 connected to the edges 102E1 and 102E3 and opposite to the edge 102E2. . Additionally, interface 102DDR-4' of semiconductor die 102A may be disposed on edge 102E2 connected to edges 102E1 and 102E3 and opposite edge 102E4. In some embodiments, for example, at least one of interface 102DDR-2 and interface 102DDR-3 of semiconductor die 102A may be a third interface of semiconductor die 102A. In some embodiments, for example, at least one of interface 102DDR-1' and interface 102DDR-4' of semiconductor die 102A may be a fourth interface of semiconductor die 102A. Memory package 400 is electrically connected to semiconductor die 102A through interfaces 102DDR-1', 102DDR-2, 102DDR-3, and 102DDR-4'. Depending on the arrangement of interfaces 102DDR-1' and 102DDR-4', the flexibility of the layout design (including interface and/or wiring design) of the semiconductor die 102A for the channel arrangement of the memory package 400 can be increased. In one embodiment of the present invention, the semiconductor die 102A can be electrically connected to the memory package 400 (or the semiconductor die 402, 404) through the interface 102DDR-2 and/or the interface 102DDR-3 (and the RDL structure 366), and also The memory package 400 (or the semiconductor die 402, 404) may be electrically connected through the interface 102DDR-1' and/or the interface 102DDR-4' (and the RDL structure 366), so the semiconductor die 102A is connected to the memory package 400 (or The arrangement of the connection paths or connection channels between the semiconductor dies 402, 404) is more flexible and diverse, and has wider versatility. In one embodiment, connections to the memory package 400 (or semiconductor die) may be made through input/output connections (eg, pads) located within interfaces 102DDR-2, 102DDR-3, 102DDR-1', 102DDR-4'. Granules 402, 404).

In some embodiments, the bottom semiconductor die fabricated with TV interconnects may include various interfaces for electrical connection to the top semiconductor die and the memory package inside the fan-out package. The top semiconductor die may only include interfaces for electrical connection with the top semiconductor die of the fan-out package. Thus, the top semiconductor die can control the memory package through the bottom semiconductor die, or the bottom semiconductor die can be used to control the memory package. Figure 2A is a cross-sectional view of a semiconductor package assembly 500B in accordance with some embodiments of the invention. Figures 2B, 2C, and 2D are perspective bottom views (plan views) of fan-out package 300B of semiconductor package assembly 500B of Figure 2A, Figure 1 illustrating the interfaces of semiconductor dies 102B and 132B, in accordance with some embodiments of the present invention. and the arrangement of via (TV) interconnects 132TV1 and 132TV3 of semiconductor die 132B. For the sake of brevity, elements that are the same or similar to those previously described with reference to FIGS. 1A-1C are not repeated in the following embodiments.

As shown in Figures 2A and 2B, fan-out package 300B may include one or more semiconductor dies 102B. For example, fan-out package 300B may include semiconductor dies 102B-1 and 102B-2, each semiconductor die including only one type of interface, such as interface 102DTD. Semiconductor die 102B-1 (or semiconductor die 102B-2) and memory package 400 are arranged side by side along direction 100. Semiconductor dies 102B-1 and 102B-2 and memory package 400 are stacked along a direction 120 different from direction 100 including various interfaces 132DDR (including interfaces 132DDR-1, 132DDR-2, 132DDR-3 and 132DDR-3 shown in FIG. 2B 132DDR-4) and 132DTD and TV interconnects 132TV1 and 132TV3 on the semiconductor die 132B. In other words, semiconductor die 132B is disposed along direction 120 beside semiconductor dies 102B- 1 and 102B- 2 and memory package 400 . In some embodiments, interface 132DDR is disposed on edge 132E1 of semiconductor die 132B and overlaps memory package 400 along direction 120 . Memory package 400 is electrically connected to semiconductor die 132B through interface 132 DDR and RDL structures 366 . Interface 132DTD is disposed on edge 132E3 opposite edge 132E1 of semiconductor die 132B. Additionally, interfaces 132DTD are arranged to overlap corresponding interfaces 102DTD of semiconductor dies 102B- 1 and 102B- 2 in direction 120 .

As shown in FIGS. 2A and 2B , TV interconnect 132TV1 of semiconductor die 132B is disposed within interface 132DTD and is electrically connected to interface 102DTD of semiconductor die 102B-1 and 102B-2. Additionally, semiconductor die 132B may also include TV interconnect 132TV3 disposed within interface 132DDR and electrically connected to memory package 400 . In some embodiments, TV interconnects 132TV1, 132TV2 (FIG. 1A), and 132TV3 may include the same or similar materials and structures.

Since semiconductor die 132B including interface 132DDR and memory package 400 are in an overlapping arrangement with RDL structure 366 interposed therebetween, interfaces 132DDR-1 and 132DDR-2 of semiconductor die 132B may be arranged in a group with conductive structure 422 422G1 overlap. Additionally, interfaces 132DDR-3 and 132DDR-4 of semiconductor die 132B may be arranged to overlap group 422G2 of conductive structures 422, as shown in FIG. 2B.

Based on the arrangement of interface 132DDR and TV interconnect 132TV3 of semiconductor die 132B, memory package 400 is electrically connected to semiconductor die 132B using a shorter routing path for data transmission. Additionally, TV interconnect 132TV3 within interface 132DDR may be electrically connected to conductive structure 322 through conductive structure 142 for power transmission and grounding without passing through other interfaces on semiconductor die 132B.

In some embodiments, interface 132DDR may be disposed on three adjacent edges of semiconductor die 132B. As shown in Figure 2C, interface 132DDR-1' of semiconductor die 132B may be disposed on edge 132E4 connected to edges 132E1 and 132E3 and opposite edge 132E2. Additionally, interface 132DDR-4' of semiconductor die 132B may be disposed on edge 132E2 connected to edges 132E1 and 132E3 and opposite edge 132E4. Memory package 400 is electrically connected to semiconductor die 132B through interfaces 132DDR-1', 132DDR-2, 132DDR-3, and 132DDR-4'. Depending on the arrangement of interfaces 132DDR-1' and 132DDR-4', flexibility in layout design (including interface and/or wiring design) of semiconductor die 132B for channel arrangement of memory package 400 may be increased.

In some embodiments, the orientation and shape of the distribution areas of TV interconnects 132TV3 within the interface 132DDR of the semiconductor die 132B and the sequence of pin assignments may be the same or similar as those of the conductive structures 422 of the semiconductor die 132B overlapping the interface 132DDR. , to shorten the routing path of data transmission (between the interface 132DDR and the conductive structure 422). In the plan view shown in FIG. 2D, TV interconnect 132TV3 disposed within interfaces 132DDR-1, 132DDR-2, 132DDR-3 and 132DDR-4 may have distribution areas 132DDR-1A, 132DDR-2A, 132DDR-3A and 132DDR-4A. Conductive structures 422 arranged in the two data channels of group 422G1 may have distribution areas 422C1A and 422C2A. Additionally, the conductive structures 422 disposed in the two data channels of group 422G2 may have distribution areas 422C3A and 422C4A. In some embodiments, distribution areas 132DDR-1A, 132DDR-2A, 132DDR-3A, and 132DDR-4A of TV interconnect 132TV3 correspond to and at least partially overlap distribution areas 422C1A, 422C2A, 422C3A, and 422C4A of conductive structure 422.

In some embodiments, the ground TV interconnects and signal TV interconnects within the DDR interface may have a staggered arrangement. Each ground TV interconnect is inserted between two adjacent signal TV interconnects in order to reduce crosstalk noise from adjacent signal TV interconnects. 2E is an enlarged plan view of semiconductor die 132B of fan-out package 500B of semiconductor package assembly 500B of FIG. 2A illustrating interface 132DDR-1 of semiconductor die (bottom semiconductor die) 132B, in accordance with some embodiments of the invention. , arrangement of TV interconnections within 132DDR-2, 132DDR-3 and 132DDR-4. For the sake of brevity, elements in the following embodiments that are the same or similar to those previously described with reference to FIGS. 1A-1C and 2A-2D will not be repeated. It is worth noting that Figure 2E only shows the ground TV interconnect 132TVG and the signal TV interconnect 132TVS within interfaces 132DDR-1, 132DDR-2, 132DDR-3 and 132DDR-4 for illustration, the power TV interconnect is hidden in Pictured. As shown in Figure 2E, TV interconnects within interfaces 132DDR-1, 132DDR-2, 132DDR-3, and 132DDR-4 (such as TV interconnect TV3 shown in Figures 2A-2B) may include signal TV interconnect 132TVS and ground TV Interconnect 132TVG. The signal TV interconnection 132TVS and the ground TV interconnection 132TVG are arranged in multiple columns, for example in two columns C1 and C2. In some embodiments, ground TV interconnect 132TVG is designed to be arranged only in column C1. Signal TV interconnections 132TVS are arranged in columns C1 and C2. In some embodiments, signal TV interconnect 132TVS in column C1 is designed to be interleaved with ground TV interconnect 132TVG. Additionally, the signal TV interconnect in column C2 is designed to be adjacent to the ground TV interconnect 132TVG in column C1. Using the method of Figure 2E, in column C2, the signal TV interconnections 132TVS and the ground TV interconnections 132TVG are arranged at intervals from each other, which can reduce crosstalk between the signal TV interconnections 132TVS. In column C1, the signal TV interconnections 132TVS are arranged at larger intervals (for example, adjacent signal TV interconnections 132TVS are separated by a distance of at least one signal TV interconnection 132TVS/ground TV interconnection 132TVG), which can reduce the signal Crosstalk between TV interconnection 132TVS.

In some embodiments, the bottom semiconductor die may also include additional interfaces (also referred to as digital input/output (I/O) interfaces) to transmit digital input/output (I/O) signals to control connections to the base (substrate ) other external integrated circuits (ICs). The digital I/O interface may be positioned adjacent the DDR4 interface and close to the edge of the bottom semiconductor die to facilitate utilization of the conductive structures between the DDR4 interface and the corresponding package edge of the fan-out package. Figure 3A is a cross-sectional view of a semiconductor package assembly 500C in accordance with some embodiments of the invention. 3B is a perspective plan view (bottom view) of the fan-out package 300C of the semiconductor package assembly 500C of FIG. 3A illustrating interfaces 132IO of the semiconductor die 132C and in addition to interfaces 132DDR-1, 132DDR-, in accordance with some embodiments of the present invention. 2. Arrangement of conductive structures 322 other than 132DDR-3 and 132DDR-4 and 132DTD. Note that for purposes of illustration, Figure 3B only shows TV interconnect 132TV1 within interfaces 132DTD and 132DTD and TV interconnect 132TV3 within interfaces 132DDR-1, 132DDR-2, 132DDR-3 and 132DDR-4, 102B 400 and 422 hidden in Pictured. For the sake of brevity, elements in the following embodiments that are the same or similar to those previously described with reference to FIGS. 1A-1C and 2A-2E will not be repeated.

As shown in FIGS. 3A and 3B , the difference between the semiconductor package assembly 500B and the semiconductor package assembly 500C is that the semiconductor die 132C of the fan-out package 300C of the semiconductor package assembly 500C may also include an interface 132IO to transmit digital input/output. (I/O) signals to control other external ICs (not shown) connected to base 200. Interface 132IO may be arranged adjacent to interfaces 132DDR-1, 132DDR-2, 132DDR-3, and 132DDR-4 and closer to edge 132E1 than interfaces 132DDR-1, 132DDR-2, 132DDR-3, and 132DDR-4. In other words, interfaces 132DDR-1, 132DDR-2, 132DDR-3, and 132DDR-4 are arranged close to edge 132E1 and between interface 132DTD and interface 132IO along direction 100. In some embodiments, interface 132I0 is electrically connected to conductive structure 322 in region 380 outside edge 132E1 along direction 100 through RDL structure 316 rather than RDL structure 366, as shown in FIG. 3B . Additionally, region 380 is located between edge 132E1 and a corresponding edge 316E of RDL structure 316 (also referred to as package edge 316E of semiconductor package assembly 500C). Therefore, the utilization of the conductive structures 322 outside the interfaces 132DDR-1, 132DDR-2, 132DDR-3 and 132DDR-4 is improved. Using the method of the embodiment of the present invention, the interfaces 132DDR-1, 132DDR-2, 132DDR-3 and 132DDR-4 can be arranged adjacent to the interface 132IO, and the interface 132IO is relatively closer to the edge 132E1, which can make the wiring layout more reasonable. , more practical. In addition, in one embodiment, the arrangement of the interface 132IO can also be applied to the embodiments of FIGS. 1A to 1C. For example, the interface 132IO may be arranged close to the edge 132E1 (Figs. 1B, 1C).

In some embodiments, the bottom semiconductor die may also include embedded trench capacitors, such as deep trench capacitors (DTCs), to provide memory package 400 with higher capacitance (value) than traditional on-die capacitors. ). Figure 4 is a cross-sectional view of a semiconductor package assembly 500D in accordance with some embodiments of the invention. Figure 5 is a cross-sectional view of a semiconductor package assembly 500E in accordance with some embodiments of the invention. 6 is an enlarged cross-sectional view of a semiconductor package assembly 500D or 500E showing a trench capacitor 132DTC embedded in a semiconductor die 132D or 132E of a semiconductor fan-out package 300D or 300E, in accordance with some embodiments of the present invention. Referring to package assembly 500D or 500E of Figures 4 and 5. For the sake of brevity, elements that are the same or similar to those previously described with reference to FIGS. 1A-1C, 2A-2E, and 3A-3B will not be repeated in the following embodiments.

As shown in FIG. 4 , the difference between the semiconductor die 132A of the semiconductor package assembly 500A and the semiconductor die 132D of the semiconductor package assembly 500D is that the semiconductor die 132D includes a trench capacitor 132DTC embedded in the semiconductor die 132D. In some embodiments, trench capacitor 132DTC is disposed within a region of semiconductor die 132D that overlaps interface 102DDR of semiconductor die 102A. Additionally, trench capacitor 132DTC may be disposed adjacent TV interconnect 132TV2. In some embodiments, trench capacitor 132DTC may be electrically connected through interfaces 102DDR-1, 102DDR-2, 102DDR-3, and 102DDR-4 of RDL structure (top RDL structure) 366 and semiconductor die (top semiconductor die) 102A to memory package 400.

As shown in FIG. 5 , the difference between the semiconductor die 132B of the semiconductor package assembly 500B and the semiconductor die 132E of the semiconductor package assembly 500E is that the semiconductor die 132E includes a trench capacitor 132DTC embedded in the semiconductor die 132E. In some embodiments, trench capacitor 132DTC is disposed within at least one of interfaces 132DDR-1, 132DDR-2, 132DDR-3, and 132DDR-4 and is electrically connected to memory package 400 through RDL structure 366. Additionally, trench capacitor 132DTC may be disposed adjacent TV interconnect 132TV3.

As shown in FIG. 6 , trench capacitor 132DTC may be formed from silicon substrate 132S of semiconductor die 132D (or semiconductor die 132E) and formed by a semiconductor process (eg, a semiconductor wafer manufacturing process). Trench capacitor 132DTC may be formed in a trench (not shown) in doped region 132DR of silicon substrate 132S and separated from silicon substrate 132S by dielectric layer DTC-1D for isolation. In addition, the conductivity of the doped region 132DR may be different from the conductivity of the doped region 132DR. In some embodiments, trench capacitor 132DTC may include first electrode DTC-1E, dielectric layer DTC-2D, second electrode DTC-2E, first electrode contact DTC-1C, and second electrode contact DTC-2C. The first electrode DTC-1E and the second electrode DTC-2E formed of doped silicon, polysilicon or conductive material are conformally formed in the trench. In addition, the dielectric layer DTC-2D is sandwiched between the first electrode DTC-1E and the second electrode DTC-2E. The first electrode contact DTC-1C is provided on the first electrode DTC-1E and is electrically connected to the first electrode DTC-1E. The second electrode contact DTC-2C is provided on the second electrode DTC-2E and is electrically connected to the second electrode DTC-2E. In some embodiments, second electrode contact DTC-2C may also be electrically connected to doped region 132DR to increase capacitance. In some embodiments, first electrode contact DTC-1C and second electrode contact DTC-2C may be part of RDL structure 366 and consist of conductive traces 370 and vias 368 (as shown in Figures 4 and 5).

One embodiment of the present invention provides a semiconductor package assembly that includes a fan-out package that includes a top semiconductor die (eg, SoC die), a bottom semiconductor die, and a bottom semiconductor die that are stacked on each other and mounted on a substrate. Die and memory packaging. The top semiconductor die and memory package are arranged side by side along the lateral direction (eg, direction 100), and both are stacked along the vertical direction (eg, direction 120) on the bottom semiconductor die with through-via (TV) interconnects . Therefore, the top semiconductor die may be fabricated to a thicker thickness (eg, the thickness of the top semiconductor die may be similar to the thickness of the memory package) to improve thermal performance. In some embodiments, the top semiconductor die includes a first interface (eg, a die-to-die (DTD) interface) that overlaps and is electrically connected to a second interface (eg, a DTD interface) disposed on the bottom semiconductor die. and a third interface for controlling memory packaging (such as a DDR4 interface). The third interface is disposed adjacent the first interface and on one or more adjacent edges proximate the top semiconductor die of the memory package. The third interface is electrically connected vertically to the memory package through the top RDL structure between the top semiconductor die and the bottom semiconductor die for signal transmission. Additionally, the third interface of the top semiconductor die may be electrically connected to the substrate through TV interconnects through the other interfaces of the bottom semiconductor die for power transmission and grounding. In some embodiments, a third interface for controlling the memory package is disposed on the bottom semiconductor die. Accordingly, the third interface of the bottom semiconductor die may overlap the memory package in a vertical direction. Additionally, the third interface of the bottom semiconductor die may include a TV interconnect disposed therein for data and power transmission and grounding. Therefore, the length of the wiring path between the third interface of the bottom semiconductor die memory package and the size of the semiconductor package assembly can be further reduced. In some embodiments, the ground and signal TV interconnections within the third interface may have a staggered arrangement. Each ground TV interconnect can act as a shield between two adjacent signal TV interconnects so that signal integrity issues such as crosstalk noise and delay uncertainty can be improved. In some embodiments, the orientation and shape of the distribution areas within the third interface of the bottom semiconductor die and the sequence of pin assignments for the TV interconnects may be the same or similar to the orientation and shape of the overlapping conductive structures of the memory package to shorten Wiring path for data transmission (between the third interface and the conductive structure of the memory package). In some embodiments, the bottom semiconductor die may also include an additional digital input/output (I/O) interface adjacent the third interface to transmit digital input/output (I/O) signals to control other external devices through the substrate. IC. In this way, the utilization rate of the conductive structure of the fan-out package in areas other than the third interface can be further improved. In some embodiments, the bottom semiconductor die may also include trench capacitors to provide the memory package with higher capacitance than traditional on-die capacitors.

While the invention has been described by way of example and in accordance with preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as will be apparent to those skilled in the art. Therefore, the scope of the appended claims is to be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims (36)

1. A semiconductor packaging component, characterized in that it includes: A first semiconductor die and a second semiconductor die stacked on each other, wherein the first semiconductor die includes a first interface that overlaps and electrically connects a second interface disposed on the second semiconductor die. a second interface; and a third interface arranged on the first edge of the first semiconductor die; and A memory package is located next to the first semiconductor die, wherein the memory package is electrically connected to the first semiconductor die through the third interface. 2. The semiconductor package assembly of claim 1, wherein the first semiconductor die has a first critical dimension and the second semiconductor die has a second critical dimension, wherein the first critical dimension Narrower than the second critical dimension. 3. The semiconductor package assembly of claim 1, wherein the first semiconductor die includes a fourth semiconductor die disposed on a second edge of the first semiconductor die and connected to the first edge. An interface, wherein the memory package is electrically connected to the first semiconductor die and the second semiconductor die through the fourth interface. 4. The semiconductor package assembly according to claim 1, wherein the first semiconductor die and the memory package are arranged side by side along a first direction, and wherein the first semiconductor die is arranged along with the A second direction different from the first direction is stacked on the second semiconductor die. 5. The semiconductor package assembly of claim 4, wherein the third interface is disposed adjacent to the first interface and between the first interface and the memory package along the first direction. between. 6. The semiconductor package component according to claim 4, wherein the second semiconductor die includes: A first via (TV) interconnect disposed in the second semiconductor die and overlapping and electrically connected to the third interface of the first semiconductor die; and A second TV interconnect is disposed within the second interface and electrically connected to the first interface of the first semiconductor die. 7. The semiconductor package assembly of claim 6, wherein the second semiconductor die includes a third interface embedded in the second semiconductor die and electrically connected through the first semiconductor die. to the trench capacitor of the memory package. 8. A semiconductor packaging component, characterized in that it includes: A first semiconductor die and a second semiconductor die stacked on each other, wherein the first semiconductor die includes a first interface that overlaps and electrically connects a second interface disposed on the second semiconductor die. a second interface; a third interface arranged on the first edge of the first semiconductor die; and a memory package located next to the second semiconductor die, wherein the memory package is electrically connected to the first semiconductor die through the third interface; The second semiconductor die and the memory package are arranged side by side in a first direction, and wherein the second semiconductor die and the memory package are stacked in the second direction in a second direction different from the first direction. on the first semiconductor die. 9. The semiconductor package assembly of claim 8, wherein the third interface is arranged to overlap the memory package along the second direction. 10. The semiconductor package assembly of claim 8, wherein the first interface is disposed on a third edge of the first semiconductor die and the third edge is opposite to the first edge. 11. The semiconductor package component according to claim 8, wherein the first semiconductor die includes: A first through-hole (TV) interconnect disposed within the third interface and electrically connected to the memory package; and A second TV interconnect is disposed within the first interface and electrically connected to the second interface of the second semiconductor die. 12. The semiconductor package assembly of claim 11, wherein the memory package includes first conductive structures arranged in groups and having first distribution areas, and the third TV interconnect has a connection with the first The distribution area corresponds to and at least partially overlaps a second distribution area. 13. The semiconductor package assembly of claim 8, wherein the third TV interconnection is arranged in a first column and a second column adjacent to the first column, and includes: Ground TV interconnections, arranged in said first column only; and Signal TV interconnections, arranged in said first column and said second column, wherein the signal TV interconnections in said first column are interleaved with ground TV interconnections, and the signal TV interconnections in the second column are interleaved with Grounded TV interconnect is adjacent. 14. The semiconductor package assembly of claim 8, wherein the first semiconductor die includes a trench capacitor embedded within the third interface and electrically connected to the memory package. 15. The semiconductor package assembly according to claim 8, further comprising: A fan-out package includes the first semiconductor die, the second semiconductor die and the memory package, wherein the fan-out package further includes: A first redistribution layer (RDL) structure is disposed between the first semiconductor die and the second semiconductor die, wherein the first RDL structure is electrically connected to the first interface, the second interface, the third interface and the memory package; a second redistribution layer (RDL) structure electrically connected to the first RDL structure and separated from the memory package by the first RDL structure; A first molding compound covering the first RDL structure and the memory package; a second molding compound filling the space between the first RDL structure and the second RDL structure; a third TV interconnect passing through the second molding compound and electrically connected to the first RDL structure and the second RDL structure; and The second conductive structure is in contact with and electrically connected to the second RDL structure. 16. The semiconductor package assembly of claim 15, wherein the first semiconductor die includes a fifth interface disposed adjacent to the third interface and larger than the third interface. The interface is closer to the first edge. 17. The semiconductor package assembly of claim 16, wherein the fifth interface is electrically connected to the outside of the first edge through the second RDL structure instead of the first RDL structure. Second conductive structure. 18. A semiconductor packaging component, characterized in that it includes: Fan-out packaging, including: memory packaging; A first semiconductor die arranged next to the memory package along a first direction; and A second semiconductor die is arranged next to the memory package along a second direction, wherein the first semiconductor die includes: a first interface that overlaps with a second interface arranged on the second semiconductor die and electrically connecting the second interface; and a third interface disposed close to the memory package and electrically connected to the memory package. 19. The semiconductor package assembly of claim 18, wherein the first semiconductor die includes a fourth interface, wherein the third interface and the fourth interface are disposed on the first semiconductor die. on an adjacent edge, wherein the memory package is electrically connected to the first semiconductor die through a fourth interface of the first semiconductor die. 20. The semiconductor package assembly according to claim 18, further comprising: A first redistribution layer (RDL) structure is disposed between the first semiconductor die and the second semiconductor die, wherein the first RDL structure is electrically connected to the first interface, the second interface, the third interface and the memory package; and A second redistribution layer (RDL) structure is electrically connected to the first RDL structure and is separated from the memory package by the first RDL structure. 21. The semiconductor package assembly of claim 20, wherein the first semiconductor die is disposed between the first RDL structure and the second RDL structure and includes a component disposed at the first interface. and interconnected with a through hole (TV) in the third interface. 22. The semiconductor package assembly of claim 21, wherein the memory package includes first conductive structures arranged in groups and having first distribution areas; and TV interconnects arranged within the third interface There is a second distribution area corresponding to and at least partially overlapping the first distribution area. 23. The semiconductor package assembly of claim 21, wherein the TV interconnects provided within the third interface are arranged in a first column and a second column adjacent to the first column. , and includes: Ground TV interconnections, arranged in said first column only; and Signal TV interconnections, arranged in said first column and said second column, wherein the signal TV interconnections in said first column are interleaved with ground TV interconnections, and the signal TV interconnections in the second column are interleaved with Ground TV interconnection is adjacent. 24. The semiconductor package assembly of claim 21, wherein the first semiconductor die includes the first semiconductor die adjacent the third interface and disposed on a first edge of the first semiconductor die. The fifth interface is such that the third interface is arranged between the first interface and the fifth interface along the second direction. 25. The semiconductor package assembly of claim 24, wherein the fifth interface is electrically connected to the second conductive structure, the second conductive structure contacts and passes through a second RDL structure instead of the first RDL. The structure is electrically connected to the second redistribution layer structure, and the second conductive structure is located outside the first edge. 26. The semiconductor package assembly of claim 21, wherein the first semiconductor die includes a trench embedded within the third interface and electrically connected to the memory package through the first RDL structure. slot capacitor. 27. The semiconductor package assembly of claim 18, wherein the second semiconductor die is disposed between the first RDL structure and the second RDL structure and includes a connection with the first semiconductor die. The first interface and the third interface of the chip overlap through-hole (TV) interconnects. 28. The semiconductor package assembly of claim 27, wherein the second semiconductor die includes a trench capacitor embedded in the second semiconductor die, wherein the trench capacitor is in contact with the first semiconductor die. Three interfaces overlap and are electrically connected to the memory package. 29. A semiconductor packaging component, characterized by comprising: Fan-out packaging, including: A first redistribution layer (RDL) structure and a second RDL structure stacked on each other; a top semiconductor die and a memory package disposed on a first redistribution layer (RDL) structure, wherein the top semiconductor die includes a first interface; and A bottom semiconductor die disposed between the first RDL structure and the second RDL structure, wherein the bottom semiconductor die includes: a second interface overlapping the first interface; and a first via ( TV) interconnect disposed within the second interface and electrically connected to the first interface through the first RDL structure, and wherein the memory package is electrically connected to the top semiconductor die and the bottom semiconductor die through the first RDL structure rather than the second RDL structure. 30. The semiconductor package assembly of claim 29, wherein the top semiconductor die includes a third interface located next to the first interface and adjacent the memory package, wherein the memory package passes through the A third interface is electrically connected to the top semiconductor die. 31. The semiconductor package assembly of claim 30, wherein the bottom semiconductor die includes a second semiconductor die that overlaps the third interface and is electrically connected to the third interface through the first RDL structure. Through-hole (TV) interconnects. 32. The semiconductor package assembly of claim 29, wherein the bottom semiconductor die includes a fourth interface overlapping the memory package, wherein the memory package is electrically connected to the memory package through the fourth interface. The bottom semiconductor grain. 33. The semiconductor package assembly of claim 32, wherein the bottom semiconductor die includes a fifth interface disposed adjacent the fourth interface and on a first edge of the bottom semiconductor die , so that the fourth interface is disposed between the second interface and the fifth interface. 34. The semiconductor package assembly of claim 32, wherein the bottom semiconductor die includes a third via (TV) interconnect disposed within the fourth interface and electrically connected to the memory package . 35. The semiconductor package assembly of claim 34, wherein the third TV interconnection is arranged in a first column and a second column adjacent to the first column, and includes: Ground TV interconnections, arranged in said first column only; and Signal TV interconnections, arranged in said first column and said second column, wherein the signal TV interconnections in said first column are interleaved with ground TV interconnections, and the signal TV interconnections in the second column are interleaved with Ground TV interconnection is adjacent. 36. The semiconductor package assembly of claim 29, wherein the bottom semiconductor die includes a trench capacitor embedded in the bottom semiconductor die and electrically connected to the memory package.