CN117746950A - Nonvolatile memory chip and leakage current compensation circuit thereof - Google Patents

Abstract

The present disclosure provides a nonvolatile memory chip and a leakage current compensation circuit thereof, wherein the nonvolatile memory chip comprises an original memory array, a decoder module and a reference current module; the original storage array comprises a plurality of first storage units; the decoder module is used for selecting a target storage unit for reading operation from a plurality of first storage units; the leakage current compensation circuit comprises a compensation memory array, wherein the compensation memory array comprises a plurality of second memory cells; the leakage current compensation circuit is used for compensating a first leakage current on a bit line where the target memory cell is located when the target memory cell is subjected to a read operation. The leakage current compensation circuit is simple in structure and easy to realize, the temperature characteristic of the compensation current is matched with the real leakage current of the original memory array, the adaptive compensation effect can be achieved no matter the high-low temperature operation is performed, leakage currents of unselected cells can be timely, effectively and reliably compensated, and the reliability of the nonvolatile memory chip is improved.

Description

Nonvolatile memory chip and leakage current compensation circuit thereof

Technical Field

The disclosure relates to the field of chip technologies, and in particular, to a nonvolatile memory chip and a leakage current compensation circuit thereof.

Background

SLC (single-level cell memory technology) norflash (a non-volatile flash technology) chips are commonly used for code storage, an independent memory array is composed of a plurality of WLs (word lines) (such as 256 word lines or 512 word lines or even 1024 word lines) and a plurality of BLs (bit lines) (such as 2048 bit lines or 4096 bit lines or even 8192 bit lines), fig. 1 is a schematic structural diagram of a memory array of an exemplary non-volatile memory chip in the prior art, and fig. 1 is a schematic diagram of a norflash memory array composed of 1024 word lines and 8192 bit lines. The designer outside the array designs a reference cell that can be threshold adjusted to provide the memory array with a reference current for the read operation, although the designer may also directly generate a reference current from the reference current source. The bias conditions for the read operation for each port are as follows: CSL (common source line ) is biased at 0V (volts), the selected word line is biased at Vread (a voltage value), the unselected bit lines are biased at 0V, and the selected bit line is biased at Vbl (0.7 to 1V). According to the different data stored, the current on the bit line is different, and the current is compared with the reference current through the sense amplifier so as to judge whether the data value stored in the selected cell is 0 or 1.

1024 cells are connected in parallel to each bit line in the array of fig. 1, meaning that 1023 cells that are not selected contribute to leakage current in addition to the bit current provided by the selected cells. The Nor flash chip design of the long channel ignores the effect of leakage current of unselected cells in the read operation for two reasons: 1) The Nor flash process of the long channel has long enough channel length, and the gate oxide layer is thick enough, so that both the channel leakage current and the GIDL (gate-induced drain leakage, gate induced drain leakage current) are small; 2) The erase algorithm will pull the threshold of the over erase cell high, so that the leakage current of unselected cells has less impact during the read operation. However, as the channel length is smaller and smaller, the thickness of the gate oxide layer is thinner and thinner, and the channel leakage current and GIDL current affect the read data, so that the effect of the leakage current of unselected cells on the read operation is revealed.

The conventional Nor flash chip design generally applies negative voltage on unselected word lines to inhibit the channel leakage current of the over erase cell during erase verification, but the applied negative voltage reduces the channel leakage current and increases the GIDL leakage current, and the higher the threshold voltage is, the more negative the gate voltage is, the greater the GIDL leakage current will affect the accuracy of erase verification, so that the compensation of the leakage current during erase verification is also necessary.

The existing leakage current compensation focuses more on the compensation of AC (alternating current) current of global bit lines, and generally adopts a scheme of inhibiting the leakage current of unselected cells, and is implemented as follows: negative voltage is applied to unselected word lines to suppress channel leakage current, and there are two scheme defects to suppress leakage current: 1) The applied negative voltage reduces the channel leakage current and increases the GIDL leakage current, and the higher the threshold voltage is, the more negative the grid voltage is, the larger the GIDL leakage current is, and the inhibition effect is weakened; 2) The establishment of the negative voltage requires a certain time, which is acceptable for erase verification or over-erase verification, but unacceptable for read operation, and if the negative voltage is maintained at all times, the standby current increases, which is not suitable for low power consumption applications.

Disclosure of Invention

The technical problem to be solved by the present disclosure is to overcome the defect that in the prior art, in the process of reading a nonvolatile memory chip, leakage current of unselected cells cannot be compensated timely, effectively and reliably, resulting in reduced reliability of the nonvolatile memory chip, and provide a nonvolatile memory chip and a leakage current compensation circuit thereof.

The technical problems are solved by the following technical scheme:

in a first aspect, a leakage current compensation circuit of a nonvolatile memory chip is provided, wherein the nonvolatile memory chip comprises an original memory array, a decoder module and a reference current module;

the original storage array comprises a plurality of first storage units;

the reference current module is used for providing reference current corresponding to reading operation for the original storage array;

the decoder module is used for selecting a target storage unit for reading operation from a plurality of first storage units;

the leakage current compensation circuit comprises a compensation storage array, wherein the compensation storage array comprises a plurality of second storage units;

wherein the number and specification parameters of the second storage units are determined based on the number and specification parameters of the first storage units;

the leakage current compensation circuit is used for compensating a first leakage current on a bit line where the target memory cell is located when the target memory cell is subjected to a read operation.

The number and specification parameters of the second storage units of the compensation storage Array in the leakage current compensation circuit are determined based on the number and specification parameters of the first storage units in the original storage Array, so that the temperature characteristic of the compensation current is matched with the real leakage current of the original Array cell, no matter how high-low temperature operation is performed, the matched compensation effect can be achieved, and the compensation effect is not influenced by the process and the temperature. When a read operation is executed on a target memory cell in an original memory array of a nonvolatile memory chip, a first leakage current on a bit line where the target memory cell is located can be compensated by a leakage current compensation circuit; the leakage current compensation circuit has a simple structure and is easy to realize, leakage current of unselected cells can be timely, effectively and reliably compensated, and the reliability of the nonvolatile memory chip is improved.

Preferably, the original memory array includes Nw first word lines, nb first bit lines, and nw×nb first memory cells, where each first bit line is connected in parallel with Nw first memory cells, each first word line is connected in parallel with Nb first memory cells, and Nw and Nb are positive integers;

the compensation storage array comprises Mw second word lines and Mb second bit lines, the Mw second word lines are connected, the Mb second bit lines are connected, the Mw second bit lines are connected with Mb second storage units in parallel, and both Mw and Mb are positive integers;

where mw×mb=nw.

The leakage current compensation circuit of the nonvolatile memory chip designs a unique compensation memory array corresponding to an original memory array based on the original memory array in the nonvolatile memory chip, and when a read operation is performed on a target memory cell in the original memory array, first leakage current on a bit line where the target memory cell is located can be compensated through the compensation memory array in the leakage current compensation circuit; the compensation memory array has compact structure and small area, can timely, effectively and reliably compensate the leakage current of unselected cells, has the compensation effect free from the influence of the process and the temperature, and improves the reliability of the nonvolatile memory chip.

Preferably, the original memory array includes 1024 first word lines, 8192 first bit lines, and 1024×8192 first memory cells;

the compensation memory array includes 32 second word lines, 32 second bit lines, and 1024 second memory cells.

Preferably, the specification parameters of the second storage unit in the compensation storage array are the same as the specification parameters of the first storage unit in the original storage array.

According to the leakage current compensation circuit of the nonvolatile memory chip, the specification parameters of the second memory cells in the compensation memory Array are the same as those of the first memory cells in the original memory Array, so that the temperature characteristic of compensation current is completely matched with the real leakage current of the original Array cell, the adaptive compensation effect can be achieved no matter the operation is performed at high and low temperatures, and the compensation effect is not influenced by the process and the temperature. When a read operation is executed on a target memory cell in an original memory array of a nonvolatile memory chip, a first leakage current on a bit line where the target memory cell is located can be compensated by a leakage current compensation circuit; the leakage current compensation circuit has a simple structure and is easy to realize, leakage current of unselected cells can be timely, effectively and reliably compensated, and the reliability of the nonvolatile memory chip is improved.

Preferably, the second memory cell in the compensation memory array corresponds to an intrinsic state.

According to the leakage current compensation circuit of the nonvolatile memory chip, the first leakage current on the bit line where the target memory cell is located can be compensated through the compensation memory array; the second memory cell in the compensation memory array corresponds to the intrinsic state, the leakage current compensation of the intrinsic state is a compromise choice for the leakage current compensation of all 1 background data and all 0 background data, and the compensation of the first leakage current can be realized without specially distinguishing the data value corresponding to the reading operation; the compensation memory array has compact structure and small area, can timely, effectively and reliably compensate the leakage current of unselected cells, has the compensation effect free from the influence of the process and the temperature, and improves the reliability of the nonvolatile memory chip.

Preferably, the decoder module includes a word line decoder and a bit line decoder;

the word line decoder is used for receiving a first read word line voltage and determining a target word line corresponding to a read operation;

the bit line decoder is used for receiving a first read bit line voltage and determining a target bit line corresponding to a read operation so as to select the target memory cell.

Preferably, the leakage current compensation circuit is further applied to a verification operation of the nonvolatile memory chip;

the verify operations include an erase verify operation, and/or an over-erase verify operation, and/or a program verify operation.

Preferably, the second word line of the compensation memory array is used for receiving a second read word line voltage during a verification operation;

the second read wordline voltage is equal to the first read wordline voltage.

Preferably, the nonvolatile memory chip further includes an amplifier;

when a read operation is performed on the target memory cell, a first input end of the amplifier is used for receiving the first leakage current and a bit current corresponding to the target memory cell, and obtaining a first current based on the sum of the first leakage current and the bit current;

the second input end of the amplifier is used for receiving the reference current and a second leakage current corresponding to the compensation storage array, and obtaining a second current based on the sum of the reference current and the second leakage current;

the output end of the amplifier is used for determining that the data value stored by the target storage unit is 1 when the first current is larger than the second current;

and the output end of the amplifier is used for determining that the data value stored by the target storage unit is 0 when the first current is smaller than the second current.

In a second aspect, there is further provided a nonvolatile memory chip, the nonvolatile memory chip includes an original memory array, a decoder module, and a reference current module, and a leakage current compensation circuit of the nonvolatile memory chip.

On the basis of conforming to the common knowledge in the art, the preferred conditions can be arbitrarily combined to obtain the preferred examples of the disclosure.

The positive progress effect of the present disclosure is:

according to the nonvolatile memory chip and the leakage current compensation circuit thereof, the number and the specification parameters of the second memory cells in the leakage current compensation circuit are determined based on the number and the specification parameters of the first memory cells, so that the temperature characteristic of the compensation current is matched with the real leakage current of the original Array cell, no matter how high-low temperature operation is performed, the matched compensation effect can be achieved, and the compensation effect is not influenced by the process and the temperature. When a read operation is executed on a target memory cell in an original memory array of a nonvolatile memory chip, a first leakage current on a bit line where the target memory cell is located can be compensated by a leakage current compensation circuit; the leakage current compensation circuit has a simple structure and is easy to realize, leakage current of unselected cells can be timely, effectively and reliably compensated, and the reliability of the nonvolatile memory chip is improved.

Drawings

FIG. 1 is a schematic diagram of a memory array of an exemplary prior art nonvolatile memory chip;

fig. 2 is a first schematic structural diagram of a leakage current compensation circuit of a nonvolatile memory chip according to embodiment 1 of the present disclosure;

fig. 3 is a first schematic structural diagram of an original memory array in the leakage current compensation circuit of the nonvolatile memory chip provided in embodiment 1 of the disclosure;

fig. 4 is a schematic diagram of a first structure of a compensation memory array in a leakage current compensation circuit of a nonvolatile memory chip according to embodiment 1 of the present disclosure;

FIG. 5 is a schematic diagram of a second structure of an original memory array in a leakage current compensation circuit of a nonvolatile memory chip according to embodiment 1 of the present disclosure;

fig. 6 is a schematic diagram of a second structure of a compensation memory array in the leakage current compensation circuit of the nonvolatile memory chip according to embodiment 1 of the present disclosure;

FIG. 7 is a schematic diagram of ideal current-voltage curves of cells in different states in a read operation according to the prior art;

FIG. 8 is a schematic diagram of leakage current of a MOS transistor in the prior art;

fig. 9 is a second schematic structural diagram of a leakage current compensation circuit of a nonvolatile memory chip according to embodiment 1 of the present disclosure.

Detailed Description

The present disclosure is further illustrated by way of examples below, but is not thereby limited to the scope of the examples described.

Example 1

The present embodiment provides a leakage current compensation circuit of a nonvolatile memory chip, as shown in fig. 2, the nonvolatile memory chip includes an original memory array 1, a decoder module 2 and a reference current module 3;

the original memory array 1 comprises a plurality of first memory cells 11;

the reference current module 3 is used for providing reference current corresponding to the read operation for the original memory array 1;

the decoder module 2 is configured to select a target memory cell for a read operation from a plurality of first memory cells 11;

the leakage current compensation circuit comprises a compensation memory array 4, wherein the compensation memory array 4 comprises a plurality of second memory cells 41;

wherein the number and specification parameters of the second storage units 41 are determined based on the number and specification parameters of the first storage units 11;

the leakage current compensation circuit is used for compensating a first leakage current on a bit line where the target memory cell is located when the target memory cell is subjected to a read operation.

Specifically, the decoder module 2 is electrically connected to the original memory array 1, and the decoder module 2 is configured to select a target memory cell for a read operation from a plurality of first memory cells 11; the reference current module 3 is used for providing a reference current corresponding to the read operation for the original memory array 1, and the leakage current compensation circuit is electrically connected with the reference current module 3.

When a first memory cell (i.e., a target memory cell) in an original array is read by connecting the word line and the bit line, the target memory cell needs to be selected by a decoder module, and during the read operation, a leakage current (i.e., a first leakage current) exists on the bit line where the target memory cell is located, so that an error occurs in the bit current corresponding to the target memory cell, for example, the true bit current is increased, thereby affecting the read operation, and therefore, the first leakage current needs to be compensated.

The number and specification parameters of the second memory cells 41 of the compensation memory Array in the leakage current compensation circuit disclosed by the disclosure are determined based on the number and specification parameters of the first memory cells 11 in the original memory Array, so that the temperature characteristic of the compensation current is matched with the real leakage current of the original Array cell, no matter whether the high-low temperature operation is performed, the adaptive compensation effect can be achieved, and the compensation effect is not influenced by the process and the temperature.

When a read operation is performed on a target memory cell in an original memory array of the nonvolatile memory chip, the leakage current compensation circuit of the nonvolatile memory chip of the embodiment can compensate a first leakage current on a bit line where the target memory cell is located; the leakage current compensation circuit has a simple structure and is easy to realize, leakage current of unselected cells can be timely, effectively and reliably compensated, the compensation effect is not influenced by the process and the temperature, and the reliability of the nonvolatile memory chip is improved.

In an alternative embodiment, as shown in fig. 3 and 4, the original memory array includes Nw first word lines, nb first bit lines, and nw×nb first memory cells 11, where each first bit line is connected in parallel with Nw first memory cells 11, each first word line is connected in parallel with Nb first memory cells 11, where Nw and Nb are positive integers; the compensation memory array comprises Mw second word lines and Mb second bit lines, the Mw second word lines are connected, the Mb second bit lines are connected, the Mw second bit lines are connected with Mb second memory cells 41 in parallel, and Mw and Mb are positive integers; where mw×mb=nw.

For the original memory array, wl_1 in fig. 3 is the 1 st first word line, wl_2 is the 2 nd first word line, and wl_nw is the Nw th first word line; BL_1 is the 1 st first bit line, BL_2 is the 2 nd first bit line, BL_Nb is the Nb first bit line, CSL_N is the common source line; each first bit line is connected with Nw first memory cells 11 in parallel, and each first word line is connected with Nb first memory cells 11 in parallel, that is, a total of nw×nb first memory cells 11 in the original memory array.

For the compensating memory array, wl_1 in fig. 4 is the 1 st second word line, wl_2 is the 2 nd second word line, and wl_mw is the Mw second word line; BL_1 is the 1 st second bit line, BL_2 is the 2 nd second bit line, BL_Mb is the Mb second bit line, CSL_M is the common source line; the Mw second word lines are connected and the Mb second bit lines are connected, and the second bit lines are connected in parallel with the mw×mb second memory cells 41, i.e. all the second sub-lines in the compensation memory array are all connected together, and when seen on the second bit lines, the mw×mb second memory cells are connected in parallel together.

The number and specification parameters of the second memory cells 41 of the compensation memory array in the leakage current compensation circuit are determined based on the number and specification parameters of the first memory cells 11 in the original memory array; specifically, the number Nw of the first memory cells connected in parallel on any one first bit line in the original memory array is the same as the number of all the second memory cells in the compensation memory array, that is, mw×mb=nw, and the compensation memory array has simple circuit and small occupied area.

The leakage current compensation circuit of the nonvolatile memory chip of the embodiment designs a unique compensation memory array corresponding to the original memory array based on the original memory array in the nonvolatile memory chip, and when a read operation is performed on a target memory cell in the original memory array, the first leakage current on a bit line where the target memory cell is located can be compensated by the compensation memory array in the leakage current compensation circuit; the compensation memory array has compact structure and small area, can timely, effectively and reliably compensate the leakage current of unselected cells, has the compensation effect free from the influence of the process and the temperature, and improves the reliability of the nonvolatile memory chip.

In an alternative embodiment, as shown in fig. 5 and 6, the original memory array 1 includes 1024 first word lines, 8192 first bit lines, and 1024×8192 first memory cells 11; the compensation memory array 4 includes 32 second word lines, 32 second bit lines, and 1024 second memory cells 41.

The original memory Array (i.e., array) shown in fig. 5 includes 1024 first word lines, WL0 to WL1023, 8192 first bit lines BL0 to BL8191, respectively, and CSL is a common source line; the first memory cells on a certain first bit line are M0, … …, mcell, M1023, respectively, for a total of 1024, where Mcell is a target memory cell selected by a read operation. The bias conditions for the read operation for each port are as follows: CSL is biased at 0V (corresponding to ground in fig. 5), the selected word line (corresponding to WLsel in fig. 5) is biased at Vread volts, the unselected bit line is biased at 0V, and the selected bit line is biased at Vbl volts, e.g., 0.7 to 1 volt, to select the target memory cell Mcell so that there will be a reference current flowing through the target memory cell Mcell; vussel is the read word line voltage, i.e., the unselected word lines are biased at 0v, vussel=0.

The compensation memory array (i.e., mini array) shown in fig. 6 includes 32 second word lines, WL0 to WL31, respectively, and BL0 to BL31, respectively, for 32 second bit lines, mc0, mc1, … …, M1023, respectively, for a total of 1024 second memory cells. The number of the first memory cells connected in parallel on any one first bit line in the original memory array is 1024, which is the same as the number of all the second memory cells in the compensation memory array.

The compensation memory array shown in fig. 6 is composed of 32 word lines and 32 bit lines, and in practice, the numbers of the word lines and the bit lines can be freely combined, so long as the number of parallel cells is matched with the number of unselected cells in the original memory array, and the number of parallel first memory cells on any one first bit line in the original memory array is ensured to be the same as the number of all second memory cells in the compensation memory array.

In an alternative embodiment, the specification parameters of the second memory cells in the compensated memory array are the same as the specification parameters of the first memory cells in the original memory array.

Specifically, the size of the second memory cell is the same as that of the first memory cell, the interval between cells, the transconductance gm, the temperature characteristic of the cells, the bias voltage of the grid electrode, the bias voltage of the source electrode, the bias voltage of the drain electrode, the bias voltage of the well and the like, so that compensation currents which are matched with the leakage current of the first memory array are obtained under different temperature conditions and different operation conditions.

According to the leakage current compensation circuit of the nonvolatile memory chip, the specification parameters of the second memory cells in the compensation memory Array are the same as those of the first memory cells in the original memory Array, so that the temperature characteristic of compensation current is completely matched with the real leakage current of the original Array cell, the adaptive compensation effect can be achieved no matter the operation is performed at high and low temperatures, and the compensation effect is not influenced by the process and the temperature. When a read operation is executed on a target memory cell in an original memory array of a nonvolatile memory chip, a first leakage current on a bit line where the target memory cell is located can be compensated by a leakage current compensation circuit; the leakage current compensation circuit has a simple structure and is easy to realize, leakage current of unselected cells can be timely, effectively and reliably compensated, and the reliability of the nonvolatile memory chip is improved.

In an alternative embodiment, the second memory cell in the compensated memory array corresponds to an intrinsic state.

Fig. 7 is a schematic diagram of ideal current-voltage curves of cells in different states in a read operation according to the prior art, corresponding to ideal current-voltage curves of program cell (program cell), erase cell (erase cell) and reference cell (reference cell). Where the abscissa Vg represents the voltage and the ordinate Id represents the current, it can be seen in fig. 7 that the current Iers of the erase cell is larger than the reference current Iref, and the current Ipgm of the program cell is smaller than the reference current Iref, iers-Iref being the current difference of the read erase cell, iref-Ipgm being the current difference of the read program cell. As can be seen from fig. 7, 1023 unselected cells are connected in parallel on the same bit line during the read operation, the generated leakage current Ileak (i.e. the first leakage current) is superimposed on the bit current of the selected target memory cell, so that the actual bit line current becomes large, the current difference of the actual read erase cell is ires+ileak-Iref, the current difference of the read program cell is Iref-Ipgm-Ileak, and when Ileak increases, the current difference of the read program cell becomes small, which increases the difficulty of reading the program cell, and even misread the program cell into the erase cell.

The memory cell may be a MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor), and fig. 8 is a schematic diagram of a leakage current of the MOS transistor in the prior art, where I1 is a Gate FN tunneling leakage current, I2 is a Gate HCI (hot carrier injection ) leakage current, I3 is a reverse biased PN junction leakage current, I4 is a subthreshold leakage current, I5 is a GIDL leakage current, I6 is a channel through current, gate is a Gate, source is a Source, drain is a Drain, and Well is a Well region.

The leakage current of the unselected cells described in the present disclosure is the sum of I3, I4, I5, and I6, where I3, I6 are negligible, and I4, I5 are related to the data stored in the cells and the bias voltage of the gate. The smaller the threshold voltage of the cell is, the smaller the sub-threshold leakage current I4 is when the gate is at 0V, and the larger the GIDL of the cell is when the threshold voltage of the cell is higher or the gate voltage is more negative. Thus, in the read operation of FIG. 8, the leakage current of the unselected cells is related to the gate voltage, which is typically 0V to meet the read speed, but the stored values are unpredictable, so that the data leakage current of all 0 s is different from the data leakage current of all 1 s.

Comparing the bit current of the selected cell in the original memory array with the reference current, it can be determined whether the data stored in the cell is 0 or 1. However, in reality, due to the existence of the leakage current, besides the bit current Icell and the reference current Iref of the cells, the leakage currents Ileak1 and Ileak2 are shown in the original memory array, where Ileak1 represents the overall leakage current (i.e. the first leakage current) of the bit line where the unselected cells are located, and Ileak2 represents the leakage current corresponding to all cells in the compensation memory array, so that icell+ileak1 and iref+ileak2 are actually compared. From the analysis of fig. 8, ileak1 is related to the data background (whether the stored value is 0 or 1) and the gate bias voltage, so that compensation using the leakage current of the data background of all 0's or all 1's is not appropriate.

The UV (ultraviolet) state is an intrinsic state of Floating Gate cell (floating gate transistor unit), and the cell leakage current in the intrinsic state is compensated, so that the leakage current compensation of 50-100% can be achieved; therefore, the second memory cell in the compensation memory array corresponds to the intrinsic state, so that the current difference of the read current of the read program cell or the erase cell can be increased, and the compensation of the first leakage current is realized.

The leakage current compensation circuit of the nonvolatile memory chip of the embodiment can compensate the first leakage current on the bit line where the target memory cell is located through the compensation memory array; the second memory cell in the compensation memory array corresponds to the intrinsic state, the leakage current compensation of the intrinsic state is a compromise choice for the leakage current compensation of all 1 background data and all 0 background data, and the compensation of the first leakage current can be realized without specially distinguishing the data value corresponding to the reading operation; the compensation memory array has compact structure and small area, can timely, effectively and reliably compensate the leakage current of unselected cells, has the compensation effect free from the influence of the process and the temperature, and improves the reliability of the nonvolatile memory chip.

In an alternative embodiment, decoder module 2 includes a word line decoder and a bit line decoder;

the word line decoder is used for receiving the first read word line voltage and determining a target word line corresponding to the read operation;

the bit line decoder is used for receiving the first read bit line voltage and determining a target bit line corresponding to the read operation so as to select a target memory cell.

As shown in fig. 9, array is an original memory Array, XDEC is a word line decoder, and during a read operation, a first read word line voltage is applied to a corresponding word line according to address information, YDEC is a bit line decoder, and during a read operation, a first read bit line voltage is applied to a corresponding bit line according to address information. The original memory Array (i.e., array) includes 1024 first word lines, 8192 first bit lines, the first read word line voltage being Vread volts, the target word line being WLsel, the target memory cell being Mcell, the selected target bit line being biased at Vbl volts.

The Array in fig. 9 is composed of 1024 word lines and 8192 bit lines, wherein Mcell is the cell to be read (i.e. the target memory cell) selected by the address, and there are another 1023 cells connected in parallel to the cell sharing one bit line, only two cells of which are shown as M0 and M1023, respectively. Mref is a reference cell that can be used to generate a reference current Iref after threshold adjustment, where the gate is biased at Vread, the source is connected to Ground, the drain is biased to Vbl during read operation, and the generated reference current is Iref. Mrysa and Mrysb are Y-direction gates referenced to the cell and are sized to match YDEC. The Mini array (i.e. the compensation memory array) is a small array composed of 32 word lines and 32 bit lines, all word lines of the small array are connected together, and all bit lines are also connected together, so that 1024 cells are connected in parallel as seen from the bit lines.

In an alternative embodiment, the leakage current compensation circuit is further applied to a verification operation of the nonvolatile memory chip; the verify operations include, but are not limited to, erase verify operations, over-erase verify operations, program verify operations, and the like.

Specifically, the second word line of the compensation memory array is configured to receive a second read word line voltage during a verify operation; the second read wordline voltage is equal to the first read wordline voltage.

The nonvolatile memory chip is internally provided with a verification operation, and the verification operation is a read operation, and the verification operation comprises but is not limited to an erasure verification operation, an over erasure verification operation, a programming verification operation and the like; unlike in the erase verification and over erase verification, the channel leakage current is dominant due to the existence of the over erase cell, so that the gate voltage of the unselected cell is biased to negative voltage to inhibit the channel leakage current.

Vussel in fig. 9 represents a first read word line voltage in the original memory array, and vussel in fig. 9 represents a second read word line voltage in the compensated memory array. The second word line of the compensation memory array receives a second read word line voltage during a verification operation, the first word line of the original memory array receives a first read word line voltage during the verification operation, and the second read word line voltage is equal to the first read word line voltage; that is, the gate voltage in the original memory array is biased to vussel to suppress the channel leakage current, and the gate voltage in the compensation memory array is biased to vussel to suppress the channel leakage current.

The leakage current compensation circuit of the nonvolatile memory chip not only can compensate leakage current in the read operation process of the nonvolatile memory chip, but also can compensate leakage current in the check operation process of the nonvolatile memory chip, has a wide application range of leakage current compensation, has a compact structure and a small area of a compensation memory array, can timely, effectively and reliably compensate leakage current of unselected cells, has no influence of process and temperature, and improves the reliability of the nonvolatile memory chip.

In an alternative embodiment, the nonvolatile memory chip further includes an amplifier;

when a read operation is performed on a target memory cell, a first input end of the amplifier is used for receiving a first leakage current and a bit current corresponding to the target memory cell, and obtaining the first current based on the sum of the first leakage current and the bit current;

the second input end of the amplifier is used for receiving the reference current, compensating the second leakage current corresponding to the memory array and obtaining the second current based on the sum of the reference current and the second leakage current;

the output end of the amplifier is used for determining that the data value stored in the target storage unit is 1 when the first current is larger than the second current;

the output end of the amplifier is used for determining that the data value stored in the target storage unit is 0 when the first current is smaller than the second current.

The amplifier of the present disclosure may also be referred to as a sense amplifier.

As shown in fig. 9, sense is an amplifier, and a first input terminal of the amplifier is configured to receive a first leakage current Ileak1 and a bit current Icell corresponding to a target memory cell, and obtain a first current based on a sum icell+ileak1 of the first leakage current and the bit current; the second input end of the amplifier is used for receiving the reference current Iref and compensating the second leakage current Ileak2 corresponding to the memory array, and obtaining the second current based on the sum Iref+Ileak2 of the reference current and the second leakage current; the output end of the amplifier is used for determining that the data value stored in the target storage unit is 1 when the first current is larger than the second current; the output end of the amplifier is used for determining that the data value stored in the target storage unit is 0 when the first current is smaller than the second current. Thereby enabling the determination of the data value stored by the target storage unit.

The leakage current compensation circuit of the nonvolatile memory chip not only can carry out leakage current compensation aiming at the reading operation process of the nonvolatile memory chip, but also can accurately judge whether the data value stored in the target memory cell corresponding to the reading operation is 0 or 1, thereby realizing the determination of the data value stored in the target memory cell; meanwhile, the compensation memory array has compact structure and smaller area, can timely, effectively and reliably compensate leakage current of unselected cells, has the compensation effect free from the influence of process and temperature, and improves the reliability of the nonvolatile memory chip.

In this embodiment, a Nor flash chip is mainly taken as an example, and the leakage current compensation circuit of the nonvolatile memory chip is described in detail, but the protection scope of the disclosure is not limited thereby, for example, the leakage current compensation circuit of the nonvolatile memory chip of the disclosure may also be used to compensate the leakage current of a Nand flash (a nonvolatile flash technology) chip.

Example 2

The present embodiment provides a nonvolatile memory chip including an original memory array 1, a decoder module 2, and a reference current module 3, as shown in fig. 2, and a leakage current compensation circuit of the nonvolatile memory chip in embodiment 1.

The nonvolatile memory chip may also include other components, such as an amplifier, etc.

The nonvolatile memory chip can be a Nor flash chip and/or a Nand flash chip.

The nonvolatile memory chip of the embodiment comprises an original memory array, a decoder module, a reference current module and a leakage current compensation circuit of the nonvolatile memory chip in embodiment 1; when a read operation is executed on a target memory cell in an original memory array of a nonvolatile memory chip, a first leakage current on a bit line where the target memory cell is located can be compensated by a leakage current compensation circuit; the leakage current compensation circuit has a simple structure and is easy to realize, leakage current of unselected cells can be timely, effectively and reliably compensated, the compensation effect is not influenced by the process and the temperature, and the reliability of the nonvolatile memory chip is improved.

While specific embodiments of the present disclosure have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the disclosure is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the disclosure, but such changes and modifications fall within the scope of the disclosure.

Claims (10)

1. The leakage current compensation circuit of the nonvolatile memory chip is characterized in that the nonvolatile memory chip comprises an original memory array, a decoder module and a reference current module;

the original storage array comprises a plurality of first storage units;

the reference current module is used for providing reference current corresponding to reading operation for the original storage array;

the decoder module is used for selecting a target storage unit for reading operation from a plurality of first storage units;

the leakage current compensation circuit comprises a compensation storage array, wherein the compensation storage array comprises a plurality of second storage units;

wherein the number and specification parameters of the second storage units are determined based on the number and specification parameters of the first storage units;

the leakage current compensation circuit is used for compensating a first leakage current on a bit line where the target memory cell is located when the target memory cell is subjected to a read operation.

2. The leakage current compensation circuit of claim 1 wherein said original memory array comprises Nw first word lines, nb first bit lines, and nw×nb first memory cells, each of said first bit lines having Nw first memory cells connected in parallel, each of said first word lines having Nb first memory cells connected in parallel, each of Nw and Nb being positive integers;

the compensation storage array comprises Mw second word lines and Mb second bit lines, the Mw second word lines are connected, the Mb second bit lines are connected, the Mw second bit lines are connected with Mb second storage units in parallel, and both Mw and Mb are positive integers;

where mw×mb=nw.

3. The leakage current compensation circuit of claim 2, wherein said original memory array comprises 1024 of said first word lines, 8192 of said first bit lines, and 1024 x 8192 of said first memory cells;

the compensation memory array includes 32 second word lines, 32 second bit lines, and 1024 second memory cells.

4. The leakage current compensation circuit of claim 2, wherein the specification parameter of the second memory cell in the compensated memory array is the same as the specification parameter of the first memory cell in the original memory array.

5. The leakage current compensation circuit of claim 1 wherein the second memory cell in the compensated memory array corresponds to an intrinsic state.

6. The leakage current compensation circuit of claim 2, wherein the decoder module comprises a word line decoder and a bit line decoder;

the word line decoder is used for receiving a first read word line voltage and determining a target word line corresponding to a read operation;

the bit line decoder is used for receiving a first read bit line voltage and determining a target bit line corresponding to a read operation so as to select the target memory cell.

7. The leakage current compensation circuit of claim 6, wherein the leakage current compensation circuit is further applied to a verify operation of the non-volatile memory chip;

the verify operations include an erase verify operation, and/or an over-erase verify operation, and/or a program verify operation.

8. The leakage current compensation circuit of claim 7 wherein the second word line of the compensated memory array is configured to receive a second read word line voltage during a verify operation;

the second read wordline voltage is equal to the first read wordline voltage.

9. The leakage current compensation circuit according to any one of claims 1 to 8, wherein the nonvolatile memory chip further comprises an amplifier;

when a read operation is performed on the target memory cell, a first input end of the amplifier is used for receiving the first leakage current and a bit current corresponding to the target memory cell, and obtaining a first current based on the sum of the first leakage current and the bit current;

the second input end of the amplifier is used for receiving the reference current and a second leakage current corresponding to the compensation storage array, and obtaining a second current based on the sum of the reference current and the second leakage current;

the output end of the amplifier is used for determining that the data value stored by the target storage unit is 1 when the first current is larger than the second current;

and the output end of the amplifier is used for determining that the data value stored by the target storage unit is 0 when the first current is smaller than the second current.

10. A non-volatile memory chip comprising a raw memory array, a decoder module, and a reference current module, and a leakage current compensation circuit of the non-volatile memory chip of any of claims 1-9.