CN117714388B - Hybrid circuit transmission and packet transmission method and system - Google Patents
Hybrid circuit transmission and packet transmission method and system Download PDFInfo
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- CN117714388B CN117714388B CN202410156624.6A CN202410156624A CN117714388B CN 117714388 B CN117714388 B CN 117714388B CN 202410156624 A CN202410156624 A CN 202410156624A CN 117714388 B CN117714388 B CN 117714388B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a hybrid circuit transmission and packet transmission method and system, relate to the communication technology field, apply to network on chip NoC circuit, noC circuit includes M x N NoC nodes, M, N is the integer greater than 1, M rows NoC nodes form M horizontal transmission paths, N columns NoC nodes form N longitudinal transmission paths, set up at least one first horizontal transmission path and every longitudinal transmission path in M horizontal transmission paths support the job configuration vector transmission based on packet transmission, other second horizontal transmission paths in M horizontal transmission paths support the data transmission of the temporary locking circuit based on route establishment; the method comprises the following steps: transmitting configuration vector information through each first transverse transmission path and each longitudinal transmission path; a temporary lock circuit is then formed based on the second transverse transmission path established by the route, and the communication data is transmitted through the temporary lock circuit. The invention improves the real-time performance of the NoC circuit.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method and a system for hybrid circuit transmission and packet transmission.
Background
For a network on chip (NetworkOnChip, noC) circuit, since data transmission can be performed between a plurality of nodes in the NoC circuit through a transverse direction or a longitudinal direction, a transmission path of the data is not unique, if the transmission path is long, a delay of data transmission is long, and a time for the data to reach a receiving end is late, which can cause a plurality of groups of data with fixed order to need to be reordered, and for a communication system, excessive delay and reorder overhead of the communication system can be caused if the data is reordered.
At present, in order to solve the problem that data is not reordered, a circuit capable of transmitting data through route locking is provided, and a transmission path is temporarily unique, so that the data does not need to be reordered, and hardware cost of data reordering is reduced.
However, the method is only suitable for large data with a relatively regular rule, but is not suitable for small data, the flexibility of circuit data transmission based on temporary locking is relatively poor, the transmission efficiency is low, and in addition, for real-time applications of a system facing real-time stream processing, such as a communication baseband, a communication route, a radar, a game, a video, artificial intelligence training, artificial intelligence reasoning and the like, if the time delay of data transmission is relatively large, the system requirement is difficult to meet.
Disclosure of Invention
The invention provides a hybrid circuit transmission and packet transmission method and system, which are used for solving the problems of poor flexibility of data transmission, low short packet transmission efficiency, large time delay of long packet data transmission, difficulty in meeting system requirements and high cost of reorder buffer silicon in the prior art.
The invention provides a hybrid circuit transmission and packet transmission method, which is applied to a network on chip (NoC) circuit, wherein the NoC circuit comprises M x N NoC nodes, M, N are integers larger than 1, M rows of NoC nodes form M transverse transmission paths, N columns of NoC nodes form N longitudinal transmission paths, at least one first transverse transmission path in the M transverse transmission paths and each longitudinal transmission path support operation configuration vector transmission based on packet transmission, and other second transverse transmission paths in the M transverse transmission paths support data transmission of a temporary locking circuit established based on routing;
The method comprises the following steps:
Transmitting configuration vector information through each of the first transverse transmission paths and each of the longitudinal transmission paths; the configuration vector information is used for configuring at least one operation of the function module on the target node of the route end point;
And forming a temporary locking circuit based on the second transverse transmission path established by the route, and transmitting communication data through the temporary locking circuit.
According to the present invention, there is provided a hybrid circuit transmission and packet transmission method, the transmission of configuration vector information through each of the first transverse transmission paths and each of the longitudinal transmission paths, comprising:
Acquiring a source node and a target node corresponding to configuration vector information to be transmitted;
Determining a target transmission path corresponding to the configuration vector information to be transmitted based on the source node, the target node, each first transverse transmission path and each longitudinal transmission path;
And transmitting the configuration vector information to be transmitted to the target node from the source node according to the target transmission path, and transmitting the configuration vector information to be transmitted to a corresponding target functional module through the target node to serve as one-time configuration of at least one job running on the target functional module.
According to the method for transmitting the hybrid circuit and the packet provided by the invention, the determining the target transmission path corresponding to the configuration vector information to be transmitted based on the source node, the target node, each first transverse transmission path and each longitudinal transmission path includes:
determining an intersecting node where a first transverse transmission path where the source node is located intersects with a longitudinal transmission path where the target node is located, and taking the first transmission path from the source node to the intersecting node and the second transmission path from the intersecting node to the target node as the target transmission paths.
According to the method for transmitting the mixed circuit and the packet, the configuration vector information to be transmitted is transmitted from the source node to the target node according to the target transmission path, and the method comprises the following steps:
And transmitting the configuration vector information to be transmitted from the source node to the intersection node through the first transmission path, and transmitting the configuration vector information to be transmitted from the intersection node to the target node through the second transmission path.
According to the present invention, there is provided a hybrid circuit transmission and packet transmission method, each NoC node supporting short packet switching and circuit switching via a temporary lock circuit, the method further comprising:
Under the condition that a preset bit of a routing packet to be transmitted is first information, characterizing that the routing packet only carries address information and does not carry configuration vector information, and determining that data transmitted through a temporary circuit with route locking is the communication data;
and under the condition that the preset bit of the routing packet to be transmitted is second information, characterizing that the routing packet carries address information and configuration vector information, and determining that the routing packet comprises the configuration vector information.
According to the hybrid circuit transmission and packet transmission method provided by the invention, the preset bit is the packet classification bit of the routing packet to be transmitted.
According to the present invention, there is provided a hybrid circuit transmission and packet transmission method, the transmission of configuration vector information through each of the first transverse transmission paths and each of the longitudinal transmission paths, comprising:
And transmitting the configuration vector information through each first transverse transmission path and each longitudinal transmission path by adopting a transmission mode of send-and-forward.
The invention also provides a hybrid circuit transmission and packet transmission system, which is applied to a network on chip (NoC) circuit, wherein the NoC circuit comprises M x N NoC nodes, M, N are integers larger than 1, M rows of NoC nodes form M transverse transmission paths, N columns of NoC nodes form N longitudinal transmission paths, at least one first transverse transmission path in the M transverse transmission paths and each longitudinal transmission path support operation configuration vector transmission based on packet transmission, and other second transverse transmission paths in the M transverse transmission paths support data transmission of a temporary locking circuit established based on routing;
The system comprises:
A packet transmission module for transmitting configuration vector information through each of the first transverse transmission paths and each of the longitudinal transmission paths; the configuration vector information is used for configuring at least one operation of the function module on the target node of the route end point;
and the circuit transmission module is used for forming a temporary locking circuit based on the second transverse transmission path established by the route and transmitting communication data through the temporary locking circuit.
The invention also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the hybrid circuit transmission and packet transmission method as described in any of the above when executing the program.
The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a hybrid circuit transmission and packet transmission method as described in any of the above.
The invention also provides a computer program product comprising a computer program which when executed by a processor implements a hybrid circuit transmission and packet transmission method as described in any one of the above.
The invention provides a hybrid circuit transmission and packet transmission method and a system, which are applied to a NoC circuit, wherein the NoC circuit comprises M x N NoC nodes, M rows of NoC nodes form M transverse transmission paths, N columns of NoC nodes form N longitudinal transmission paths, and at least one first transverse transmission path in the M transverse transmission paths and a longitudinal transmission path are arranged to support operation configuration vector transmission of packet transmission; the other second transverse transmission paths are mainly used for establishing transmission paths through routing packets to form a temporary locking circuit, so that large-block communication data can be transmitted through the temporary locking circuit, each first transverse transmission path and each longitudinal transmission path are supported for packet transmission, and configuration vector information of small blocks of at least one operation can be transmitted through each first transverse transmission path and/or each longitudinal transmission path to a functional module connected to a target NoC node at a routing end point, so that operation configuration and the like can be carried out on the functional modules connected to each NoC node. The embodiment of the invention mainly transmits the regular large-block data through a path mainly used for transverse transmission, and mainly transmits the small-block operation configuration vector which does not need to be split and transmitted through a path mainly used for longitudinal transmission, thereby eliminating storage for reordering and reducing silicon overhead; the method reduces the data transmission delay and improves the flexibility of configuration vector information transmission, and when the second transverse transmission path is used for forming a temporary locking circuit for transmission, the transmission of longitudinal configuration vector information is not influenced, the data size of the longitudinal configuration vector information is small, the transmission does not need to form a temporary locking circuit specially, the transmission can be directly carried out through a packet, the resources occupied by the temporary locking circuit can be effectively reduced, the transverse transmission and the longitudinal transmission can be operated in parallel, the silicon overhead and the transmission time delay are effectively reduced, the instantaneity of a NoC circuit is improved, and the method is applicable to various processing systems facing real-time flows.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a hybrid circuit transmission and packet transmission method provided by the invention;
FIG. 2 is a schematic diagram of a NoC circuit in a hybrid circuit transmission and packet transmission method provided by the present invention;
FIG. 3 is a schematic diagram of a NoC node circuit in a hybrid circuit transmission and packet transmission method according to the present invention;
fig. 4 is a schematic structural diagram of a hybrid circuit transmission and packet transmission system provided by the present invention;
Fig. 5 is a schematic structural diagram of an electronic device provided by the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The hybrid circuit transmission and packet transmission method and system of the present invention are described below with reference to the accompanying drawings.
The hybrid circuit transmission and packet transmission method of the embodiment of the invention is mainly applied to a network on chip (NetworkOnChip, noC) circuit, wherein the NoC circuit comprises M x N NoC nodes, M, N is an integer larger than 1, M rows of NoC nodes form M transverse transmission paths, N columns of NoC nodes form N longitudinal transmission paths, at least one first transverse transmission path in the M transverse transmission paths and each longitudinal transmission path support the transmission of an operation configuration vector based on packet transmission, and other second transverse transmission paths in the M transverse transmission paths support the data transmission of a temporary locking circuit based on route establishment;
Fig. 1 is a flow chart of a hybrid circuit transmission and packet transmission method provided by the present invention, as shown in fig. 1, the method includes steps 101 and 102; wherein:
step 101, transmitting configuration vector information through each first transverse transmission path and each longitudinal transmission path; the configuration vector information is used for configuring at least one operation of the function module on the target node of the route end point.
And 102, forming a temporary locking circuit based on the second transverse transmission path established by the route, and transmitting communication data through the temporary locking circuit.
It should be noted that, the embodiment of the present invention does not limit the sequence of executing the above steps 101 and 102, that is, the configuration vector information may be transmitted to the functional module located on the destination node of the route destination through each first lateral transmission path and each longitudinal transmission path, at least one operation of the functional module may be configured, and then a temporary locking circuit may be formed based on the second lateral transmission path established by the route, so as to transmit the communication data through the temporary locking circuit, or the temporary locking circuit may be formed based on the second lateral transmission path, so as to transmit the communication data through the temporary locking circuit, and then the configuration vector information may be transmitted to the functional module located on the destination node of the route destination through each first lateral transmission path and each longitudinal transmission path, and the above two steps may be simultaneously executed, which is not limited herein.
In the related art, data is transmitted through a circuit with route locking, which is only suitable for large data with a relatively regular rule, but not suitable for small data, the flexibility of data transmission is poor, the transmission efficiency is low, and in addition, for a system facing real-time stream processing, such as real-time application of communication baseband, communication route, radar, game, video, artificial intelligent training, artificial intelligent reasoning and the like, the time delay of data transmission of packet switching is relatively large, and the system requirement is difficult to meet.
In order to solve the problems, the embodiment of the invention mixes circuit transmission and packet transmission, uses a temporary circuit established by a route to transmit large-block data and adds the route data transmission aiming at small-block configuration data. The transmission efficiency of the large-block data is guaranteed, the hardware overhead of data reordering is reduced, and meanwhile, the transmission efficiency and flexibility of the small-block data are guaranteed.
The method of the embodiment of the invention is applied to a NoC circuit, the NoC circuit comprises M x N NoC nodes, M rows of NoC nodes form M transverse transmission paths, and N columns of NoC nodes form N longitudinal transmission paths. Each NoC node supports short packet exchanges and circuit exchanges via a temporary lock circuit.
At least one first transverse transmission path and each longitudinal transmission path of the M transverse transmission paths are set to support operation configuration vector transmission based on packet transmission, configuration vector information of small blocks can be transmitted to each NoC node through a combined path formed by the first transverse transmission path and each longitudinal transmission path by using a data packet so as to perform operation configuration and the like on the functional modules corresponding to each NoC node, and configuration of at least one operation can be performed on the functional modules.
Specifically, each of the first lateral transmission paths is not mainly configured to support temporary lock circuit transmission, and it can be understood that the first lateral transmission paths are mainly configured to laterally transmit configuration vector information to transmit the configuration vector information to a certain column.
Alternatively, each of the first lateral transmission paths may be configured at the top of a logic circuit or a functional flow diagram of the NoC, and job configuration may be performed by a plurality of job configuration sources, MCUs, or job management hardware.
The other second transverse transmission paths among the M transverse transmission paths support data transmission of the temporary locking circuit established based on the route, and the temporary locking circuit may be formed based on such second transverse transmission paths as a main basis, and thus large blocks of communication data may be transmitted through the temporary locking circuit.
The second transverse transmission path is used as a main support for circuit transmission, which can be understood as the transmission of a circuit established according to a routing packet, and is a circuit with a route lock, i.e. a temporary lock circuit can be formed based on the second transverse transmission path as a main support, and then the temporary lock circuit is used for data transmission.
The functional module and the memory module in the NoC circuit can be configured by a certain job, and can send an execution state report to a job configuration source.
Optionally, the implementation manner of transmitting the configuration vector information through each of the first transverse transmission paths and each of the longitudinal transmission paths may include:
and transmitting the configuration vector information through each first transverse transmission path and each longitudinal transmission path by adopting a transmission mode of send-and-forward (send-and-forward).
Specifically, the first transverse transmission path and the longitudinal transmission path support the transmission of the operation configuration vector based on the packet transmission, which can be understood as the routing of the unlocking circuit, the short data (operation configuration vector and operation execution state) can be carried by the header of the routing packet without adopting the circuit transmission, the packet exchange is adopted, and the data transmission is completed simultaneously with the completion of the routing, and the transmission mode of send-and-form can be adopted by the routing unlocking circuit.
In the hybrid circuit transmission and packet transmission method provided by the embodiment of the invention, for relatively regular large-block data, the transmission is mainly performed through a transverse transmission path, and for small-block operation configuration vectors which do not need to be split and transmitted, the transmission is mainly performed through a longitudinal transmission path, so that storage for reordering is eliminated, and silicon overhead is reduced; the method reduces the data transmission delay and improves the flexibility of configuration vector information transmission, and when a second transverse transmission path is used for forming a temporary locking circuit for transmission, the transmission of longitudinal configuration vector information is not affected, the data size of the longitudinal configuration vector information is small, the transmission does not need to form a special temporary locking circuit, the transmission can be directly carried out through a packet, the resources occupied by the formation of the temporary locking circuit are effectively reduced, the transverse transmission and the longitudinal transmission can be operated in parallel, the silicon overhead and the transmission delay are effectively reduced, the instantaneity of a NoC circuit is improved, and the method is applicable to various processing systems facing real-time streams.
Optionally, the implementation manner of transmitting the configuration vector information through each of the first transverse transmission paths and each of the longitudinal transmission paths may include:
Acquiring a source node and a target node corresponding to configuration vector information to be transmitted;
Determining a target transmission path corresponding to the configuration vector information to be transmitted based on the source node, the target node, each first transverse transmission path and each longitudinal transmission path;
according to the target transmission path, based on packet exchange, the configuration vector information to be transmitted is packed, transmitted to the target node by the source node through packet exchange, and transmitted to a corresponding target functional module through the target node to serve as one-time configuration of at least one job running on the target functional module.
Optionally, the determining, based on the source node, the target node, each of the first transverse transmission paths, and each of the longitudinal transmission paths, an implementation manner of the target transmission path corresponding to the configuration vector information to be transmitted may include:
determining an intersecting node where a first transverse transmission path where the source node is located intersects with a longitudinal transmission path where the target node is located, and taking the first transmission path from the source node to the intersecting node and the second transmission path from the intersecting node to the target node as the target transmission paths.
Optionally, the implementation manner of transmitting the configuration vector information to be transmitted from the source node to the target node according to the target transmission path may include:
And transmitting the configuration vector information to be transmitted from the source node to the intersection node through the first transmission path, and transmitting the configuration vector information to be transmitted from the intersection node to the target node through the second transmission path.
Specifically, a target transmission path for transmitting configuration vector information can be determined based on a source node, a target node, each first transverse transmission path and each longitudinal transmission path, specifically, the first transverse transmission path where the source node is located and the longitudinal transmission path where the target node is located are determined first, then the intersecting node where the two paths intersect is determined, further, the first transmission path from the source node to the intersecting node and the second transmission path from the intersecting node to the target node can be determined as target transmission paths, the configuration vector information to be transmitted is transmitted from the source node to the intersecting node through the first transmission path, and then the configuration vector information to be transmitted is transmitted from the intersecting node to the target node through the second transmission path, so that the configuration vector information is transmitted from the source node to the target node.
Specifically, since the row (transverse) transmission path of the NoC node in the NoC circuit may be locked as a temporary locking circuit, the configuration packet may be transmitted mainly by a column (longitudinal) transmission path, so as to ensure that each configuration can arrive in time, after the configuration packet is sent out, the configuration packet may first find and arrive at the column where the target node is located according to a routing algorithm, and then reach the target node by routing downward along the column. Thus, rows of packet switching nodes may be configured in the vicinity of the configurator/controller to ensure reachability of each column configuration.
In some embodiments, multiple configurators/controllers may send configuration vector information to each functional module (or storage module) of each job flow in parallel.
Optionally, each NoC node may support short packet exchange and circuit exchange via a temporary route locking circuit, and in the case that a preset bit of a to-be-transmitted route packet is first information, characterize that the route packet only carries address information, does not carry configuration vector information, and determine that data transmitted through the temporary route locked circuit is the communication data;
and under the condition that the preset bit of the routing packet to be transmitted is second information, characterizing that the routing packet carries address information and configuration vector information, and determining that the routing packet comprises the configuration vector information.
Alternatively, the preset bit may be a packet classification bit of the routing packet to be transmitted.
Specifically, regarding the routing packet format, a packet classification bit function switch of a routing packet to be transmitted may be set, and the function is defined as:
1) First bit = 0; the lock is routed as a temporary circuit.
2) First bit = 1; and the route is not locked, and the message carried by the packet is transmitted to the destination node.
Note that, regarding the routing protocol, the protocol that does not lock the route does not include a function of locking the route.
After error checking, the target node may send a status data packet (non-lock packet) to report an error or report success of the packet.
Regarding the timeout, a timeout check may be set at the packet-issuing node (source node). The retransmission is a timeout. And after the retransmission times exceed the limit, the system reports errors.
The hybrid circuit transmission and packet transmission methods provided by the embodiments of the present invention are illustrated below.
Fig. 2 is a schematic structural diagram of a NoC circuit in the hybrid circuit transmission and packet transmission method provided in the present invention, as shown in fig. 2, which is a NoC circuit structure of a system on a physical layer of a small base station, wherein (12) is an inter-node connection, (13) is an interface connection, and (15) is a connection jacket of a local module.
The NoC circuit is specifically described below by way of one example of a base station:
1) Two sectors (cells) are supported, five of which are shown in fig. 2 as thick and transversal lines, which can be understood as allocations: two upstream fan channels are arranged, two downstream fan channels are arranged, and the rest one is arranged.
2) The DFE in the figure is a group of digital front-end transceiver modules.
3) The ping-pong cache of the Shared memory (Shared memory) storage group in the figure exchanges data between DFE and Baseband (Baseband) in real time.
4) The upper two rows of (transverse) thin lines (18) can ensure the flexible and controllable of the micro control unit (Micro Controller Unit, MCU) to the DFE and baseband routing; other column (vertical) thin lines ensure the accessibility of each module's configuration and execution report.
5) Column (longitudinal) bold lines (16) ensure reachability and flexibility for each row route; row (lateral) bold lines ensure lockable data-path temporary circuits.
6) The thick lines are planned to be temporary locked as paths for the circuit, it being noted that these paths may also support unlocked packet switched routing.
7) The thin line is intended primarily to support unlocked packet switched routing. It should be noted that these paths may also be locked as temporary circuits.
In addition, the plurality of memories of the memory area are arranged in a plurality of rows and a plurality of columns (16), and are firstly routed to a row where the node of the computing function module is located through a plurality of thick line nodes of the plurality of rows and the plurality of columns; the row is locked and circuit-based transfers are completed.
The long data transmitted by the locking circuit serves the data input and output of the functional computing units in the NoC circuit, circuitry is established between the storage and computing units, the respective computing units are ordered according to a common computational sequence, the respective computing units are ordered according to a computational flow, wherein each row performs one data stream processing, and then multiple rows of data stream processing hardware are programmed to perform parallel operations of multiple processing streams (e.g., (17)).
The multiple configurators/controllers may send configuration vector information (18, 19) in parallel to each functional module (or memory module) of each job flow.
For NoC nodes in a NoC circuit, a connection jacket (wrapper) of each routing node supports two functions of a route locking circuit and a route unlocking circuit, and the specific circuit structure is as follows:
fig. 3 is a schematic structural diagram of a NoC node circuit in the hybrid circuit transmission and packet transmission method provided by the present invention, and as shown in fig. 3, the NoC node circuit includes: a data path (21) and a control path (22). Wherein:
a. (21) Is an ingress circuit reconfiguration design circuit (20);
for an ingress circuit reconfiguration design circuit (20), it is determined which of the following is satisfied by the routing packet:
1) Locking circuit: a protocol of the route lock circuit is performed.
2) Carry data, unlock circuit: a protocol for packet-switched delivery of data is performed.
B. (21) Is an egress circuit reconfiguration design circuit (29);
for an egress circuit reconfiguration design circuit (29), it is determined which of the following is satisfied by the routing packet:
1) Locking circuit: the route path is temporarily locked, and locking or releasing is performed after the final route is waited.
2) Carry data, unlock circuit: after the packet is sent out, the previous operation is forgotten.
C. (21) Is the ingress and egress of the route;
d. (22) The first circuit function of (a) is a packing function for the source routing node;
e. (22) The second circuit function of (a) is to route the reception and unpacking parsing of packets for the intermediate node and the target routing node;
f. (22) The third circuit function of (a) is to determine the egress route and transmit route packets for the source route node and the intermediate node;
g. (22) Is a watchdog of the source routing node;
h. (22) The fifth circuit function of (a) is to complete data receiving (including cyclic redundancy check (Cyclic Redundancy Check, CRC) check) sending and controlling (the source routing node can be the receiving end or the sending end of the data) for the source routing node;
i. (22) The sixth circuit function of (a) is to complete data receiving (including CRC check) sending and controlling for the target routing node (the target routing node can be a receiving end or a sending end of the data);
j. (22) Is to keep track of the occupancy status of the update neighboring nodes.
Wherein (24) introducing four-way input of (21) into a connection jacket controller (22) to implement routing, and (25) sending a routing decision to (21) to implement outlet selection, a wiring (26) circuit connecting the jacket to the module: and executing the reconfiguration of the module inlet circuit, determining the configuration of the connection module inlet circuit and the connection protocol according to the input line of the connected module in the circuit design stage, and sending the data subjected to the reconfiguration into the module.
Wiring (27) circuitry of the connected module to the connection housing: performing a module exit circuit reconfiguration configuration: in the circuit design stage, the configuration of the outlet circuit and the connection protocol of the connected module is determined according to the output line of the connected module, and data is output to the connection jacket.
(28) The control and status information interaction for connecting the outer sleeve and the connected module at least comprises the establishment path requirement supporting the source route, data basic information, timeout, error report and the like; and data base information (including broadcast and multicast), time-out, and error reporting, etc. supporting the target route.
The two main functions performed by the connecting sleeve are in particular:
The first function is to establish a circuit connection through a route: and establishing, locking and withdrawing the route connection. This function is dynamic, once per transmission. (22) According to the data transmission requirement of the source route local module initiating device, a route packet is compiled to finish:
1. (22) the node keeps track of occupancy status of neighboring nodes;
2. Adding header content and recording paths according to the address of a target routing node of a route and the occupation condition of adjacent nodes, temporarily locking the input and output paths of the node in two directions, and sending a routing packet to the determined direction;
3. According to the routing method, a local module of the target routing node is finally found, and a circuit is established to connect the local module of the source routing node and the local module of the target routing node;
4. The local module of the target routing node confirms the transmission request, if the local module is idle, a command of returning to the locking circuit is sent out; if not, a busy state is sent out;
5. locking circuit: establishing a directional locked circuit connection;
6. Maintaining a locked state, supporting bus transmission;
7. And (3) locking is withdrawn: after the transmission is finished, the data receiving side sends out a request for canceling the circuit locking, the source routing node executes a command for canceling the circuit, all nodes along the line cancel the locking, and circuit resources are released;
8. The transmission application node is provided with overtime control, and the abnormal overtime transmission is terminated and reported to the system.
The second function is to transmit data using circuitry: after the circuit is locked, data transmission over the circuit is started. The source routing node or the target routing node can send data, the sent data is enabled to be effective by the enabling bit, the enabling bit disappears after the sending is finished, the data receiving party makes a data receiving report according to the CRC check result, the source routing node receives the report and immediately unlocks the circuit, and circuit resources are released.
Connected module M (23): may be a processor, a functional module, a memory, and an interface module. The input connections to the connected module M (23) may include:
1) A processor: a data storage write bus and a program/configuration memory coupled to the input to the processor;
2) Functional module: connecting a data storage write bus and a configuration register which are input to the functional module;
3) A memory: connecting a write port input to the data memory, a node internal direct memory access (DirectMemory Access, DMA) providing an address;
4) An interface: the connection is input to the interface, and the DMA inside the node provides subsequent data transmission.
The output connections to the connected module M (23) may include:
1> processor: the data storage readout bus of the processor is connected to the output;
2> functional module: the read bus of the data storage of the module is connected to the output;
3> memory: the readout of the data memory is connected to the output through the node internal DMA;
4> interface: the interface is directly connected to the output.
The various pins of the NoC node circuit of fig. 3 are described below:
the connecting lines are divided into four directions and eight groups of connecting lines; the method comprises the following steps of:
1) Nin: north port input lines (connectable to south port output, east port output, west port output, and local (C) input);
2) Nout: north port output lines (from south port input, east port input, west port input, and local (C) output);
3) Sin: a south port input line (connectable to north port output, east port output, west port output, and local (C) input);
4) Sout: southbound output lines (from northbound input, eastbound input, westbound input, and local (C) output);
5) Ein: east input line (connectable to north output, south output, west output, and local (C) input);
6) Eout: east output line (from north input, south input, west input, and local (C) output);
7) Win: west port input line (connectable to north port output, south port output, east port output, and local (C) input);
8) Wout: west port output lines (from north port input, south port input, east port input, and local (C) output);
wherein clock is the clock signal input.
Regarding performance and overhead, in the embodiment of the invention, a circuit can not be locked, the simulation operation configuration short packet does not affect performance because of the locked circuit, and short data packets frequently appear in actual transmission, if a protocol for locking a temporary circuit is adopted, the network occupancy rate is too large, and the performance is low. The invention also adopts short packet switching, short packets have no extra cost of receiving end reordering, the occupied probability of the locking network is low, the locking network is occupied only when transmitting packets, each node is send-and-forward, and the whole routing resource is not occupied.
For silicon overhead, because the packets are very short, one packet carries one complete data packet, no data block exists, no reordering overhead of the offload engine (offload engine) exists, long data circuit switching avoids reordering, and short data packet switching ensures network efficiency. The silicon overhead in the transmission of the present invention is therefore small.
The embodiment of the invention establishes a mixed network-on-chip which supports circuit transmission (transmission of a circuit established according to a routing packet) and packet transmission (transmission of data carried by the routing packet), and utilizes the mixed circuit transmission and packet transmission method to transmit, thereby reducing silicon overhead, having good instantaneity and meeting the requirement of a real-time stream processing system on time delay.
The hybrid transmission and packet transmission system provided by the present invention will be described below, and the hybrid transmission and packet transmission system described below and the hybrid transmission and packet transmission method described above may be referred to correspondingly to each other.
The hybrid circuit transmission and packet transmission system is applied to a network on chip NoC circuit, the NoC circuit comprises m×n NoC nodes, M, N are integers larger than 1, M rows of NoC nodes form M transverse transmission paths, N columns of NoC nodes form N longitudinal transmission paths, at least one first transverse transmission path of the M transverse transmission paths and each longitudinal transmission path are set to support packet transmission-based operation configuration vector transmission, and other second transverse transmission paths of the M transverse transmission paths support data transmission of a temporary locking circuit established based on routing.
Fig. 4 is a schematic structural diagram of a hybrid circuit transmission and packet transmission system according to the present invention, and as shown in fig. 4, a hybrid circuit transmission and packet transmission 400 includes:
a packet transmission module 401, which is a type of function of each NoC node, for transmitting configuration vector information through each of the first transverse transmission paths and each of the longitudinal transmission paths; the configuration vector information is used for configuring at least one operation of the function module on the target node of the route end point;
The circuit transmission module 402 is another type of function of each NoC node, and is configured to form a temporary lock circuit based on the second lateral transmission path established by the route, and transmit communication data through the temporary lock circuit.
In the hybrid circuit transmission and packet transmission system provided by the embodiment of the invention, the hybrid circuit transmission and packet transmission system is applied to a NoC circuit, the NoC circuit comprises M x N NoC nodes, M rows of NoC nodes form M transverse transmission paths, N columns of NoC nodes form N longitudinal transmission paths, wherein at least one first transverse transmission path and longitudinal transmission path in the M transverse transmission paths are set to support the transmission of an operation configuration vector of packet transmission; the other second transverse transmission paths can establish transmission paths through the routing packets to form a temporary locking circuit, so that large-block communication data is transmitted through the temporary locking circuit, the first transverse transmission paths and the longitudinal transmission paths are mainly used for packet transmission, and configuration vector information of small blocks of at least one operation can be transmitted through the first transverse transmission paths and/or the longitudinal transmission paths to function modules connected to target NoC nodes at the routing end points, so that operation configuration and the like can be carried out on the function modules connected to the NoC nodes. The embodiment of the invention mainly transmits the regular large-block data through the transverse transmission path, and mainly transmits the small-block operation configuration vector which does not need to be split and transmitted through the longitudinal transmission path, thereby eliminating the storage for reordering and reducing the silicon cost; the method reduces the data transmission delay and improves the flexibility of configuration vector information transmission, and when the second transverse transmission path is used for forming a temporary locking circuit for transmission, the transmission of longitudinal configuration vector information is not influenced, the data size of the longitudinal configuration vector information is small, the transmission does not need to form a temporary locking circuit specially, the transmission can be directly carried out through a packet, the resources occupied by the temporary locking circuit can be effectively reduced, the transverse transmission and the longitudinal transmission can be operated in parallel, the silicon overhead and the transmission time delay are effectively reduced, the instantaneity of a NoC circuit is improved, and the method is applicable to various processing systems facing real-time flows.
Optionally, the packet transmission module 401 is specifically configured to:
Acquiring a source node and a target node corresponding to configuration vector information to be transmitted;
Determining a target transmission path corresponding to the configuration vector information to be transmitted based on the source node, the target node, each first transverse transmission path and each longitudinal transmission path;
and according to the target transmission path, packing the configuration vector information to be transmitted, transmitting the configuration vector information to be transmitted to the target node by the source node, and transmitting the configuration vector information to be transmitted to a corresponding target functional module through the target node to serve as one-time configuration of at least one job running on the target functional module.
Optionally, the packet transmission module 401 is further specifically configured to:
determining an intersecting node where a first transverse transmission path where the source node is located intersects with a longitudinal transmission path where the target node is located, and taking the first transmission path from the source node to the intersecting node and the second transmission path from the intersecting node to the target node as the target transmission paths.
Optionally, the packet transmission module 401 is further specifically configured to:
And transmitting the configuration vector information to be transmitted from the source node to the intersection node through the first transmission path, and transmitting the configuration vector information to be transmitted from the intersection node to the target node through the second transmission path.
Optionally, each NoC node supports short packet switching and circuit switching via a temporary lock circuit, and the hybrid circuit transmission and packet transmission system 400 further includes:
a processing module for:
Under the condition that a preset bit of a routing packet to be transmitted is first information, characterizing that the routing packet only carries address information and does not carry configuration vector information, and determining that data transmitted through a temporary circuit with route locking is the communication data;
and under the condition that the preset bit of the routing packet to be transmitted is second information, characterizing that the routing packet carries address information and configuration vector information, and determining that the routing packet comprises the configuration vector information.
Optionally, the preset bit is a packet classification bit of the routing packet to be transmitted.
Optionally, the packet transmission module 401 is further specifically configured to:
And transmitting the configuration vector information through each first transverse transmission path and each longitudinal transmission path by adopting a transmission mode of send-and-forward.
Fig. 5 is a schematic structural diagram of an electronic device according to the present invention, and as shown in fig. 5, the electronic device may include: processor 510, communication interface (Communications Interface) 520, memory 530, and communication bus 540, wherein processor 510, communication interface 520, memory 530 complete communication with each other through communication bus 540. The processor 510 may invoke logic instructions in the memory 530 to perform a hybrid circuit transmission and packet transmission method, applied to a network on chip NoC circuit, where the NoC circuit includes m×n NoC nodes, M, N are integers greater than 1, M rows of NoC nodes form M transverse transmission paths, N columns of NoC nodes form N longitudinal transmission paths, at least one first transverse transmission path of the M transverse transmission paths and each longitudinal transmission path support packet transmission-based job configuration vector transmission, and other second transverse transmission paths of the M transverse transmission paths support data transmission of a temporary lock circuit established based on a route; the method comprises the following steps:
Transmitting configuration vector information through each of the first transverse transmission paths and each of the longitudinal transmission paths; the configuration vector information is used for configuring at least one operation of the function module on the target node of the route end point;
And forming a temporary locking circuit based on the second transverse transmission path established by the route, and transmitting communication data through the temporary locking circuit.
Further, the logic instructions in the memory 530 described above may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In another aspect, the present invention further provides a computer program product, where the computer program product includes a computer program, where the computer program is stored on a non-transitory computer readable storage medium, where the computer program, when executed by a processor, is capable of executing the hybrid circuit transmission and packet transmission methods provided by the foregoing methods, and is applied to a network on chip NoC circuit, where the NoC circuit includes m×n NoC nodes, M, N are integers greater than 1, the M-row NoC nodes form M lateral transmission paths, the N-column NoC nodes form N longitudinal transmission paths, where at least one first lateral transmission path of the M lateral transmission paths and each longitudinal transmission path support transmission of a job configuration vector based on packet transmission, and where other second lateral transmission paths of the M lateral transmission paths support data transmission of a temporary lock circuit established based on routing; the method comprises the following steps:
Transmitting configuration vector information through each of the first transverse transmission paths and each of the longitudinal transmission paths; the configuration vector information is used for configuring at least one operation of the function module on the target node of the route end point;
And forming a temporary locking circuit based on the second transverse transmission path established by the route, and transmitting communication data through the temporary locking circuit.
In still another aspect, the present invention further provides a non-transitory computer readable storage medium, on which a computer program is stored, the computer program being implemented when executed by a processor to perform the hybrid circuit transmission and packet transmission methods provided by the above methods, applied to a network on chip NoC circuit, where the NoC circuit includes m×n NoC nodes, M, N being integers greater than 1, the M rows of NoC nodes forming M lateral transmission paths, the N columns of NoC nodes forming N longitudinal transmission paths, at least one first lateral transmission path of the M lateral transmission paths and each of the longitudinal transmission paths being set to support packet transmission-based job configuration vector transmission, and other second lateral transmission paths of the M lateral transmission paths being set to support data transmission of a temporary lock circuit established based on routing; the method comprises the following steps:
Transmitting configuration vector information through each of the first transverse transmission paths and each of the longitudinal transmission paths; the configuration vector information is used for configuring at least one operation of the function module on the target node of the route end point;
And forming a temporary locking circuit based on the second transverse transmission path established by the route, and transmitting communication data through the temporary locking circuit.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A hybrid circuit transmission and packet transmission method, characterized in that it is applied to a network on chip NoC circuit, where the NoC circuit includes m×n NoC nodes, M, N are integers greater than 1, M rows of NoC nodes form M lateral transmission paths, N columns of NoC nodes form N longitudinal transmission paths, at least one first lateral transmission path of the M lateral transmission paths and each longitudinal transmission path support packet transmission-based job configuration vector transmission, and other second lateral transmission paths of the M lateral transmission paths support data transmission of a temporary locking circuit established based on routing;
The method comprises the following steps:
Transmitting configuration vector information through each of the first transverse transmission paths and each of the longitudinal transmission paths; the configuration vector information is used for configuring at least one operation of the function module on the target node of the route end point;
And forming a temporary locking circuit based on the second transverse transmission path established by the route, and transmitting communication data through the temporary locking circuit.
2. The hybrid circuit transmission and packet transmission method according to claim 1, wherein the transmitting the configuration vector information through each of the first transverse transmission paths and each of the longitudinal transmission paths includes:
Acquiring a source node and a target node corresponding to configuration vector information to be transmitted;
Determining a target transmission path corresponding to the configuration vector information to be transmitted based on the source node, the target node, each first transverse transmission path and each longitudinal transmission path;
And transmitting the configuration vector information to be transmitted to the target node from the source node according to the target transmission path, and transmitting the configuration vector information to be transmitted to a corresponding target functional module through the target node to serve as one-time configuration of at least one job running on the target functional module.
3. The hybrid circuit transmission and packet transmission method according to claim 2, wherein the determining a target transmission path corresponding to the configuration vector information to be transmitted based on the source node, the target node, each of the first lateral transmission paths, and each of the longitudinal transmission paths includes:
determining an intersecting node where a first transverse transmission path where the source node is located intersects with a longitudinal transmission path where the target node is located, and taking the first transmission path from the source node to the intersecting node and the second transmission path from the intersecting node to the target node as the target transmission paths.
4. The hybrid circuit transmission and packet transmission method according to claim 3, wherein said transmitting the configuration vector information to be transmitted from the source node to the target node according to the target transmission path includes:
And transmitting the configuration vector information to be transmitted from the source node to the intersection node through the first transmission path, and transmitting the configuration vector information to be transmitted from the intersection node to the target node through the second transmission path.
5. The hybrid circuit transmission and packet transmission method of any one of claims 1 to 4, wherein each NoC node supports short packet switching and circuit switching via a temporary lock circuit, the method further comprising:
Under the condition that a preset bit of a routing packet to be transmitted is first information, characterizing that the routing packet only carries address information and does not carry configuration vector information, and determining that data transmitted through a temporary circuit with route locking is the communication data;
and under the condition that the preset bit of the routing packet to be transmitted is second information, characterizing that the routing packet carries address information and configuration vector information, and determining that the routing packet comprises the configuration vector information.
6. The hybrid circuit transmission and packet transmission method according to claim 5, wherein the preset bits are packet classification bits of the routing packet to be transmitted.
7. The hybrid circuit transmission and packet transmission method according to any one of claims 1 to 4, wherein the transmission of the configuration vector information through each of the first transverse transmission paths and each of the longitudinal transmission paths includes:
And transmitting the configuration vector information through each first transverse transmission path and each longitudinal transmission path by adopting a transmission mode of send-and-forward.
8. A hybrid circuit transmission and packet transmission system, characterized in that it is applied to a network on chip NoC circuit, where the NoC circuit includes m×n NoC nodes, M, N are integers greater than 1, M rows of NoC nodes form M lateral transmission paths, N columns of NoC nodes form N longitudinal transmission paths, at least one first lateral transmission path of the M lateral transmission paths and each longitudinal transmission path are set to support transmission of an operation configuration vector based on packet transmission, and other second lateral transmission paths of the M lateral transmission paths support data transmission of a temporary locking circuit based on route establishment;
The system comprises:
A packet transmission module for transmitting configuration vector information through each of the first transverse transmission paths and each of the longitudinal transmission paths; the configuration vector information is used for configuring at least one operation of the function module on the target node of the route end point;
and the circuit transmission module is used for forming a temporary locking circuit based on the second transverse transmission path established by the route and transmitting communication data through the temporary locking circuit.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the hybrid circuit transmission and packet transmission method according to any one of claims 1 to 7 when executing the program.
10. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the hybrid circuit transmission and packet transmission method of any of claims 1 to 7.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101778049A (en) * | 2010-03-04 | 2010-07-14 | 南京大学 | Router and transmission method thereof on packet-circuit switching chip |
| CN102904807A (en) * | 2012-10-10 | 2013-01-30 | 清华大学 | A method for implementing fault-tolerant reconfigurable network-on-chip through data segmentation and transmission |
| WO2022193183A1 (en) * | 2021-03-17 | 2022-09-22 | 北京希姆计算科技有限公司 | Network-on-chip simulation model generation method and apparatus, electronic device, and computer-readable storage medium |
| CN115883447A (en) * | 2023-02-06 | 2023-03-31 | 极芯通讯技术(南京)有限公司 | Temporary on-circuit data transmission method and system established based on packet routing |
| CN115987918A (en) * | 2023-02-06 | 2023-04-18 | 极芯通讯技术(南京)有限公司 | Method and system for establishing temporary circuit based on packet switching routing |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3118528B1 (en) * | 2020-12-28 | 2023-12-01 | Commissariat Energie Atomique | Memory module suitable for implementing calculation functions |
-
2024
- 2024-02-04 CN CN202410156624.6A patent/CN117714388B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101778049A (en) * | 2010-03-04 | 2010-07-14 | 南京大学 | Router and transmission method thereof on packet-circuit switching chip |
| CN102904807A (en) * | 2012-10-10 | 2013-01-30 | 清华大学 | A method for implementing fault-tolerant reconfigurable network-on-chip through data segmentation and transmission |
| WO2022193183A1 (en) * | 2021-03-17 | 2022-09-22 | 北京希姆计算科技有限公司 | Network-on-chip simulation model generation method and apparatus, electronic device, and computer-readable storage medium |
| CN115883447A (en) * | 2023-02-06 | 2023-03-31 | 极芯通讯技术(南京)有限公司 | Temporary on-circuit data transmission method and system established based on packet routing |
| CN115987918A (en) * | 2023-02-06 | 2023-04-18 | 极芯通讯技术(南京)有限公司 | Method and system for establishing temporary circuit based on packet switching routing |
Non-Patent Citations (2)
| Title |
|---|
| 基于SRAM的软硬件协同转置存储器设计与实现;郑艳丽;李丽;潘红兵;李伟;沙金;;微电子学;20131220(第06期);全文 * |
| 基于包交换技术的可重构片上网络混合路由器设计;苑乔;张华健;朱进宇;闫峥;宋宇鲲;刘学毅;;微电子学与计算机;20200305(第03期);全文 * |
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