CN117713870B - Multi-antenna radio frequency transceiver switch circuit and radio frequency chip - Google Patents
Multi-antenna radio frequency transceiver switch circuit and radio frequency chip Download PDFInfo
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- CN117713870B CN117713870B CN202410166511.4A CN202410166511A CN117713870B CN 117713870 B CN117713870 B CN 117713870B CN 202410166511 A CN202410166511 A CN 202410166511A CN 117713870 B CN117713870 B CN 117713870B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/401—Circuits for selecting or indicating operating mode
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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Abstract
The invention relates to the technical field of wireless communication and discloses a multi-antenna radio frequency receiving and transmitting switch circuit and a radio frequency chip, wherein the multi-antenna radio frequency receiving and transmitting switch circuit comprises an antenna port, a receiving and transmitting matching module, a switch module and a radio frequency port which are electrically connected in sequence; the antenna ports comprise at least 3, the receiving and transmitting matching modules comprise at least 3, the switch module comprises at least one, the input end of each receiving and transmitting matching module is correspondingly connected to the antenna port respectively, and the output end of each receiving and transmitting matching module is connected with the input end of the switch module; each receiving and transmitting matching module comprises a first inductor and a first capacitor, wherein the first end of the first inductor is connected with the first end of the first capacitor and is used as an input end of the receiving and transmitting matching module, the second end of the first capacitor is grounded, and the second end of the first inductor is used as an output end of the receiving and transmitting matching module. The multi-antenna radio frequency receiving and transmitting switch circuit has the effects of high integration level, strong anti-interference capability, insertion loss reduction and harmonic suppression on a transmitting carrier wave.
Description
Technical Field
The present invention relates to the field of wireless communications technologies, and in particular, to a multi-antenna radio frequency transceiver switch circuit and a radio frequency chip.
Background
In the field of wireless communication, radio frequency switches are one of the most important devices in 4G and 5G communication, and are responsible for switching between different transmission links and receiving links, and the most interesting indexes are Insertion Loss (IL), isolation (ISO), harmonics and the like. The existing transceiver system composed of one or two antennas and a plurality of TRX radio frequency ports comprises one or two antennas and a plurality of TRX radio frequency ports, and controls a radio frequency switch circuit between a multipath receiving and transmitting path.
The existing receiving and transmitting system composed of one or two antennas and a plurality of TRX radio frequency ports can cause problems of insertion loss, harmonic degradation and the like under the condition of no matching network. The rf switch structure is generally used in Sub 3G frequency band, and in general, the higher the frequency of the rf signal, the greater the attenuation and loss of the signal, which may result in increased insertion loss, and the higher the frequency, the more easily harmonic is generated. When a certain channel of the multi-channel TRX radio frequency port is in a receiving and transmitting state, the equivalent capacitance coff of the parallel radio frequency switch in an off state is increased, signal mismatch also occurs, S11 is deteriorated, and the problems of signal reflection, leakage and the like are caused, so that the insertion loss is increased, and harmonic wave deterioration is caused.
Disclosure of Invention
The embodiment of the invention aims to provide a multi-antenna radio frequency receiving and transmitting switch circuit, which is used for solving the problems of insertion loss and harmonic degradation of the existing multi-antenna radio frequency receiving and transmitting switch circuit by connecting a receiving and transmitting matching module on a three-antenna port.
In order to solve the technical problems, in a first aspect, an embodiment of the present invention provides a multi-antenna radio frequency transceiver switch circuit, where the multi-antenna radio frequency transceiver switch circuit includes an antenna port, a transceiver matching module, a switch module and a radio frequency port that are electrically connected in sequence;
The antenna ports comprise at least 3, the transceiver matching modules comprise at least 3, the switch module comprises at least one, the input end of each transceiver matching module is correspondingly connected to one antenna port, the output end of each transceiver matching module is connected with the input end of the switch module, and the output end of the switch module is connected to the radio frequency port;
Each receiving and transmitting matching module comprises a first inductor and a first capacitor, wherein a first end of the first inductor is connected with a first end of the first capacitor and serves as an input end of the receiving and transmitting matching module, a second end of the first capacitor is grounded, and a second end of the first inductor serves as an output end of the receiving and transmitting matching module.
Preferably, the transceiver matching module further comprises a second inductor, a first end of the second inductor is connected with a second end of the first inductor, and a second end of the second inductor is grounded.
Preferably, the switch module comprises a series switch group and a parallel switch group; the control end of the series switch group is used as the input end of the switch module, the output end of the series switch group is connected with the control end of the parallel switch group and used as the output end of the switch module, and the output end of the parallel switch group is grounded.
Preferably, the series switch group includes m first switches connected in series, the parallel switch group includes m second switches connected in parallel, where m is a positive integer greater than 3, a control end of each first switch is used to connect with an output end of the transceiver matching module, an output end of each first switch is connected with a control end of a corresponding second switch, and an output end of each second switch is grounded.
Preferably, the first switch includes n first transistors and a first resistor connected in a field effect stacking manner, a drain electrode of the first transistor is connected to the antenna port, a source electrode of the first transistor is connected to the radio frequency port, a gate electrode of the first transistor is connected to a first end of the first resistor, and a second end of the first resistor is used for being connected to an external first control signal; wherein n is a positive integer greater than or equal to 1, and the source electrode of each first transistor is connected with the drain electrode of the first transistor adjacent to the source electrode;
The second switch comprises n second transistors and a second resistor which are connected in a field effect stacking mode, wherein the drain electrodes of the second transistors are respectively connected with the radio frequency port and the source electrode of the first transistor, the source electrode of the second transistor is grounded, the grid electrode of the second transistor is connected with the first end of the second resistor, and the second end of the second resistor is used for being connected with an external second control signal; the source of each second transistor is connected to the drain of the first transistor adjacent thereto.
Preferably, the multi-antenna radio frequency transceiver switch circuit further comprises a first switch bias circuit, wherein the first switch bias circuit is connected with the switch module and is used for providing direct current bias for the switch module;
the first switch bias circuit comprises a third resistor, a fourth resistor, a first MOS tube and a second MOS tube; the first end of the third resistor is respectively connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube, the grid electrode of the second MOS tube is connected with the drain electrode of the second MOS tube, the drain electrode of the first MOS tube is connected with the first end of the fourth resistor, the second end of the fourth resistor is connected with the source electrode of the first MOS tube, the substrate of the first MOS tube is connected with the source electrode of the second MOS tube, and the substrate of the second MOS tube is suspended.
Preferably, the first MOS tube is an NMOS tube, and the second MOS tube is a PMOS tube.
Preferably, the multi-antenna radio frequency transceiver switch circuit further comprises a second switch bias circuit, wherein the second switch bias circuit is connected with the switch module and is used for providing direct current bias for the switch module;
The second switch bias circuit comprises a fifth resistor, a sixth resistor, a seventh resistor and a third MOS tube; the first end of the fifth resistor is respectively connected with the grid electrode of the third MOS tube and the first end of the seventh resistor, the second end of the seventh resistor is connected with the substrate of the third MOS tube, the drain electrode of the third MOS tube is connected with the first end of the sixth resistor, and the source electrode of the third MOS tube is connected with the second end of the sixth resistor.
Preferably, the third MOS transistor is an NMOS transistor.
In a second aspect, the present invention provides a radio frequency chip, where the radio frequency chip includes the multi-antenna radio frequency transceiver switch circuit described above.
Compared with the prior art, the multi-antenna radio frequency receiving and transmitting switch circuit is electrically connected with an antenna port, a receiving and transmitting matching module, a switch module and a radio frequency port; the number of the antenna ports is at least 3, and one antenna is added, so that the integration level of three antenna switches is increased; the receiving and transmitting matching modules comprise at least 3, the switch module comprises at least one, the input end of each receiving and transmitting matching module is correspondingly connected to one antenna port, the output end of each receiving and transmitting matching module is connected with the input end of the switch module, and the output end of the switch module is connected to the radio frequency port; the receiving and transmitting matching module comprises a first inductor and a first capacitor, wherein a first end of the first inductor is connected with a first end of the first capacitor and is used as an input end of the receiving and transmitting matching module, a second end of the first capacitor is grounded, and a second end of the first inductor is used as an output end of the receiving and transmitting matching module. The first inductor is connected in series with each antenna end, and a first capacitor is connected in parallel to the ground, so that an L-shaped matching network required by a radio frequency front-end circuit is formed, the universality is strong, the integration level is high, and the anti-interference capability is enhanced; the problem of increased insertion loss and deteriorated transmission and reception performance due to signal mismatch in the signal link of the antenna can be avoided, and harmonic suppression of the transmission carrier can be realized.
Drawings
For a clearer description of the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the description below are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
Fig. 1 is an overall circuit diagram of an L-shaped multi-antenna rf transceiver switch circuit provided in an embodiment of the present invention;
fig. 2 is a diagram of an overall circuit of a pi-type multi-antenna rf transceiver switch circuit according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a parallel and series switch structure stack according to an embodiment of the present invention;
fig. 4 is an equivalent circuit diagram of the MOS transistor of the series switch of fig. 3;
Fig. 5 is an equivalent circuit diagram of the MOS transistor of the parallel switch of fig. 3.
In the figure, 100 parts of a multi-antenna radio frequency receiving and transmitting switch circuit, 1 part of an antenna port, 2 parts of a receiving and transmitting matching module, 3 parts of a switch module, 31 parts of a series switch group, 32 parts of a parallel switch group, 4 parts of a radio frequency port, 5 parts of a first switch bias circuit, 6 parts of a second switch bias circuit.
Detailed Description
The following description of the technical solutions in the embodiments of the present invention will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Referring to fig. 1-5, an embodiment of the present invention provides a multi-antenna rf transceiver switch circuit 100, where the multi-antenna rf transceiver switch circuit 100 includes an antenna port 1, a transceiver matching module 2, a switch module 3 and an rf port 4 electrically connected in sequence.
The antenna port 1 comprises at least 3 (ANT 1, ANT2, ANT 3), the transceiver matching module 2 comprises at least 3, the switch module 3 comprises at least one, each input end of the transceiver matching module 2 is correspondingly connected to one antenna port 1, the output end of the transceiver matching module 2 is connected to the input end of the switch module 3, and the output end of the switch module 3 is connected to the radio frequency port 4 (TRX 1, TRX2, TRX3, …, TRXn, n is greater than or equal to 1). One antenna is added, so that the integration level of the three antenna switches is increased.
Each transceiver matching module 2 includes a first inductor L1 and a first capacitor C1, where a first end of the first inductor L1 is connected to a first end of the first capacitor C1 and is used as an input end of the transceiver matching module 2, a second end of the first capacitor C1 is grounded, and a second end of the first inductor L1 is used as an output end of the transceiver matching module 2. The first inductor L1 is connected in series with each antenna end, and the first capacitor C1 is connected to the ground in parallel, so that an L-shaped matching network required by a radio frequency front-end circuit is formed, the universality is strong, the integration level is high, and the anti-interference capability is enhanced; the problem of increased insertion loss and deteriorated transmission and reception performance due to signal mismatch in the signal link of the antenna can be avoided, and harmonic suppression of the transmission carrier can be realized.
In this embodiment, the transceiver matching module 2 further includes a second inductor L2, a first end of the second inductor L2 is connected to a second end of the first inductor L1, and a second end of the second inductor L2 is grounded. The first inductor L1 is connected in series at each antenna end, the first capacitor C1 is connected to the ground in parallel, and the second inductor L2 is connected to the ground in parallel, so that a pi-shaped matching network required by a radio frequency front-end circuit is formed, the universality is strong, the integration level is high, and the anti-interference capability is enhanced; the problem of increased insertion loss and deteriorated transmission and reception performance due to signal mismatch in the signal link of the antenna can be avoided, and harmonic suppression of the transmission carrier can be realized.
In this embodiment, the switch module 3 includes a series switch group 31 and a parallel switch group 32; the control end of the series switch group 31 is used as the input end of the switch module 3, the output end of the series switch group 31 is connected with the control end of the parallel switch group 32 and is used as the output end of the switch module 3, and the output end of the parallel switch group 32 is grounded.
In this embodiment, the series switch group 31 includes m first switches S 1 connected in series, the parallel switch group 32 includes m second switches S 2 connected in parallel, where m is a positive integer greater than 3, a control end of each first switch S 1 is used to connect to an output end of the transceiver matching module 2, an output end of each first switch S 1 is connected to a control end of a corresponding second switch S 2, and an output end of each second switch S 2 is grounded.
The first switches S 1 include switches S 1 to S 2n-1, the second switches S 2 include switches S 2 to S 2n, and n is greater than or equal to 1, and each of the switches S 2n-1 and S 2n is configured as a group of switches in a one-to-one correspondence.
The series switch group 31 (S 1、S3、S5、……、S2n-1) and the parallel switch group 32 (S 2、S4、S6、……、S2n) are respectively provided between the ground and the branch circuit in the series branch circuit. The specific implementation devices of the series switch S 1 and the parallel switch S 2 may be SOI CMOS transistors, or may be other switches.
In this embodiment, the first switch S 1 includes n first transistors M1se and a first resistor connected in a field-effect stacking manner, where a drain electrode of the first transistor M1se is connected to the antenna port 1, a source electrode of the first transistor M1se is connected to the radio frequency port 4, a gate electrode of the first transistor M1se is connected to a first end of the first resistor Rg, se, and a second end of the first resistor Rg, se is used to connect an external first control signal Vg, se; wherein n is a positive integer greater than or equal to 1, and the source of each first transistor M1se is connected to the drain of the first transistor M1se adjacent thereto.
Optionally, the series transistors include M1se, M2se …, mnse.
The second switch S 2 includes n second transistors M1sh and second resistors Rg, sh connected in a field effect stacking manner, drain electrodes of the second transistors M1sh are respectively connected to the radio frequency port 4 and source electrodes of the first transistors M1se, source electrodes of the second transistors M1sh are grounded, gate electrodes of the second transistors M1sh are connected to first ends of the second resistors Rg, sh, and second ends of the second resistors Rg, sh are used for connecting external second control signals Vg, sh; wherein n is greater than or equal to 1, and the source of each second transistor M1sh is connected to the drain of the first transistor M1se adjacent thereto.
Optionally, the parallel transistors include M1sh, M2sh …, mnsh.
The specific structures of the series switch group 31 (S1, S3, S5, … …, S2 n-1) and the parallel switch group 32 (S2, S4, S6, … …, S2 n) are shown in fig. 3, and the SOI radio frequency switch generally adopts a stack (field effect stacked) structure, and in a specific embodiment, the stack number is generally 10 to 15.
In this embodiment, when the transceiver matching module 2 includes a first inductor L1 and a first capacitor C1, the multi-antenna radio frequency transceiver switching circuit 100 further includes a first switching bias circuit 5, where the first switching bias circuit 5 is connected to the switching module 3, and the first switching bias circuit 5 is configured to provide dc bias for the switching module 3.
The first switch bias circuit 5 comprises a third resistor R3, a fourth resistor R4, a first MOS tube N1 and a second MOS tube P1; the first end of the third resistor R3 is respectively connected with the grid electrode of the first MOS tube N1 and the grid electrode of the second MOS tube P1, the grid electrode of the second MOS tube P1 is connected with the drain electrode of the second MOS tube P1, the drain electrode of the first MOS tube N1 is connected with the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected with the source electrode of the first MOS tube N1, the substrate of the first MOS tube N1 is connected with the source electrode of the second MOS tube P1, and the substrate of the second MOS tube P1 is arranged in a suspending mode.
The first MOS tube N1 is an NMOS tube, and the second MOS tube P1 is a PMOS tube.
Specifically, as shown in fig. 4, the specific structures of the transistors of the series switch group 31 and the parallel switch group 32 are that the first switch bias circuit 5 adopts diode bias, that is, a high-resistance dc bias resistor (rg=100 kΩ) needs to be placed at the gate of the transistor, and the body region uses diode self-bias, so that the transistors of the whole branch are in a consistent bias state. The drain electrode D of the series switch group 31 is a first end of the series switch, the source electrode S of the series switch group 31 is a second end of the series switch, the rf port 4 is connected to the ground with the parallel switch, and the gate electrode of the series switch S1 receives the external first control signals Vg, se, vg, se by the first resistor Rg common to each stack, and the sum of the external first control signals Vg, se, vg, se is generally ±2.6v; the drain electrode D of the parallel switch group 32 is a first end of the parallel switch connected to the rf port 4 and the series switch group 31, the source electrode S of the parallel switch group 32 is a second end of the parallel switch connected to the ground, and the gate electrode of the parallel switch receives an external second control signal Vg, sh, which is generally ±2.6v through a second resistor Rg common to each stack.
The L-shaped matching of the matching network is a narrow-band network, particularly for the problem that the insertion loss is increased and the receiving and transmitting performance is deteriorated due to the mismatch of high-frequency signals of a radio frequency switch, and the harmonic suppression of a transmitting carrier wave can be realized.
In this embodiment, when the transceiver matching module 2 includes a first inductor L1, a first capacitor C1 and a second inductor L2; the multi-antenna radio frequency transceiver switch circuit 100 further comprises a second switch bias circuit 6, wherein the second switch bias circuit 6 is connected with the switch module 3, and the second switch bias circuit 6 is used for providing direct current bias for the switch module 3.
The second switch bias circuit 6 comprises a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and a third MOS tube N1; the first end of the fifth resistor R5 is connected to the gate of the third MOS transistor N1 and the first end of the seventh resistor R7, the second end of the seventh resistor R7 is connected to the substrate of the third MOS transistor N1, the drain of the third MOS transistor N1 is connected to the first end of the sixth resistor R6, and the source of the third MOS transistor N1 is connected to the second end of the sixth resistor R6.
The third MOS transistor N1 is an NMOS transistor.
Specifically, the specific structures of the transistors in the series switch group 31 and the parallel switch group 32 are shown in fig. 5, and the second switch bias circuit 6 adopts resistance bias, that is, a high-resistance dc bias resistor (rg=rb=100 kΩ) needs to be placed in the gate and the body of the transistor, so that the transistors in the whole branch are in a consistent bias state; the drain electrode D of the series switch group 31 is connected to the first end of the series switch, the source electrode S of the series switch group 31 is the second end of the series switch, the rf port 4 is connected to the ground with the parallel switch, and the gate electrode of the series switch S1 receives the control signal Vg, se through the stack common resistor Rg, se, and normally takes ±2.6v; the drain D of the parallel switch group 32 is a first end of the parallel switch connected to the rf port 4 and the series switch group 31, the source S of the parallel switch group 32 is a second end of the parallel switch connected to the ground, and the gate of the parallel switch receives an external second control signal Vg, sh through a second resistor Rg, sh common to each stack, and typically takes ±2.6v.
The matching network is higher in pi-type matching ratio than L-type matching Q value, impedance matching between an antenna and a receiving link can be flexibly adjusted, and particularly the problems of increased insertion loss and deterioration of receiving and transmitting performance caused by high-frequency signal mismatch of a radio frequency switch can be solved, and harmonic suppression of a transmitting carrier can be realized. In practical applications, the structure of the electrical second switching bias circuit 6 has stronger suppression of harmonics than the structure of the first switching bias circuit 5.
Example two
The invention provides a radio frequency chip, which comprises the multi-antenna radio frequency transceiver switch circuit 100.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present invention.
Claims (7)
1. The multi-antenna radio frequency receiving and transmitting switch circuit comprises an antenna port, a receiving and transmitting matching module, a switch module and a radio frequency port which are electrically connected in sequence; it is characterized in that the method comprises the steps of,
The antenna ports comprise at least 3, the transceiver matching modules comprise at least 3, the switch module comprises at least one, the input end of each transceiver matching module is correspondingly connected to one antenna port, the output end of each transceiver matching module is connected with the input end of the switch module, and the output end of the switch module is connected to the radio frequency port;
Each receiving and transmitting matching module comprises a first inductor and a first capacitor, wherein a first end of the first inductor is connected with a first end of the first capacitor and is used as an input end of the receiving and transmitting matching module, a second end of the first capacitor is grounded, and a second end of the first inductor is used as an output end of the receiving and transmitting matching module;
The switch module comprises a series switch group and a parallel switch group; the control end of the series switch group is used as the input end of the switch module, the output end of the series switch group is connected with the control end of the parallel switch group and used as the output end of the switch module, and the output end of the parallel switch group is grounded;
The series switch group comprises m first switches which are connected in series, the parallel switch group comprises m second switches which are connected in parallel, wherein m is a positive integer which is more than 3, the control end of each first switch is used for being connected with the output end of the transceiver matching module, the output end of each first switch is connected with the control end of a corresponding second switch, and the output end of each second switch is grounded;
The first switch comprises n first transistors and a first resistor which are connected in a field effect stacking mode, wherein when n is 1, the source electrode of the first transistor is connected with the radio frequency port, the drain electrode of the first transistor is connected with the antenna port, the grid electrode of the first transistor is connected with the first end of the first resistor, and the second end of the first resistor is used for being connected with an external first control signal; when n is a positive integer greater than 1, the source electrode of a first transistor is connected with the radio frequency port, the source electrode of the rest first transistors are connected with the drain electrodes of the adjacent first transistors, the drain electrode of an nth first transistor is connected with the antenna port, the grid electrode of the first transistor is connected with the first end of the first resistor, and the second end of the first resistor is used for being connected with an external first control signal;
The second switch comprises n second transistors and a second resistor which are connected in a field effect stacking mode, wherein when n is 1, the drain electrode of the second transistor is respectively connected with the radio frequency port and the source electrode of the first transistor, the source electrode of the second transistor is grounded, the grid electrode of the second transistor is connected with the first end of the second resistor, and the second end of the second resistor is used for being connected with an external second control signal; when n is a positive integer greater than 1, the drain electrode of the first second transistor is respectively connected with the radio frequency port and the source electrode of the first transistor, the drain electrode of the remaining second transistor is connected with the source electrode of the second transistor adjacent to the drain electrode of the second transistor, the source electrode of the nth second transistor is grounded, the grid electrode of the second transistor is connected with the first end of the second resistor, and the second end of the second resistor is used for being connected with an external second control signal.
2. The multi-antenna radio frequency transmit-receive switch circuit of claim 1, wherein the transmit-receive matching module further comprises a second inductor, a first end of the second inductor being connected to a second end of the first inductor, a second end of the second inductor being grounded.
3. The multi-antenna radio frequency transceiver switching circuit of claim 1, further comprising a first switch bias circuit coupled to the switch module, the first switch bias circuit configured to provide a dc bias for the switch module;
the first switch bias circuit comprises a third resistor, a fourth resistor, a first MOS tube and a second MOS tube; the first end of the third resistor is respectively connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube, the grid electrode of the second MOS tube is connected with the drain electrode of the second MOS tube, the drain electrode of the first MOS tube is connected with the first end of the fourth resistor, the second end of the fourth resistor is connected with the source electrode of the first MOS tube, the substrate of the first MOS tube is connected with the source electrode of the second MOS tube, and the substrate of the second MOS tube is suspended.
4. The multi-antenna radio frequency transmit-receive switch circuit of claim 3, wherein the first MOS transistor is an NMOS transistor and the second MOS transistor is a PMOS transistor.
5. The multi-antenna radio frequency transceiver switching circuit of claim 1, further comprising a second switching bias circuit connected to the switching module, the second switching bias circuit for providing a dc bias for the switching module;
The second switch bias circuit comprises a fifth resistor, a sixth resistor, a seventh resistor and a third MOS tube; the first end of the fifth resistor is respectively connected with the grid electrode of the third MOS tube and the first end of the seventh resistor, the second end of the seventh resistor is connected with the substrate of the third MOS tube, the drain electrode of the third MOS tube is connected with the first end of the sixth resistor, and the source electrode of the third MOS tube is connected with the second end of the sixth resistor.
6. The multi-antenna radio frequency transmit-receive switch circuit of claim 5, wherein the third MOS transistor is an NMOS transistor.
7. A radio frequency chip, characterized in that the radio frequency chip comprises a multi-antenna radio frequency transceiver switching circuit according to any one of claims 1-6.
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| KR20180006176A (en) * | 2016-07-08 | 2018-01-17 | 재단법인 다차원 스마트 아이티 융합시스템 연구단 | Wireless charging system of using multi-frequency for wireless charging at long and short distance |
| CN111525933B (en) * | 2020-04-30 | 2021-12-17 | 维沃移动通信有限公司 | Radio frequency circuit and electronic equipment |
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