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CN117708033A - Bus release device - Google Patents

Bus release device Download PDF

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Publication number
CN117708033A
CN117708033A CN202311797018.4A CN202311797018A CN117708033A CN 117708033 A CN117708033 A CN 117708033A CN 202311797018 A CN202311797018 A CN 202311797018A CN 117708033 A CN117708033 A CN 117708033A
Authority
CN
China
Prior art keywords
switch
clock line
voltage comparator
serial clock
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311797018.4A
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Chinese (zh)
Inventor
吴林林
葛晓欢
王楠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou Micro Nano Core Electronic Technology Co ltd
Original Assignee
Hangzhou Micro Nano Core Electronic Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Hangzhou Micro Nano Core Electronic Technology Co ltd filed Critical Hangzhou Micro Nano Core Electronic Technology Co ltd
Priority to CN202311797018.4A priority Critical patent/CN117708033A/en
Publication of CN117708033A publication Critical patent/CN117708033A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Logic Circuits (AREA)

Abstract

The invention provides a bus release device, which relates to the field of circuit design, and comprises a digital chip, a first switch, a first resistor and a first voltage comparator; the digital chip is used for controlling each component of the device; the output end of the first voltage comparator is electrically connected with the first port of the digital chip; the first serial clock line is connected to a first input end of the first voltage comparator, and is electrically connected with the first device; the first input end of the first voltage comparator is electrically connected with the second port of the digital chip; the input voltage of the second input end of the first voltage comparator is a first preset value; the first serial clock line is also connected to a first end of the first resistor; the first end of the first resistor is electrically connected with the first end of the first switch; the second terminal of the first switch is connected to the ground terminal. The switch can be switched on and off in real time according to the change of the level, and the whole process can be realized without waiting.

Description

Bus release device
Technical Field
The present disclosure relates to the field of circuit design, and in particular, to a bus release device.
Background
I2C (Inter-Integrated Circuit, two-wire serial bus) bus communication is used in various scenarios, but when I2C communicates between different voltage domains, an isolator is required to be used for protection to isolate interference between different circuits. The related art generally uses a level shifter as an isolator, and when a change in the level of one side of the level shifter is detected, after waiting for a preset period of time, the level of the other side of the level shifter is changed accordingly to complete bus release. However, the related art requires waiting for a preset time, so that the real-time performance is poor, and the bus error release is easy to occur.
Disclosure of Invention
The present disclosure provides a bus release device to at least solve the above technical problems in the prior art.
According to a first aspect of the present disclosure, a bus release is provided. The device comprises a digital chip, a first switch, a first resistor and a first voltage comparator; the digital chip is used for controlling various components of the device;
the output end of the first voltage comparator is electrically connected with the first port of the digital chip;
the first serial clock line is connected to the first input end of the first voltage comparator, and the first serial clock line is electrically connected with first equipment; a first input end of the first voltage comparator is electrically connected with a second port of the digital chip; the input voltage of the second input end of the first voltage comparator is a first preset value;
the first serial clock line is also connected to a first end of the first resistor; the first end of the first resistor is electrically connected with the first end of the first switch;
the second end of the first switch is connected to the ground.
In an embodiment, the apparatus further comprises a third switch, a third resistor, and a second voltage comparator; the output end of the second voltage comparator is electrically connected with the fourth port of the digital chip; the second serial clock line is connected to the first input end of the second voltage comparator, and the second serial clock line is electrically connected with second equipment; the first input end of the second voltage comparison is electrically connected with a fifth port of the digital chip; the input voltage of the second input end of the second voltage comparator is a second preset value; the second serial clock line is also connected to the first end of the third resistor; the first end of the third resistor is electrically connected with the first end of the third switch; the second terminal of the third switch is connected to the ground terminal.
In one embodiment, the first serial clock line is used for transmitting an output signal; the second serial clock line is used for transmitting an input signal; the digital chip is used for controlling the first switch and the third switch to be closed under the condition that the first serial clock line is detected to be at a low level and the output end of the first voltage comparator is detected to be at a low level; the digital chip is used for controlling the first switch and the third switch to be disconnected under the condition that the first serial clock line is detected to be in a low level and the output end of the first voltage comparator is detected to be in a high level.
In one embodiment, the first serial clock line is used for transmitting an input signal; the second serial clock line is used for transmitting output signals; the digital chip is used for controlling the first switch and the third switch to be closed under the condition that the second serial clock line is detected to be at a low level and the output end of the second voltage comparator is detected to be at a low level; the digital chip is used for controlling the first switch and the third switch to be disconnected under the condition that the second serial clock line is detected to be in a low level and the output end of the second voltage comparator is detected to be in a high level.
In one embodiment, the device further comprises a second resistor and a second switch; the first serial data line is connected to a seventh port of the digital chip, and is electrically connected with the first device; the first serial data line is also connected to a first end of the second resistor; the second end of the second resistor is electrically connected with the first end of the second switch; the second terminal of the second switch is connected to the ground terminal.
In one embodiment, the apparatus further comprises a fourth resistor and a fourth switch; the second serial data line is connected to the ninth port of the digital chip and is electrically connected with the second device; the second serial data line is also connected to the first end of the fourth resistor; the second section of the fourth resistor is electrically connected with the first end of the fourth switch; the second terminal of the fourth switch is connected to the ground terminal.
In one embodiment, the first serial data line is used for transmitting an output signal; the second serial data line is used for transmitting an input signal; the digital chip is used for controlling the first serial data line to be changed into a low level under the condition that the second serial clock line is detected to be in a low level and the second serial data line is detected to be in a high level.
In one embodiment, the first serial data line is used for transmitting an input signal; the second serial data line is used for transmitting an output signal; the digital chip is further configured to control the first serial data line to be low or to keep the first serial data line high if the first serial clock line is detected to be low.
In one embodiment, the first device includes a first device switch and a device resistor; a first end of the first equipment switch is connected to a first end of the equipment resistor, and a second end of the first equipment switch is connected to the grounding end; a second terminal of the device resistor is connected to the first serial clock line; when the first equipment switch is opened and the first switch is opened, the output voltage of the first voltage comparator is at a high level, and the first serial clock line is at a high level; the output voltage of the first voltage comparator is low level, the first serial clock line is low level, when the first device switch is closed and the first switch is open; the output voltage of the first voltage comparator is low level, the first serial clock line is low level, with the first device switch closed and the first switch closed; with the first device switch open and the first switch closed, the output voltage of the first voltage comparator is high and the first serial clock line is low.
In an embodiment, the digital chip is further configured to determine a level less than a first percentage of the power supply as a low level and a level greater than a second percentage of the power supply as a high level.
According to a second aspect of the present disclosure, there is provided an electronic device comprising the bus release device described above.
When the bus release device and the bus release method are used for bus detection, the switch can be switched on and off according to the change of the level, so that the high level/low level can be transmitted to the other side of the bus release device, the function of bus release is realized, the whole process can be realized without waiting, and the real-time performance is good.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
Fig. 1 shows a schematic flow diagram of an implementation model of a bus release device according to an embodiment of the disclosure;
fig. 2 shows a second implementation model schematic diagram of a bus release device according to an embodiment of the disclosure.
Detailed Description
In order to make the objects, features and advantages of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly described in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.
Fig. 1 shows a schematic circuit structure of a circuit system according to an embodiment of the present application. The device comprises a bus release device U1, a first device I1 and a second device I2. The bus release device comprises a digital chip D1.
The first device I1 and the bus release device U1 are electrically connected through a first power line VCCA, a first serial data line SCL1, a first serial clock line SDA1, and a first ground line GNDA. The bus release device U1 is electrically connected to the second device I2 through the second power line VCCB, the second serial data line SCL2, the second serial clock line SDA2, and the second ground line GNDB.
The power line is used for providing power for the bus release device U1, the first device I1 and the second device I2. In some embodiments, the voltages on the first power line VCCA and the second power line VCCB are different.
The serial data line is used for transmitting data. In some embodiments, the data signal is generated by the first device I1, transmitted to the bus release device U1 through the first serial data line SCL1, and the bus release device U1 transmits the data signal to the first device I2 through the second serial data line SDA 1. In some embodiments, the data signal is generated by the second device I2, transmitted to the bus release device U1 via the second serial data line SCL2, and the bus release device U1 transmits the data signal to the first device I1 via the first serial data line SDA 1.
The serial clock line is used to transmit a clock signal. In some embodiments, the clock signal is transmitted by the first device I1 through the first serial clock line SCL1 into the bus release device U1, and the bus release device U1 in turn transmits the clock signal through the second serial clock line SCL2 into the second device I2. In some embodiments, the clock signal is generated by the second device I2, transmitted to the bus release device U1 through the second serial clock line SCL2, and the bus release device U1 transmits the clock signal to the first device I1 through the first serial clock line SCL1.
The ground wire is used for providing the ground. In some embodiments, the potentials of the first ground line GNDA and the second ground line GNDB are the same. Illustratively, the potentials of the first ground line GNDA and the second ground line GNDB are 0V.
In summary, when the embodiment of the disclosure performs bus detection, the switch is switched on and off according to the level change, so that the high level/low level can be transferred to the other side of the bus release device, the function of bus release is realized, the whole process can be realized without waiting, and the real-time performance is good.
Fig. 2 shows a schematic circuit structure of a bus release device according to an embodiment of the present application. The device comprises a digital chip D1, a first switch K1, a first resistor R1 and a first voltage comparator C1.
The output end of the first voltage comparator C1 is electrically connected with the first port of the digital chip D1. In some embodiments, the electrical device may be a high-speed ADC (Analog-to-Digital Converter), a comparator time-division multiplexing or other voltage change detection circuit in addition to the first voltage comparator C1.
The first serial clock line SCL1 is connected to the first input end of the first voltage comparator C1, and the first serial clock line SCL1 is electrically connected with the first equipment I1; the first input end of the first voltage comparator C1 is electrically connected with the second port of the digital chip D1; the input voltage of the second input end of the first voltage comparator C1 is a first preset value. In some embodiments, the input voltage at the second input of the first voltage comparator C1 is denoted VREF1.
The first serial clock line SCL1 is also connected to a first end of a first resistor R1; the first end of the first resistor R1 is electrically connected to the first end of the first switch K1.
The second terminal of the first switch K1 is connected to the ground GND.
In some embodiments, the first device I1 comprises a first device switch Ki and a device resistor Ri; a first terminal of the first device switch Ki is connected to a first terminal of the device resistor Ri, and a second terminal of the first device switch Ki is connected to the ground GND; the second terminal of the device resistor Ri is connected to the first serial clock line SCL1. The measurement point of the first serial clock line SCL1 in the bus release device U1 is PA (please refer to fig. 2), the equivalent resistance from PA to the ground line is Rd, and the equivalent resistance at the first device I1 side is Rf, so the following four possibilities exist according to the closing condition of the first device switch Ki and the first switch K1:
(1) ki closed, K1 closed: rf=r1'; rd=ri '×rf/(ri' +rf). The voltage at the PA point is v1=vcca Rd/(rd+rc); that is, when the first device switch Ki is closed and the first switch K1 is closed, the output voltage of the first voltage comparator C1 is at a low level, and the first serial clock line SCL1 is at a low level.
(2) ki open, K1 closed: rf=r1'; rd=ri Rf/(ri+rf); the voltage at the PA point is v2=vcca Rd/(rd+rc); that is, when the first device switch Ki is opened and the first switch K1 is closed, the output voltage of the first voltage comparator C1 is at a high level, and the first serial clock line SCL1 is at a low level.
(3) ki closed, K1 open: rf=r1rd=ri Rf/(ri+rf); the voltage at the PA point is v3=vcca Rd/(rd+rc); that is, when the first device switch Ki is closed and the first switch K1 is opened, the output voltage of the first voltage comparator C1 is at a low level, and the first serial clock line SCL1 is at a low level.
(4) ki off, K1 off: rf=r1; rd=ri Rf/(ri+rf); the voltage at the PA point is v4=vcca Rd/(rd+rc). That is, when the first device switch Ki is turned off and the first switch K1 is turned off, the output voltage of the first voltage comparator C1 is at a high level, and the first serial clock line SCL1 is at a high level.
According to the I2C standard, a level below 30% of VCCA is considered as a low level of SCL, and a level above 70% is considered as a high level of SCL. In the embodiment of the disclosure, selecting a suitable resistance value to make the value of V4 greater than vcca×0.7; the values of V1 to V3 are all smaller than VCCA 0.3; and V1 has a value less than VREF1 and V2 is greater than VREF1.
TABLE 1 first Voltage comparator and level of SCL1
The following table relationship can be judged:
1. when in the circuit state S2, since V1 is smaller than Vref, the voltage comparator C1 outputs 0 at this time, i.e., the first voltage comparator C1 outputs a low level;
2. when in the circuit state S3, since V2 is greater than Vref, the voltage comparator C1 outputs 1 at this time, i.e., the first voltage comparator C1 outputs a high level.
In some embodiments, the bus release device U1 further includes a third switch K3, a third resistor R3, and a second voltage comparator C2. The output end of the second voltage comparator C2 is electrically connected with the fourth port of the digital chip D1. The second serial clock line SCL2 is connected to the first input end of the second voltage comparator C2, and the second serial clock line SCL2 is electrically connected with the second equipment I2; the first input end of the second voltage comparator C2 is electrically connected with the fifth port of the digital chip D1; the input voltage of the second input terminal of the second voltage comparator C2 is a second preset value. The second serial clock line SCL2 is also connected to the first end of the third resistor R3; the first end of the third resistor R3 is electrically connected to the first end of the third switch K3. The second terminal of the third switch K3 is connected to the ground GND. Optionally, the second preset value is denoted as REF2.
In some embodiments, the clock signal transmitted by the serial clock line is generated by the second device I2, and after passing through the bus release device U1, enters the first device I1, that is, the first serial clock line SCL1 is used to transmit the output signal; the second serial clock line SCL2 is used for transmitting an input signal, in which case the voltage of the output signal is adapted to the voltage of the second device I2 and the voltage of the input signal is adapted to the voltage of the first device I1. The digital chip D1 is configured to control the first switch K1 and the third switch K3 to be turned on when the first serial clock line SCL1 is detected to be at a low level and the output terminal of the first voltage comparator C1 is detected to be at a low level; the digital chip D1 is configured to control the first switch K1 and the third switch K3 to be turned off when the first serial clock line SCL1 is detected to be at a low level and the output terminal of the first voltage comparator C1 is detected to be at a high level.
Illustratively, when the output of the first device I1 changes from high to low, the first device switch Ki needs to be closed, where the potential at PA is less than Vref, and the digital chip D1 detects that the first serial clock line SCL1 is low, and the output of the first voltage comparator C1 is also low. At this time, the digital chip D1 controls the first switch K1 and the third switch K3 to be turned on, so that the second serial clock line SCL2 on the side of the second device I2 also becomes low level, which is equivalent to that the low level on the left side of the bus release device U1 is transmitted to the right side, and the bus release function is realized.
Illustratively, when the output of the first device I1 changes from low to high, the first device switch Ki needs to be opened, but the first switch K1 is still closed, so that the digital chip D1 detects that the first serial clock line SCL1 is still high, while the potential at PA is greater than VREF1, and the digital chip D1 detects that the output of the first voltage comparator C1 is high. At this time, the digital chip D1 controls the first switch K1 and the third switch K3 to be turned off, so that the second serial clock line SCL2 on the side of the second device I2 also becomes high level, which is equivalent to that the high level on the left side of the bus release device U1 is transmitted to the right side, and the bus release function is realized.
Similarly, in some embodiments, the clock signal transmitted by the serial clock line is generated by the second device I2, and enters the first device I1 after passing through the bus release device U1, that is, the first serial clock line SCL1 is used to transmit the input signal; the second serial clock line SCL2 is used for transmitting an output signal, in which case the voltage of the output signal is adapted to the voltage of the first device I1 and the voltage of the input signal is adapted to the voltage of the second device I2. The digital chip D1 is configured to control the first switch K1 and the third switch K3 to be turned on when the second serial clock line SCL2 is detected to be at a low level and the output terminal of the second voltage comparator C1 is detected to be at a low level; the digital chip D1 is configured to control the first switch K1 and the third switch K3 to be turned off when the second serial clock line SCL is detected to be at a low level and the output terminal of the second voltage comparator C2 is detected to be at a high level.
In some embodiments, the switch includes, but is not limited to, at least one of a mos switch, a switch array, a switching circuit.
The bus release unit U1 needs to convert serial data signals in addition to serial clock signals. The bus release U1 is also provided with corresponding ports and electrical devices. In some embodiments, the bus release device U1 further includes a second resistor R2 and a second switch K2; the first serial data line SDA1 is connected to the seventh port of the digital chip D1, and the first serial data line SDA1 is electrically connected to the first device I1; the first serial data line SDA1 is also connected to a first end of the second resistor R2; the second end of the second resistor R2 is electrically connected with the first end of the second switch K2; the second terminal of the second switch K2 is connected to the ground GND.
In some embodiments, bus release U1 further comprises a fourth resistor R4 and a fourth switch K4; the second serial data line SDA2 is connected to the ninth port of the digital chip D1, and the second serial data line SDA2 is electrically connected to the second device I2; the second serial data line SDA2 is also connected to the first end of the fourth resistor R4; the second section of the fourth resistor R4 is electrically connected with the first end of the fourth switch K4; the second terminal of the fourth switch K4 is connected to the ground GND.
In some embodiments, the first serial data line SDA1 is used to transmit an output signal; the second serial data line SDA2 is used for transmitting an input signal; the digital chip is configured to control the first serial data line SDA1 to be low level if the second serial clock line SCL2 is detected to be low level and the second serial data line SDA2 is detected to be high level.
In some embodiments, the first serial data line SDA1 is used to transmit an input signal; the second serial data line SDA2 is used for transmitting an output signal; the digital chip D1 is also used to control the first serial data line SDA1 to go low or to keep the first serial data line SDA1 high if it is detected that the first serial clock line SCL1 is low.
In summary, when the embodiment of the disclosure performs bus detection, the switch is switched on and off according to the level change, so that the high level/low level can be transferred to the other side of the bus release device, the function of bus release is realized, the whole process can be realized without waiting, and the real-time performance is good.
In some embodiments, the workflow of the bus detection device U1 may be expressed as follows:
1) The first switch K1 and the third switch K3 are turned off by default. At this time, the PA point has a voltage greater than VCC by 70% due to the pull-up resistor, and the digital chip detects the SCL input between U1 and I1 to be high.
2) When SCL1 of the first device I1 outputs a low level, ki is in a closed state, at this time, the PA point voltage is lower than VREF1, the digital module detects that SCL input is low level, the comparator also outputs a low level, and the digital module D1 controls K1 and K3 to be closed. SCL between I2 and U1 is pulled low due to K3 closing. The low level corresponding to the left is transferred to the right.
3) When the module I1 starts to output high level, ki is opened, and SCL detected by the digital module D1 is still low level due to the fact that K1 is still closed, but at this time, since the voltage of the PA point is greater than VREF, the comparator outputs high level, the digital module can judge that I1 has released the SCL bus accordingly, the digital module then opens K1 and K3, then the SCL on the left is restored to high level, and simultaneously SCL on the right is also released due to K3 opening, which is equivalent to high level being transferred to the right.
4) When SCL2 is actively pulled down on the right side, U1 likewise passes the signal from the right side to the left side in the same sense and control.
5) The processing for the serial data line is as follows: u1 receives the signal output from left or right and judges the transmission direction of the signal.
If the left is the output: when the digital chips D1-SCL 2 inputs are low while detecting the SDA2 input. If SDA2 is low, SDA1 is also pulled low after pulling down the other side SCL1, otherwise the high level of SDA1 is kept unchanged.
If the right is the output: then SDA1 on the left is pulled low or remains high while SCL2 is detected as low.
In summary, when the embodiment of the disclosure performs bus detection, the switch is switched on and off according to the level change, so that the high level/low level can be transferred to the other side of the bus release device, the function of bus release is realized, the whole process can be realized without waiting, and the real-time performance is good.
The embodiment of the disclosure also provides a component on the traffic equipment, wherein the component comprises a chip, and the chip comprises the micro-controller unit system.
In some alternative embodiments, the component may be a circuit board level component, a vehicle electrical system level component, or a vehicle assembly component. As examples, the components may be an engine, a chassis, a body, and electrical and electronic equipment of a vehicle. Among them, the electric and electronic devices of the vehicle may include a headlight for illumination, a management device controlling the engine, a center control device receiving broadcasting, navigation, listening to music, entertainment, etc.
The embodiment of the disclosure also provides a traffic device, which comprises a chip, wherein the chip comprises the micro-controller unit system. The chip may be a multi-core heterogeneous chip, and the traffic equipment includes, but is not limited to, a balance car, a bus, a train, an airplane, or the like.
The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the present disclosure. Any modifications, equivalent substitutions, improvements, etc. that are within the spirit and scope of the present disclosure are intended to be included within the scope of the present disclosure.

Claims (10)

1. A bus release device, comprising a digital chip, a first switch, a first resistor and a first voltage comparator; the digital chip is used for controlling various components of the device;
the output end of the first voltage comparator is electrically connected with the first port of the digital chip;
the first serial clock line is connected to the first input end of the first voltage comparator, and the first serial clock line is electrically connected with first equipment; a first input end of the first voltage comparator is electrically connected with a second port of the digital chip; the input voltage of the second input end of the first voltage comparator is a first preset value;
the first serial clock line is also connected to a first end of the first resistor; the first end of the first resistor is electrically connected with the first end of the first switch;
the second end of the first switch is connected to the ground.
2. The apparatus of claim 1, further comprising a third switch, a third resistor, and a second voltage comparator;
the output end of the second voltage comparator is electrically connected with the fourth port of the digital chip;
the second serial clock line is connected to the first input end of the second voltage comparator, and the second serial clock line is electrically connected with second equipment; the first input end of the second voltage comparison is electrically connected with a fifth port of the digital chip; the input voltage of the second input end of the second voltage comparator is a second preset value;
the second serial clock line is also connected to the first end of the third resistor; the first end of the third resistor is electrically connected with the first end of the third switch;
the second terminal of the third switch is connected to the ground terminal.
3. The apparatus of claim 2, wherein the first serial clock line is configured to transmit an output signal; the second serial clock line is used for transmitting an input signal;
the digital chip is used for controlling the first switch and the third switch to be closed under the condition that the first serial clock line is detected to be at a low level and the output end of the first voltage comparator is detected to be at a low level;
the digital chip is used for controlling the first switch and the third switch to be disconnected under the condition that the first serial clock line is detected to be in a low level and the output end of the first voltage comparator is detected to be in a high level.
4. The apparatus of claim 2, wherein the first serial clock line is configured to transmit an input signal; the second serial clock line is used for transmitting output signals;
the digital chip is used for controlling the first switch and the third switch to be closed under the condition that the second serial clock line is detected to be at a low level and the output end of the second voltage comparator is detected to be at a low level;
the digital chip is used for controlling the first switch and the third switch to be disconnected under the condition that the second serial clock line is detected to be in a low level and the output end of the second voltage comparator is detected to be in a high level.
5. The apparatus of any one of claims 1 to 4, further comprising a second resistor and a second switch;
the first serial data line is connected to a seventh port of the digital chip, and is electrically connected with the first device; the first serial data line is also connected to a first end of the second resistor; the second end of the second resistor is electrically connected with the first end of the second switch;
the second terminal of the second switch is connected to the ground terminal.
6. The apparatus of claim 5, further comprising a fourth resistor and a fourth switch;
the second serial data line is connected to the ninth port of the digital chip and is electrically connected with the second device; the second serial data line is also connected to the first end of the fourth resistor; the second section of the fourth resistor is electrically connected with the first end of the fourth switch;
the second terminal of the fourth switch is connected to the ground terminal.
7. The apparatus of claim 5, wherein the first serial data line is configured to transmit an output signal; the second serial data line is used for transmitting an input signal;
the digital chip is used for controlling the first serial data line to be changed into a low level under the condition that the second serial clock line is detected to be in a low level and the second serial data line is detected to be in a high level.
8. The apparatus of claim 5, wherein the first serial data line is for transmitting an input signal; the second serial data line is used for transmitting an output signal;
the digital chip is further configured to control the first serial data line to be low or to keep the first serial data line high if the first serial clock line is detected to be low.
9. The apparatus of any one of claims 1 to 4, wherein the first device comprises a first device switch and a device resistor; a first end of the first equipment switch is connected to a first end of the equipment resistor, and a second end of the first equipment switch is connected to the grounding end; a second terminal of the device resistor is connected to the first serial clock line;
when the first equipment switch is opened and the first switch is opened, the output voltage of the first voltage comparator is at a high level, and the first serial clock line is at a high level;
the output voltage of the first voltage comparator is low level, the first serial clock line is low level, when the first device switch is closed and the first switch is open;
the output voltage of the first voltage comparator is low level, the first serial clock line is low level, with the first device switch closed and the first switch closed;
with the first device switch open and the first switch closed, the output voltage of the first voltage comparator is high and the first serial clock line is low.
10. The device according to any one of claims 1 to 8, wherein,
the digital chip is further configured to determine a level less than a first percentage of the power supply as a low level and a level greater than a second percentage of the power supply as a high level.
CN202311797018.4A 2023-12-25 2023-12-25 Bus release device Pending CN117708033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311797018.4A CN117708033A (en) 2023-12-25 2023-12-25 Bus release device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311797018.4A CN117708033A (en) 2023-12-25 2023-12-25 Bus release device

Publications (1)

Publication Number Publication Date
CN117708033A true CN117708033A (en) 2024-03-15

Family

ID=90144187

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311797018.4A Pending CN117708033A (en) 2023-12-25 2023-12-25 Bus release device

Country Status (1)

Country Link
CN (1) CN117708033A (en)

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