CN117691986A - High-speed double-level converter - Google Patents

Abstract

The invention discloses a high-speed double-level converter. The drain electrode of the sixth NMOS tube is connected with the input end of the first buffer, the drain electrode of the thirteenth PMOS tube, the drain electrode of the fourteenth PMOS tube, the grid electrode of the fifteenth PMOS tube, the grid electrode of the sixteenth PMOS tube and the first output end; the drain electrode of the seventh NMOS tube is connected with the input end of the second buffer, the drain electrode of the sixteenth PMOS tube, the drain electrode of the fifteenth PMOS tube, the grid electrode of the thirteenth PMOS tube, the grid electrode of the fourteenth PMOS tube and the second output end. In the invention, the level inversion of a pair of differential output ends is realized by two transistors connected with the output ends of two buffers without depending on a cross positive feedback structure in a circuit, so that the high-speed inversion of the level state of the output ends is realized; the voltage of the high-level signal at the output end can reach the high-voltage power supply voltage, and the rear logic circuit has no leakage risk, no direct current and no direct current loss; high-speed level conversion can be realized without an intermediate power supply.

Description

High-speed double-level converter

Technical Field

The present invention relates to a level shifter in the field of integrated circuits.

Background

A level shifter (level shifter) is a voltage conversion circuit, which is a voltage platform. For example, if communication is required between two chips with different power supply voltages, conversion between two power supply voltages (levels) is required. The level shifter may be switched from one voltage to another voltage or voltages. A bi-level converter is one of level converters, and refers to a voltage conversion circuit that directly converts one voltage into another voltage.

Referring to fig. 1, a conventional level shifter is shown. in_lv and inb_lv are a pair of low voltage differential signals input to the level shifter, and out_hv and outb_hv are a pair of high voltage differential signals output from the level shifter. The source electrode of the first PMOS tube PM1 and the source electrode of the second PMOS tube PM2 are both connected with the high-voltage power supply voltage vdd_hv. The grid electrode of the first PMOS tube PM1 is connected with the second output end. The grid electrode of the second PMOS tube PM2 is connected with the first output end. The drain electrode of the first PMOS tube PM1 is connected with the source electrode of the third PMOS tube PM 3. The drain electrode of the second PMOS tube PM2 is connected with the source electrode of the fourth PMOS tube PM 4. The drain electrode of the third PMOS tube PM3 is connected to the drain electrode of the first NMOS tube NM1, and is further connected to the gate electrode of the second PMOS tube PM2, and is used as the first output end to output the outb_hv. The drain electrode of the fourth PMOS tube PM4 is connected to the drain electrode of the second NMOS tube NM2, and is further connected to the gate electrode of the first PMOS tube PM1, and is used as the second output end to output out_hv. The gate of the third PMOS PM3 is connected to the gate of the first NMOS NM1, and receives in_lv as the first input terminal. The gate of the fourth PMOS PM4 is connected to the gate of the second NMOS NM2, and receives the inb_lv input as the second input terminal. The source of the first NMOS transistor NM1 and the source of the second NMOS transistor NM2 are both grounded vss.

In the level shifter shown in fig. 1, if the initial state in_lv is at a low level (voltage equal to or close to vss) and inb_lv is at a high level (voltage equal to or close to vdd_hv), out_hv is at a high level and outb_hv is at a low level. The specific circuit operation is as follows. The first NMOS tube NM1 is in a cut-off state, the first PMOS tube PM1 and the third PMOS tube PM3 are in a conduction state, the second NMOS tube NM2 and the fourth PMOS tube PM4 are in a conduction state, and the second PMOS tube PM2 is in a cut-off state. When in_lv is turned from low level to high level, inb_lv is turned from high level to low level, the first NMOS tube NM1 is turned from off to on, the second NMOS tube NM2 is turned from on to off, and since out_hv and outb_hv are not yet turned over, the first PMOS tube PM1 and the third PMOS tube PM3 are still in a conducting state, and the voltage of the outb_hv is gradually reduced only when the driving capability of the first NMOS tube NM1 is stronger than that of the first PMOS tube PM1 and the third PMOS tube PM 3. When the voltage V (outb_hv) < vdd_hv-VTH of the first output end, where VTH represents the same threshold voltage of all the MOS transistors, the second PMOS transistor PM2 is switched to the on state, the second PMOS transistor PM2 and the fourth PMOS transistor PM4 are turned on, and then charge out_hv, and the voltage of out_hv gradually rises. Meanwhile, the driving capability of the first PMOS tube PM1 gradually weakens, the outb_hv is accelerated and falls, the driving capability of the second PMOS tube PM2 gradually strengthens, and the out_hv is accelerated and rises. Eventually out_hv stabilizes to vdd_hv, outb_hv stabilizes to vss, completing a flip. Because the circuit shown in fig. 1 is symmetrical left and right, the same can be known that in_lv is turned from high level to low level in the initial state, and meanwhile, when inb_lv is turned from low level to high level, out_hv is turned from high level to low level, and outb_hv is turned from low level to high level, so that the working states of all MOS transistors are changed.

In the level shifter shown in fig. 1, since the gate connection manner of the first PMOS tube PM1 and the second PMOS tube PM2 forms the cross positive feedback, the driving capability of the first NMOS tube NM1 and the second NMOS tube NM2 must be greater than that of the first PMOS tube PM1 and the second PMOS tube PM2, otherwise, the level shifter cannot be turned over. The level shifter is a digital signal that converts a digital signal of a low voltage domain into a digital signal of a high voltage domain, where the digital signal is composed of a low level and a high level. If the digital signal of the low voltage domain jumps from low to high or high to low. The same flip of the level shifter output should occur, i.e. a jump from low to high or from high to low. In order to ensure that the circuit can work normally at each process corner (process corner), it is necessary to ensure that the driving forces of the first PMOS tube PM1 and the second PMOS tube PM2 are much weaker than those of the first NMOS tube NM1 and the second NMOS tube NM2, resulting in slower rise times of the high-voltage differential output signals out_hv and outb_hv, and limited input signal speeds, so that the level shifter cannot realize high-speed inversion.

Referring to fig. 2, a current mode evolution type high-speed level converter is shown. in_lv and inb_lv are a pair of low voltage differential signals input to the level shifter, out_hv and outb_hv are theA pair of high voltage differential signals output by the level shifter. The source of the fifth PMOS pipe PM5 and the source of the sixth PMOS pipe PM6 are both connected with the high-voltage power supply voltage vdd_hv. The drain electrode of the fifth PMOS tube PM5 is connected with the source electrode of the seventh PMOS tube PM 7. The drain electrode of the sixth PMOS tube PM6 is connected with the source electrode of the eighth PMOS tube PM 8. The drain electrode of the seventh PMOS tube PM7 is connected to the drain electrode of the third NMOS tube NM3, and further connected to the gate electrode of the fifth PMOS tube PM5, and further connected to the gate electrode of the eighth PMOS tube PM8, and is used as the first output end to output the outb_hv. The drain electrode of the eighth PMOS tube PM8 is connected to the drain electrode of the fourth NMOS tube NM4, and further connected to the gate electrode of the sixth PMOS tube PM6, and further connected to the gate electrode of the seventh PMOS tube PM7, and is used as the second output end to output out_hv. The gate of the third NMOS transistor NM3 receives in_lv as the first input terminal. The gate of the fourth NMOS transistor NM4 receives the inb_lv input as the second input terminal. The source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are both grounded vss. The current formula of the MOS tube working in the saturation region is:wherein I is the source leakage current of the MOS transistor, u _n And c _ox W is the channel width of the MOS tube, L is the channel length of the MOS tube, V _GS V is the voltage difference between the source electrode and the grid electrode of the MOS tube _TH Is the threshold voltage of the MOS tube. If two or more MOS transistors are at V _GS Under the condition of approximately equal source-drain current, the source-drain current is in direct proportion to the width-to-length ratio of the MOS transistor, and current mirror image can be realized. The fifth PMOS transistor PM5 and the eighth PMOS transistor PM8 form a current mirror. The sixth PMOS transistor PM6 and the seventh PMOS transistor PM7 form a current mirror.

In the level shifter shown in fig. 2, a broken line portion indicates a circuit other than the main body circuit, by way of example only. The non-body circuits are, for example: the source of the ninth PMOS pipe PM9 is connected with the high-voltage power supply voltage vdd_hv, and the drain of the ninth PMOS pipe PM9 is connected with the drain of the fifth NMOS pipe NM 5. The source of the fifth NMOS transistor NM5 is grounded vss. The gates of the ninth PMOS PM9 and the fifth NMOS NM5 are connected to the second output terminal.

In the level shifter shown in fig. 2, when in_lv is high level and inb_lv is low level, a current mirror is generated through the fifth PMOS transistor PM5 and the eighth PMOS transistor PM8, and the drain current of the third NMOS transistor NM3 is mirrored to the second output terminal. When in_lv is low level and inb_lv is high level, current mirror images are generated through the sixth PMOS tube PM6 and the seventh PMOS tube PM7, drain current of the fourth NMOS tube NM4 is mirrored to the first output end, and high-speed overturning of high-voltage differential output signals out_hv and outb_hv is achieved. The gate and drain shorts of the transistor are called diode connections. When the seventh PMOS PM7 is turned on, the gate and the drain of the fifth PMOS PM5 are equivalent to a short circuit. When the eighth PMOS tube PM8 is turned on, the gate and the drain of the sixth PMOS tube PM6 are equivalent to a short circuit. Since the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are all connected by using diodes, the high-level voltage of the high-voltage differential output signals out_hv and outb_hv can only reach vdd_hv-vth, where vth represents the same threshold voltage of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM 6. If vdd_hv is close to or less than 2 times vth, the level shifter is not applicable, and may cause leakage of the ninth PMOS transistor PM9 in the later logic (dotted line portion). Leakage current is direct current and increases direct current power consumption.

Referring to fig. 3, a conventional multilevel converter is shown. The input pair of low voltage differential signals in_lv and inb_lv are first converted to an intermediate voltage vdd_mv by a level shifter first, resulting in a pair of intermediate voltage differential signals out_mv and outb_mv. The pair of intermediate voltage differential signals out_mv and outb_mv are then converted to the high voltage vdd_hv by a level shifter two, and a pair of high voltage differential signals out_hv and outb_hv are output. This scheme enables high speed level shifting, but introducing the intermediate power supply vdd_mv requires an additional voltage generator, resulting in complex overall circuitry.

Disclosure of Invention

The invention aims to solve the technical problem of realizing high-speed level conversion without intermediate power supply voltage and direct current.

In order to solve the technical problems, the invention provides a high-speed double-level converter, which comprises two NMOS (N-channel metal oxide semiconductor) tubes, seven PMOS (P-channel metal oxide semiconductor) tubes and two buffers; the pair of low voltage differential signals in_lv and inb_lv are input to a pair of differential inputs of the level shifter, and the pair of differential outputs of the level shifter output a pair of high voltage differential signals outb_hv and out_hv. The grid electrode of the sixth NMOS tube is used as a first input end, and the grid electrode of the seventh NMOS tube is used as a second input end; the source electrode of the sixth NMOS tube and the source electrode of the seventh NMOS tube are grounded; the drain electrode of the sixth NMOS tube is connected with the input end of the first buffer, the drain electrode of the thirteenth PMOS tube, the drain electrode of the fourteenth PMOS tube, the grid electrode of the fifteenth PMOS tube, the grid electrode of the sixteenth PMOS tube and the first output end; the drain electrode of the seventh NMOS tube is connected with the input end of the second buffer, the drain electrode of the sixteenth PMOS tube, the drain electrode of the fifteenth PMOS tube, the grid electrode of the thirteenth PMOS tube, the grid electrode of the fourteenth PMOS tube and the second output end. The source electrode of the thirteenth PMOS tube is connected with the drain electrode of the tenth PMOS tube PM 10; the source electrode of the sixteenth PMOS tube is connected with the drain electrode of the eleventh PMOS tube; the grid electrode of the tenth PMOS transistor is connected with the output end of the first buffer; the grid electrode of the eleventh PMOS tube is connected with the output end of the second buffer. The source electrode of the fourteenth PMOS tube and the source electrode of the fifteenth PMOS tube are connected with the drain electrode of the twelfth PMOS tube; the grid electrode of the twelfth PMOS tube is connected with a low-voltage power supply. The source electrode of the tenth PMOS transistor, the source electrode of the eleventh PMOS transistor and the source electrode of the twelfth PMOS transistor are all connected with high-voltage power supply voltage.

Further, the driving current of the twelfth PMOS transistor satisfies the following four conditions simultaneously: the drain current of the first output end is larger than the drain current of the second output end.

Further, the delay of the first buffer and the second buffer is more than half of the rising time of the two output ends from the low level to the high level.

Preferably, the aspect ratio of the conducting channel of each MOS tube is adjusted so that the driving current of the twelfth PMOS tube meets the four conditions.

Preferably, the twelfth PMOS transistor uses an inverse ratio transistor, i.e., the channel length is greater than the channel width.

Alternatively, the twelfth PMOS transistor is changed to a resistor, and the low-voltage power supply is omitted; one end of the resistor is connected with high-voltage power supply voltage, and the other end of the resistor is connected with the source electrode of the fourteenth PMOS tube and the source electrode of the fifteenth PMOS tube.

Further, when out_hv is low level and outb_hv is high level, the tenth PMOS tube is closed, and the eleventh PMOS tube is turned on; when the out_hv is at a high level and the outb_hv is at a low level, the tenth PMOS tube is turned on, and the eleventh PMOS tube is turned off; the two output ends are turned from low level to high level and are completed by a tenth PMOS tube and an eleventh PMOS tube.

Further, when in_lv is turned from low level to high level and inb_lv is turned from high level to low level, the seventh NMOS transistor NM7 is turned off, the sixth NMOS transistor NM6 is turned on, weak driving current of the twelfth PMOS transistor and the fourteenth PMOS transistor is overcome, electric charge is discharged, the outb_hv is rapidly lowered to vss, and the first buffer outputs low level to drive the tenth PMOS transistor to be turned on; when the outb_hv is smaller than the threshold voltage of the vdd_hv-sixteenth NMOS transistor, the sixteenth PMOS transistor is conducted to charge out_hv, the out_hv rapidly reaches the high voltage vdd_hv, and the second buffer outputs high level to drive the eleventh PMOS transistor to be closed; the grid connection mode of the fourteenth PMOS tube and the fifteenth PMOS tube forms cross positive feedback, so that the out_hv is ensured to maintain high voltage vdd_hv.

Further, when in_lv is turned from high level to low level and inb_lv is turned from low level to high level, the sixth NMOS tube is closed, the seventh NMOS tube is conducted, weak driving current of the twelfth PMOS tube and the fifteenth PMOS tube is overcome, charges are discharged, out_hv is rapidly reduced to vss, and the second buffer outputs low level to drive the eleventh PMOS tube to be conducted; when out_hv is smaller than the threshold voltage of the vdd_hv-thirteenth NMOS tube, the thirteenth PMOS tube is conducted to charge the outb_hv, the outb_hv rapidly rises to the high voltage vdd_hv, and the first buffer outputs high level to drive the tenth PMOS tube to be closed; the grid connection mode of the fourteenth PMOS tube and the fifteenth PMOS tube forms cross positive feedback, so that the outb_hv is ensured to maintain the high level vdd_hv.

Further, the grid connection mode of the thirteenth PMOS tube, the fourteenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube forms cross positive feedback for maintaining the voltage of the two output ends at the high-voltage power supply voltage.

The invention has the technical effects that: the level inversion of a pair of differential output ends is realized by two transistors connected with the output ends of two buffers without depending on a cross positive feedback structure in a circuit, so that the high-speed inversion of the level state of the output ends is realized; the voltage of the high-level signal at the output end can reach the high-voltage power supply voltage, and the rear logic circuit has no leakage risk, no direct current and no direct current loss; high-speed level conversion can be realized without an intermediate power supply.

Drawings

Fig. 1 is a schematic diagram of a conventional level shifter.

Fig. 2 is a schematic diagram of a conventional current mode evolution type high-speed level shifter.

Fig. 3 is a schematic diagram of a conventional multilevel converter.

Fig. 4 is a schematic diagram of a high-speed dual-level converter according to the present invention.

The reference numerals in the drawings illustrate: in_lv and inb_lv are a pair of low voltage differential signals, out_mv and outb_mv are a pair of intermediate voltage differential signals, out_hv and outb_hv are a pair of high voltage differential signals, vss is ground, vdd_mv is an intermediate voltage drain supply voltage, vdd_hv is a high voltage supply voltage, PMx (x is a number) is a PMOS tube, NMx (x is a number) is an NMOS tube, NUFx (x is a number) is a buffer, vlo is a low voltage supply.

Detailed Description

Please refer to fig. 4, which shows a high-speed dual-level converter according to the present invention. The two buffers (each composed of even number of inverters) BUF1 and BUF2 comprise two NMOS tubes NM6 and NM7, and seven PMOS tubes PM10, PM11, PM12, PM13, PM14, PM15 and PM 16. in_lv and inb_lv are a pair of low voltage differential signals input to the level shifter, and out_hv and outb_hv are a pair of high voltage differential signals output from the level shifter. The gate of the sixth NMOS transistor NM6 is used as the first input terminal, and receives the input of in_lv. The gate of the seventh NMOS transistor NM7 serves as a second input terminal, and receives the input of inb_lv. The source of the sixth NMOS transistor NM6 and the source of the seventh NMOS transistor NM7 are both grounded vss. The drain electrode of the sixth NMOS transistor NM6 is connected to the input end of the first buffer BUF1, further connected to the drain electrode of the thirteenth PMOS transistor PM13, further connected to the drain electrode of the fourteenth PMOS transistor PM14, further connected to the gate electrode of the fifteenth PMOS transistor PM15, further connected to the gate electrode of the sixteenth PMOS transistor PM16, and used as the first output end to output the output_hv. The drain electrode of the seventh NMOS transistor NM7 is connected to the input end of the second buffer BUF2, further connected to the drain electrode of the sixteenth PMOS transistor PM16, further connected to the drain electrode of the fifteenth PMOS transistor PM15, further connected to the gate electrode of the thirteenth PMOS transistor PM13, further connected to the gate electrode of the fourteenth PMOS transistor PM14, and output out_hv as the second output end. The source electrode of the thirteenth PMOS tube PM13 is connected with the drain electrode of the tenth PMOS tube PM 10. The source of the sixteenth PMOS transistor PM16 is connected to the drain of the eleventh PMOS transistor PM 11. The gate of the tenth PMOS transistor PM10 is connected to the output terminal of the first buffer BUF 1. The gate of the eleventh PMOS PM11 is connected to the output terminal of the second buffer BUF2. The source electrode of the fourteenth PMOS tube PM14 and the source electrode of the fifteenth PMOS tube PM15 are connected with the drain electrode of the twelfth PMOS tube PM 12. The gate of the twelfth PMOS transistor PM12 is connected to the low voltage power supply vlo. The source of the tenth PMOS transistor PM10, the source of the eleventh PMOS transistor PM11, and the source of the twelfth PMOS transistor PM12 are all connected to the high voltage power supply vdd_hv.

In the high-speed dual-level converter shown in fig. 4, the driving current of the twelfth PMOS PM12 is required to satisfy the following four conditions: (1) less than one tenth of the drive current of the sixth NMOS transistor NM6, (2) less than one tenth of the drive current of the seventh NMOS transistor NM7, (3) greater than the leakage current of the first output terminal, and (4) greater than the leakage current of the second output terminal. This defined relationship is achieved, for example, by adjusting the aspect ratio of the conduction channels of the individual MOS transistors. The above four limitations have the following two effects. In the first aspect, since the gate of the twelfth PMOS transistor PM12 is connected to the low voltage source vlo, the driving capability (i.e., the supplied current) of the twelfth PMOS transistor PM12 is significantly weaker than that of the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7, which is advantageous for signal inversion, and the combined driving capability of the twelfth PMOS transistor PM12, the fourteenth PMOS transistor PM14 and the fifteenth PMOS transistor PM15 is significantly weaker than that of the sixth NMOS transistor NM6 and the seventh NMOS transistor NM 7. The low voltage power supply vlo is typically created by additional circuitry to avoid ESD (electrostatic discharge ). In the second aspect, the twelfth PMOS PM12 has a stronger driving capability than the leakage current of the two output terminals, which makes the twelfth PMOS PM12, the fourteenth PMOS PM14, and the fifteenth PMOS PM15 have a stronger comprehensive driving capability than the leakage current of the two output terminals, in order to maintain the high-level voltage of the output terminal as vdd_hv. The twelfth PMOS transistor PM12, the fourteenth PMOS transistor PM14, and the fifteenth PMOS transistor PM15 are designed to maintain the high level therein at the high voltage vdd_hv after the output high voltage differential signal is turned over in the case that the speed of the input differential signal is very low (low frequency) or direct current. If these three devices are removed, the high level in the output high voltage differential signal after the inversion is completed will drop due to the leakage current at the corresponding output terminal increasing with time, resulting in the voltage of the high level being gradually smaller than vdd_hv. In addition, when the twelfth PMOS transistor PM12 is designed as an inverse ratio transistor (i.e., the channel length L is greater than the channel width W), the gate capacitance of the twelfth PMOS transistor PM12 is larger, which is beneficial to reducing the areas of the fourteenth PMOS transistor PM14 and the fifteenth PMOS transistor PM 15.

Alternatively, the twelfth PMOS transistor PM12 is replaced with a resistor, and the voltage source vlo is omitted, and the above four limitations are not required to be considered. One end of the resistor is connected with the high-voltage power supply voltage vdd_hv, and the other end of the resistor is connected with the source electrode of the fourteenth PMOS tube PM14 and the source electrode of the fifteenth PMOS tube PM 15.

In the high-speed dual-level converter shown in fig. 4, when out_hv is at a low level and outb_hv is at a high level, the tenth PMOS pipe PM10 is turned off and the eleventh PMOS pipe PM11 is turned on. When out_hv is at high level and outb_hv is at low level, the tenth PMOS pipe PM10 is turned on, and the eleventh PMOS pipe PM11 is turned off.

When in_lv is turned from low level to high level and inb_lv is turned from high level to low level, the seventh NMOS transistor NM7 is turned off, the sixth NMOS transistor NM6 is turned on, weak driving current is overcome to the twelfth PMOS transistor PM12 and the fourteenth PMOS transistor PM14, electric charge is discharged, the outb_hv is rapidly dropped to vss, and the first buffer BUF1 outputs low level to drive the tenth PMOS transistor PM10 to be turned on. When the outb_hv is smaller than the vdd_hv-VTH, wherein VTH represents the same threshold voltage of all MOS transistors, the sixteenth PMOS transistor PM16 is conducted to charge the out_hv, the out_hv rapidly reaches the high voltage vdd_hv, and the second buffer BUF2 outputs a high level to drive the eleventh PMOS transistor PM11 to be turned off. The gate connection mode of the fourteenth PMOS tube PM14 and the fifteenth PMOS tube PM15 forms cross positive feedback, so that the out_hv level is ensured to maintain the high voltage vdd_hv.

When in_lv is turned from high level to low level and inb_lv is turned from low level to high level, the sixth NMOS transistor NM6 is turned off, the seventh NMOS transistor NM7 is turned on and overcomes weak driving current of the twelfth PMOS transistor PM12 and the fifteenth PMOS transistor PM15 and discharges charges, out_hv is rapidly lowered to vss, and the second buffer BUF2 outputs low level to drive the eleventh PMOS transistor PM11 to be turned on. When out_hv is smaller than vdd_hv-VTH, the thirteenth PMOS pipe PM13 is conducted to charge the outb_hv, the outb_hv rapidly rises to the high voltage vdd_hv, and the first buffer BUF1 outputs a high level to drive the tenth PMOS pipe PM10 to be closed. The gate connection mode of the fourteenth PMOS tube PM14 and the fifteenth PMOS tube PM15 forms cross positive feedback, so that the outb_hv level is ensured to maintain the high level vdd_hv.

In the invention, the delay time of the first buffer BUF1 and the second buffer BUF2 is required to be more than half of the rising time of the two output ends from the low level to the high level, so that the high level voltages of the out_hv and the outb_hv are ensured to reach vdd_hv.

In the high-speed dual-level converter shown in fig. 4, the gate connection modes of the thirteenth PMOS transistor PM13, the fourteenth PMOS transistor PM14, the fifteenth PMOS transistor PM15, and the sixteenth PMOS transistor PM16 form cross positive feedback. Unlike the conventional level shifter shown in fig. 1, in the high-speed dual-level shifter provided by the invention, the charging of the two output ends to the high level (i.e., the inversion of the two output ends from the low level to the high level) is completed by the tenth PMOS tube PM10 and the eleventh PMOS tube PM11, and does not depend on the cross positive feedback structure. The tenth PMOS tube PM10 and the eleventh PMOS tube PM11 are automatically started to charge the two output ends fast according to the output signal states of the two output ends, so that high-speed overturning is realized. The cross positive feedback structure in the present invention only functions to maintain the two output voltages out_hv, outb_hv at the high level vdd_hv. Compared with the current mode evolution type high-speed level converter shown in fig. 2, the voltage of the two output end signals out_hv and outb_hv of the high-speed double-level converter provided by the invention can reach the high-voltage power supply voltage vdd_hv, and the later logic circuit has no leakage risk, so that no direct current exists and no direct current loss exists. Compared with the multi-level converter shown in fig. 3, the conversion circuit of the invention can realize high-speed level conversion without an intermediate power supply in the working process.

The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. The high-speed double-level converter is characterized by comprising two NMOS (N-channel metal oxide semiconductor) tubes, seven PMOS (P-channel metal oxide semiconductor) tubes and two buffers; a pair of low voltage differential signals in_lv and inb_lv are input to a pair of differential input terminals of the level shifter, and a pair of differential output terminals of the level shifter output a pair of high voltage differential signals outb_hv and out_hv;

the grid electrode of the sixth NMOS tube is used as a first input end, and the grid electrode of the seventh NMOS tube is used as a second input end; the source electrode of the sixth NMOS tube and the source electrode of the seventh NMOS tube are grounded; the drain electrode of the sixth NMOS tube is connected with the input end of the first buffer, the drain electrode of the thirteenth PMOS tube, the drain electrode of the fourteenth PMOS tube, the grid electrode of the fifteenth PMOS tube, the grid electrode of the sixteenth PMOS tube and the first output end; the drain electrode of the seventh NMOS tube is connected with the input end of the second buffer, the drain electrode of the sixteenth PMOS tube, the drain electrode of the fifteenth PMOS tube, the grid electrode of the thirteenth PMOS tube, the grid electrode of the fourteenth PMOS tube and the second output end;

the source electrode of the thirteenth PMOS tube is connected with the drain electrode of the tenth PMOS tube PM 10; the source electrode of the sixteenth PMOS tube is connected with the drain electrode of the eleventh PMOS tube; the grid electrode of the tenth PMOS transistor is connected with the output end of the first buffer; the grid electrode of the eleventh PMOS tube is connected with the output end of the second buffer;

the source electrode of the fourteenth PMOS tube and the source electrode of the fifteenth PMOS tube are connected with the drain electrode of the twelfth PMOS tube; the grid electrode of the twelfth PMOS tube is connected with a low-voltage power supply;

the source electrode of the tenth PMOS transistor, the source electrode of the eleventh PMOS transistor and the source electrode of the twelfth PMOS transistor are all connected with high-voltage power supply voltage.

2. The high-speed bi-level converter of claim 1 wherein the drive current of the twelfth PMOS transistor satisfies the following four conditions simultaneously: the drain current of the first output end is larger than the drain current of the second output end.

3. The high-speed bi-level shifter of claim 1 wherein the first buffer, the second buffer have a delay greater than half the rise time of the two outputs toggling from low to high.

4. The high-speed bi-level converter of claim 2 wherein the drive current of the twelfth PMOS transistor is adjusted to meet the four conditions by adjusting an aspect ratio of a conductive channel of each MOS transistor.

5. The high-speed bi-level converter of claim 2 wherein the twelfth PMOS transistor is an inverted-ratio transistor, i.e., having a channel length greater than the channel width.

6. The high-speed bi-level converter of claim 1 wherein the twelfth PMOS transistor is changed to a resistor, in which case the low voltage power supply is omitted; one end of the resistor is connected with high-voltage power supply voltage, and the other end of the resistor is connected with the source electrode of the fourteenth PMOS tube and the source electrode of the fifteenth PMOS tube.

7. The high-speed bi-level converter of claim 1 wherein when out_hv is low and outb_hv is high, the tenth PMOS transistor is turned off and the eleventh PMOS transistor is turned on; when the out_hv is at a high level and the outb_hv is at a low level, the tenth PMOS tube is turned on, and the eleventh PMOS tube is turned off; the two output ends are turned from low level to high level and are completed by a tenth PMOS tube and an eleventh PMOS tube.

8. The high-speed bi-level converter of claim 1 wherein when in_lv is turned from low to high, inb_lv is turned from high to low, the seventh NMOS transistor NM7 is turned off, the sixth NMOS transistor NM6 is turned on and the twelfth PMOS transistor and the fourteenth PMOS transistor are overcome to weak drive current and discharge charge, the outb_hv drops rapidly to vss, and the first buffer output low drives the tenth PMOS transistor to be turned on; when the outb_hv is smaller than the threshold voltage of the vdd_hv-sixteenth NMOS transistor, the sixteenth PMOS transistor is conducted to charge out_hv, the out_hv rapidly reaches the high voltage vdd_hv, and the second buffer outputs high level to drive the eleventh PMOS transistor to be closed; the grid connection mode of the fourteenth PMOS tube and the fifteenth PMOS tube forms cross positive feedback, so that the out_hv is ensured to maintain high voltage vdd_hv.

9. The high-speed bi-level converter of claim 1 wherein when in_lv is turned from high to low, inb_lv is turned from low to high, the sixth NMOS transistor is turned off, the seventh NMOS transistor is turned on and the twelfth PMOS transistor is turned on against weak drive current and discharges charge, out_hv drops rapidly to vss, and the second buffer output low drives the eleventh PMOS transistor to turn on; when out_hv is smaller than the threshold voltage of the vdd_hv-thirteenth NMOS tube, the thirteenth PMOS tube is conducted to charge the outb_hv, the outb_hv rapidly rises to the high voltage vdd_hv, and the first buffer outputs high level to drive the tenth PMOS tube to be closed; the grid connection mode of the fourteenth PMOS tube and the fifteenth PMOS tube forms cross positive feedback, so that the outb_hv is ensured to maintain the high level vdd_hv.

10. The high-speed dual-level converter as set forth in claim 1, wherein gate connections of the thirteenth PMOS transistor, the fourteenth PMOS transistor, the fifteenth PMOS transistor, and the sixteenth PMOS transistor form a cross positive feedback for maintaining the voltages of the two output terminals at the high voltage supply voltage.