CN117690943A - Manufacturing method of image sensor - Google Patents

Abstract

The invention proposes a method for manufacturing an image sensor, which belongs to the field of semiconductor manufacturing technology and includes the following steps: providing a substrate, including a device area and a non-device area; forming a first oxide layer on the substrate, and covering the first oxide layer The device area extends to part of the non-device area; steps are formed on the substrate in the non-device area; a second oxide material layer is formed on the substrate, and the second oxide material layer covers the first oxide layer, the surface and sidewalls of the steps ; Forming a sacrificial layer on the surface of the second oxidized material layer; performing planarization processing on the sacrificial layer at least twice to remove the sacrificial layer and part of the thickness of the second oxidized material layer, and then performing polishing processing to form a second oxidized layer; in the first A bonding contact layer with high bonding strength is formed on the dioxide layer; the bonding contact layer is bonded to the carrier substrate to form an image sensor. The invention provides a method for manufacturing an image sensor, which can effectively improve the quality and yield of the image sensor.

Description

A method of manufacturing an image sensor

Technical field

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing an image sensor.

Background technique

The image sensor can convert the light signal shining on its own photosensitive surface into a corresponding electrical signal through photoelectric conversion, and output a corresponding image based on the converted electrical signal. It is widely used in various optoelectronic devices, such as digital cameras, Cameras, video recorders, fax machines, image scanners and digital televisions, etc. However, the production of image sensors has problems such as complex processes and low yield rates.

Contents of the invention

The present invention proposes a method for manufacturing an image sensor. The unexpected effect is that it can effectively reduce bubbles at the bonding interface, improve bonding quality, and thus improve the yield rate of the image sensor.

In order to solve the above technical problems, the present invention is implemented through the following technical solutions.

The present invention proposes a method for manufacturing an image sensor, which at least includes the following steps:

Provide a substrate, the substrate including a device area and a non-device area;

forming a first oxide layer on the substrate, the first oxide layer covering the device area and extending to part of the non-device area;

forming steps on the substrate in the non-device area;

forming a second oxide material layer on the substrate, the second oxide material layer covering the first oxide layer, the surface and sidewalls of the steps;

Form a sacrificial layer on the surface of the second oxidized material layer;

Perform planarization processing on the sacrificial layer at least twice to remove the sacrificial layer and part of the thickness of the second oxide material layer, and then perform polishing processing to form a second oxide layer;

forming a bonding contact layer with high bonding strength on the second oxide layer; and

The bonding contact layer is bonded to the carrier substrate to form an image sensor.

Further, the bonding contact layer is formed using a high-density plasma chemical vapor deposition process.

Further, the pressure applied by the polishing process is half of the pressure applied by the planarization process.

Further, the step of forming the second oxide layer includes:

Form a first sacrificial layer on the surface of the second oxidized material layer;

Perform a first planarization process on the first sacrificial layer to remove part of the thickness of the first sacrificial layer to form a second sacrificial layer;

Perform a second planarization process on the second sacrificial layer to remove the second sacrificial layer and part of the thickness of the second oxide material layer to form an intermediate oxide material layer; and

A first polishing process is performed on the intermediate oxide material layer to remove part of the thickness of the intermediate oxide material layer to form a second oxide layer, and the surface of the second oxide layer is smooth.

Further, the thickness of the first polishing process is 70nm-90nm, and the processing time is 57s-67s.

Further, after the first polishing process, the surface roughness of the second oxide layer is 0.1nm-0.3nm.

Further, the step of forming the bonding contact layer includes:

Form a bonding material layer on the surface of the second oxide layer;

The bonding material layer is polished for a second time to remove part of the thickness of the bonding material layer to form a bonding contact layer.

Further, the thickness of the bonding material layer is 90nm-110nm.

Further, the thickness of the second polishing process is 50nm-70nm, and the processing time is 57s-67s.

Further, after the second polishing process, the surface roughness of the bonding contact layer is 0.1nm-0.3nm.

Further, the manufacturing method further includes: after forming the bonding contact layer, performing particle removal and cleaning on the substrate.

The present invention proposes a method for manufacturing an image sensor. By adding polishing treatment after planarization, the unexpected effects are: simplifying the process flow, greatly reducing process time, and improving production efficiency; and the formed bonding interface film layer is uniform It has high properties, good density, high surface roughness and high bonding strength, which reduces the generation of bubbles during the bonding process and improves the quality of the bonding between the image sensor and the carrier substrate, thus improving the reliability and yield rate of the image sensor. .

Description of the drawings

FIG. 1 is a flow chart of a manufacturing method of an image sensor in the present invention.

FIG. 2 is a schematic structural diagram of the first oxide material layer in an embodiment of the present invention.

Figure 3 is a schematic structural diagram of a grinding unit in an embodiment of the present invention.

Figure 4 is a schematic structural diagram of a step in an embodiment of the present invention.

FIG. 5 is a schematic structural diagram of the second oxide material layer in an embodiment of the present invention.

FIG. 6 is a schematic structural diagram of the first sacrificial layer in an embodiment of the present invention.

FIG. 7 is a schematic structural diagram of the second sacrificial layer in an embodiment of the present invention.

FIG. 8 is a schematic structural diagram of the intermediate oxide material layer in an embodiment of the present invention.

FIG. 9 is a schematic structural diagram of the second oxide layer in an embodiment of the present invention.

Figure 10 is a schematic structural diagram of the bonding material layer in an embodiment of the present invention.

FIG. 11 is a schematic structural diagram of a bonding contact layer in an embodiment of the present invention.

FIG. 12 is a schematic diagram of bonding between a CMOS transistor and a carrier substrate in an embodiment of the present invention.

FIG. 13 is an electron micrograph of an image sensor produced in another embodiment of the present invention.

FIG. 14 is an electron micrograph of an image sensor produced in an embodiment of the present invention.

Picture description:

100. Substrate; 110. Step; 200. First oxide material layer; 210. First oxide layer; 300. Second oxide material layer; 310. Intermediate oxide material layer; 320. Second oxide layer; 400. First Sacrificial layer; 410, second sacrificial layer; 500, bonding material layer; 510, bonding contact layer; 511, contact surface; 600, bearing substrate; 601, bonding surface; 700, rotation axis; 800, grinding blade.

Detailed ways

The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. The drawings only show the components related to the present invention and do not follow the actual implementation of the component numbers, shapes and components. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be arbitrarily changed, and the component layout type may also be more complex.

The technical solution of the present invention will be further described in detail below with reference to several embodiments and drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without any creative work fall within the scope of protection of the present invention.

The backside illuminated image sensor (Back side Illuminated Complementary Metal Oxide Semiconductor, BSI CMOS) has a metal interconnection layer and a photosensitive layer respectively placed on both sides of the substrate to avoid refraction and obstruction of incident light by the metal interconnection layer. Compared with front side illumination CMOS (FSI CMOS), it has better quantum efficiency and angular responsivity, making back-illuminated image sensors gradually occupy an important position in industrial applications and is widely used in digital cameras, In fields such as interchangeable lens digital cameras and smartphones, during the preparation process of back-illuminated image sensors, CMOS transistors need to be bonded to a carrier substrate. This application proposes a method for manufacturing an image sensor, which can effectively reduce bubbles at the bonding interface between the CMOS transistor and the carrier substrate, improve the bonding quality of the image sensor, and improve the performance of the back-illuminated image sensor.

Please refer to Figures 1 and 2. In step S10, in an embodiment of the present invention, a substrate 100 is first provided, and a semiconductor device is fabricated on the substrate 100 to form a device area (not shown in the figure). A region where a semiconductor device is not fabricated is defined as a non-device region (not shown in the figure), and the non-device region is, for example, provided around the device region. Taking the substrate 100 for manufacturing the device as an example, the manufacturing process of the back-illuminated image sensor will be described. The present invention does not limit the type of substrate, and different types of substrates can be selected according to the production of different types of semiconductor devices. In an embodiment of the present invention, the substrate 100 may be a silicon (Si) substrate, for example, to produce a complementary metal oxide semiconductor transistor (CMOS). In an embodiment of the present invention, before fabricating the device, the substrate 100 is doped to reduce the resistance of the substrate 100 and prevent the latch-up effect. In an embodiment of the present invention, the substrate 100 is doped with boron (B) or gallium (Ga) to form a P-type doped substrate.

Please refer to FIGS. 1 and 2 . In step S10 , in an embodiment of the present invention, after fabricating a device on a substrate 100 , two or even multiple substrates 100 are bonded together. In one embodiment of the present invention, the manufacturing process of the back-illuminated image sensor is explained by taking the bonding of the substrate 100 in which the CMOS transistor is manufactured and a carrier substrate as an example.

Please refer to FIGS. 1 and 2 . In step S20 , in an embodiment of the present invention, a first oxide material layer 200 is first formed on the substrate 100 on which the CMOS transistor is fabricated. The first oxide material layer 200 covers the entire Device and non-device areas and sidewalls of the substrate 100 . In an embodiment of the present invention, the first oxide material layer 200 is, for example, dense silicon oxide or other materials. The present invention is not limited to the method of forming the first oxidized material layer 200. In this embodiment, for example, the first oxidized material layer 200 is formed using High Density Plasma Chemical Vapor Deposition (HDPCVD). The thickness of the first oxide material layer 200 is, for example, 350 nm-400 nm, specifically, it is 360 nm, 380 nm, or 400 nm.

Please refer to FIG. 1 , FIG. 3 and FIG. 4 . In step S30 , in an embodiment of the present invention, after the first oxide material layer 200 is formed, for example, a chemical mechanical polishing (CMP) process may be used. The substrate 100 in the non-device area is edge trimmed to form steps 110 to reduce edge defects and improve device reliability. Trimming can be done in two steps, such as surface grinding and edge cutting. Specifically, a chemical mechanical polishing process is used to plane grind the entire first oxidized material layer 200 to make the surface of the first oxidized material layer 200 flat and ensure that the depth of edge cutting remains consistent. After the first oxide material layer 200 is plane ground, the edge of the substrate 100 is ground and cut using the grinding unit in FIG. 3 . The grinding unit includes a grinding blade 800 and a rotating shaft 700. The grinding blade 800 is fixed on the rotating shaft 700. The rotating shaft 700 drives the grinding blade 800 to rotate in the vertical direction, and the substrate 100 rotates in the horizontal direction. The grinding blade 800 and the substrate 100 The edges of the substrate 100 are contacted and grinded and cut to remove the first oxide material layer 200 covering the edges of the substrate 100 and part of the substrate 100 to form steps 110 . During the trimming process, the first oxide material layer 200 on the side of the substrate 100 is simultaneously removed to form the first oxide layer 210 . The substrate 100 is trimmed using a chemical mechanical polishing process. The process flow is simple and the process time is greatly shortened, which effectively improves production efficiency.

Please refer to Figures 3 and 4. In an embodiment of the present invention, the depth h of the step 110 is, for example, 140 μm-160 μm, specifically, it is 140 μm, 150 μm or 160 μm, etc., and the width d of the step 110 is, for example, 1.3 mm-160 μm. 1.5mm, for example, 1.3mm, 1.4mm or 1.5mm. By setting the size of the step 110 within the above range, abnormalities in the device area on the substrate 100 can be effectively prevented during subsequent deposition of the bonding interface film layer.

Please refer to FIG. 1, FIG. 4 and FIG. 5. In step S40, in an embodiment of the present invention, after forming the step 110, for example, plasma enhanced chemical vapor deposition (Plasma Enhanced CVD, PECVD) is used to deposit the positive Using Tetraethylorthosilicate (TEOS) technology, the second oxide material layer 300 is formed on the surface of the first oxide layer 210 and the surface and side walls of the step 110 . Specifically, for example, using tetraethyl orthosilicate (TEOS) and oxygen (O ₂ ) as raw materials, the second oxide material layer 300 is deposited on the surface of the step 110 . In one embodiment of the present invention, the flow rate of the tetraethyl orthosilicate liquid introduced is, for example, 500 mgm-1000 mgm, and the ethyl orthosilicate liquid is vaporized, and the temperature of the vaporization treatment is, for example, 100°C-120°C. Then, the ethyl orthosilicate gas is transported into the reaction chamber through an inert gas, such as helium, and oxygen is introduced into the reaction chamber. Radio frequency is used to dissociate ethyl orthosilicate gas and oxygen in the chamber, and react to generate silicon dioxide. In an embodiment of the present invention, the gas flow rate of oxygen can be set to 2000 sccm-3000 sccm, for example, and the radio frequency power can be set to 400W-800W, for example. In one embodiment of the present invention, the reaction pressure in the reaction chamber is, for example, 7T-9T, and the reaction temperature is, for example, 400°C-420°C. Further, the reaction pressure is 8T, and the reaction temperature is 410°C. The formed second oxide material layer 300 has good coverage and high mobility on the TEOS surface, which can avoid the generation of low-density areas or voids. And the second oxide material layer 300 is formed through a plasma enhanced ethyl orthosilicate film (PETEOS) process, which reduces the temperature of depositing the second oxide material layer 300 and ensures the film quality of the second oxide material layer 300, thereby improving the performance of the second oxide material layer 300. The quality of other film layers formed on the surface of the dioxide material layer 300. In an embodiment of the present invention, the thickness of the second oxide material layer 300 is, for example, 1400nm-1450nm, specifically, it is 1420nm, 1440nm or 1450nm.

Please refer to FIG. 1, FIG. 5 and FIG. 6. In step S50, in one embodiment of the present invention, after forming the second oxide material layer 300, for example, using a plasma enhanced ethyl orthosilicate film process, A first sacrificial layer 400 is formed on the surface of the second oxide material layer 300. In an embodiment of the present invention, the first sacrificial layer 400 is made of, for example, dense silicon oxide and other materials, and the thickness of the first sacrificial layer 400 is, for example, 1180 nm-1220 nm, specifically, for example, 1190 nm, 1200 nm, or 1210 nm. Two plasma-enhanced ethyl orthosilicate film processes are used to form the second oxidized material layer 300 and the first sacrificial layer 400 respectively, while ensuring that the overall thickness and strength of the second oxidized material layer 300 and the first sacrificial layer 400 remain unchanged. , while improving the coverage uniformity of the oxide layer and improving the overall quality of the oxide layer. In the fabricated CMOS transistor, the depth of the cutting channel between the exposure area (shot) is about 500nm, and the overall thickness of the second oxide material layer 300 and the first sacrificial layer 400 is controlled to 2500nm-2700nm. Fully fill the cutting trench between shot and shot to prevent bubbles from appearing during the subsequent bonding process between the CMOS transistor and the carrier substrate.

Please refer to FIGS. 1, 5 and 6. In step S50, in an embodiment of the present invention, after forming the first sacrificial layer 400, the substrate 100 is annealed to improve the second oxide material layer 300. and the quality of the first sacrificial layer 400, and further reduce the interface charge. In one embodiment of the present invention, the flow of oxygen and TEOS into the chamber is stopped, nitrogen is injected into the chamber, and then the temperature of the substrate 100 is maintained at 380°C-420°C, and the second oxide material layer on the substrate 100 is 300 and the first sacrificial layer 400 are annealed to improve the density of the oxide layer and the bonding strength between the oxide layers.

Please refer to FIG. 1, FIG. 6 to FIG. 7. In step S60, in an embodiment of the present invention, after the substrate 100 is annealed, for example, the first sacrificial layer 400 on the substrate 100 is subjected to a first step. Secondary flattening process. In one embodiment of the present invention, for example, a chemical mechanical polishing (CMP) process is used to perform the first planarization process. The polishing pad used is, for example, a hard pad, and the service life of the hard pad is, for example, greater than 25 hours. This improves the efficiency of the chemical mechanical polishing process. quality, thereby improving the production yield of semiconductor structures. In one embodiment of the present invention, for example, the grinding unit in FIG. 3 is used to perform a first planarization process on the first sacrificial layer 400 on the substrate 100 to remove part of the thickness of the first sacrificial layer 400 . In an embodiment of the present invention, for example, the substrate 100 is divided into a device area and a non-device area, where the area close to the center of the substrate 100 is the device area, and the area close to the edge of the substrate 100 is the non-device area. And during the first planarization process, the pressure in the device area is set to 2mT-4mT, for example, the pressure in the area inside the non-device area is set to 6mT-8mT, and the pressure in the area outside the non-device area is set to 8mT, for example. -10mT. When depositing a film layer, the accumulation of the film layer in the area at the edge of the substrate 100 causes the actual deposited thickness to be greater than the preset thickness. By setting a higher pressure on the area at the edge of the substrate 100 , the surface of the substrate 100 is ensured after polishing. Keep it flat. In one embodiment of the present invention, the first planarization process is performed in three stages, for example, and the first stage is for example grinding for 45s-55s, the second stage is for example grinding for 45s-55s, and the third stage is for example grinding for 45s-55s. In an embodiment of the present invention, the thickness of the first planarization process is, for example, 800nm-1000nm, specifically, 800nm, 900nm or 1000nm, etc., and the width is, for example, 1.3mm-1.5mm. After the first sacrificial layer 400 is subjected to the first planarization process, the second sacrificial layer 410 is formed.

Please refer to FIG. 1 and FIG. 8 . In step S60 , in an embodiment of the present invention, after forming the second sacrificial layer 410 , the second sacrificial layer 410 is planarized for a second time using, for example, a CMP process. The polishing pad is, for example, a hard pad, and the service life of the hard pad is, for example, greater than 25 hours. In one embodiment of the present invention, for example, the grinding unit in FIG. 3 is used to perform a second planarization process on the second sacrificial layer 410 to remove the second sacrificial layer 410 and part of the thickness of the second oxide material layer 300 to form an intermediate layer. Oxide material layer 310. During the second planarization process, the pressure in the device area is set to, for example, 2mT-4mT, the pressure in the area inside the non-device area is set to, for example, 6mT-8mT, and the pressure in the area outside the non-device area is set to, for example, 8mT-8mT. 10mT. In one embodiment of the present invention, the second planarization process is performed in three stages, for example, and the first stage is for example grinding for 45s-55s, the second stage is for example grinding for 45s-55s, and the third stage is for example grinding for 45s-55s. In an embodiment of the present invention, the thickness of the second planarization process is, for example, 800nm-1000nm, specifically, 800nm, 900nm or 1000nm, etc., and the width is, for example, 1.3mm-1.5mm.

Please refer to Figure 1, Figure 8 and Figure 9. In step S60, in an embodiment of the present invention, an intermediate oxide material layer 310 is formed, and the first polishing process is continued on the intermediate oxide material layer 310 to remove part of the thickness. The middle oxide material layer 310 forms a second oxide layer 320. In one embodiment of the present invention, for example, a buffing CMP process is used to perform the first polishing process, and the pressure applied to the substrate 100 during the polishing process is the pressure applied to the substrate 100 during the planarization process. During the first polishing process, the pressure in the device area is set to 1mT-2mT, for example, the pressure in the area inside the non-device area is set to 3mT-4mT, and the pressure in the area outside the non-device area is set to 4mT-5mT, for example. . In one embodiment of the present invention, the first polishing process is performed in three stages, for example, and the first stage is for example polishing for 1 s, the second stage is for example polishing for 1 s, and the third stage is for example polishing for 55s-65s. In an embodiment of the present invention, the thickness of the first polishing process is, for example, 50nm-70nm, specifically, 50nm, 60nm or 70nm, etc., and the width is, for example, 1.3mm-1.5mm. In one embodiment of the present invention, the polishing pad used in the first polishing process is, for example, a non-woven polishing pad. Compared with hard pads, non-woven fabrics are soft and have excellent surface smoothness, and are less sensitive to oxidized materials during polishing. Layer scratches are minor. In one embodiment of the present invention, before the first polishing process, the surface roughness of the second oxide layer 320 is, for example, 0.4nm-0.6nm. After the first polishing process, the surface roughness of the second oxide layer 320 is, for example, It is 0.1nm-0.3nm, and for example, it is 0.2nm. Through the buffering CMP process, defects such as micro scratches and roughness on the surface of the oxidized material layer can be improved, making the surface of the second oxide layer 320 flat and smooth, thus ensuring the uniformity and deposition quality of subsequent film deposition. .

Referring to FIG. 1 , FIG. 9 and FIG. 10 , in step S70 , in an embodiment of the present invention, after forming the second oxide layer 320 , a bonding material layer 500 is formed on the surface of the second oxide layer 320 . And the bonding material layer 500 is, for example, dense silicon oxide or other materials. The present invention does not limit the formation method of the bonding material layer 500. In this embodiment, for example, the bonding material layer 500 is formed by using High Density Plasma Chemical Vapor Deposition (HDPCVD), and HDPCVD During the process, only deposition is performed without sputter etching, thereby improving the deposition efficiency of the bonding material layer 500 and improving the coverage effect of the bonding material layer 500 on the steps 110, thereby further enhancing the lining. The bonding strength of the bonding interface film layer of the bottom 100 is beneficial to improving the bubble enhancement effect caused by rapid annealing during the subsequent bonding process between the CMOS transistor and the carrier substrate. In an embodiment of the present invention, the thickness of the bonding material layer 500 is, for example, 90 nm-110 nm, specifically, it is 90 nm, 100 nm, or 110 nm. And in one embodiment of the present invention, by configuring the first polishing process, the second oxide layer 320 formed by TEOS technology and the bonding material layer 500 formed by HDPCVD technology are prevented from being separated in the subsequent packaging and cutting steps, thereby improving improve the image sensor yield.

Please refer to Figure 1, Figure 10 and Figure 11. In step S80, in an embodiment of the present invention, after forming the bonding material layer 500, the bonding material layer 500 is polished for a second time to remove part of the bonding material layer 500. The thick bonding material layer 500 forms a bonding contact layer 510, and the bonding contact layer 510 has high bonding strength. In an embodiment of the present invention, for example, a buffingCMP process is used to perform the second polishing process. During the second polishing process, the pressure in the device area is set to 1mT-2mT, for example, the pressure in the area inside the non-device area is set to 3mT-4mT, and the pressure in the area outside the non-device area is set to 4mT-5mT, for example. . In an embodiment of the present invention, the second polishing process is performed in three stages, for example, and the first stage is polishing for 1 s, the second stage is polishing for 1 s, and the third stage is polishing for 55 s-65 s. In an embodiment of the present invention, the thickness of the second polishing process is, for example, 50nm-70nm, specifically, 50nm, 60nm or 70nm, etc., and the width is, for example, 1.3mm-1.5mm. In one embodiment of the present invention, the polishing pad used in the first polishing process is, for example, a non-woven polishing pad. Compared with hard pads, non-woven fabrics are soft and have excellent surface smoothness. During polishing, the material layer is The scratches are minor. In an embodiment of the present invention, the roughness of the surface of the bonding contact layer 510 before the second polishing process is, for example, 0.4nm-0.6nm. After the second polishing process, the roughness of the surface of the bonding contact layer 510 is, for example, 0.1nm-0.3nm, another example is 0.2nm. Through the buffering CMP process, defects such as micro scratches and roughness on the surface of the material layer can be improved, thereby further enhancing the flatness and roughness of the bonding contact layer 510 and further enhancing the bonding contact layer 510 . Bonding strength, thereby suppressing the bubble enhancement effect caused by rapid annealing during the bonding process, thereby improving the bonding quality of the CMOS transistor and the carrier substrate, and improving the yield of the image sensor.

Please refer to FIG. 1 , FIG. 10 and FIG. 11 . In an embodiment of the present invention, after the bonding contact layer 510 is formed, the substrate 100 is subjected to particle removal and cleaning. Further, for example, an RCA cleaning process is used to clean the substrate 100 to remove a large number of particles generated during multiple chemical mechanical polishing processes to prevent device contamination.

Please refer to FIG. 1, FIG. 10 to FIG. 12. In step S80, in an embodiment of the present invention, after forming the bonding contact layer 510, the substrate 100 on which the CMOS transistor is fabricated is turned over, so that the bonding contact layer 510 is formed. 510 is close to the carrier substrate 600, and uses a low-temperature fusion bonding process to bond the substrate 100 and the carrier substrate 600 to produce a back-illuminated image sensor. Specifically, a plasma activation process is performed on the contact surface 511 on the bonding contact layer 510 and the bonding surface 601 of the carrier substrate 600. The reaction gas used includes one or more of Ar, _N2 , _O2 and _SF6. kind. By contacting the contact surface 511 on the bonding contact layer 510 with the bonding surface 601 of the carrier substrate 600, the substrate 100 and the carrier substrate 600 are bonded. During the bonding process, the bonding pressure applied is, for example, 1N-10N. The bonding time is, for example, 10s-60s, and the bonding temperature is, for example, 10°C-50°C. The bonded substrate 100 and the carrier substrate 600 are annealed. The annealing temperature is, for example, 300° C. to 400° C., and the annealing time is, for example, 40 min to 80 min. Controlling the annealing time within the above range can effectively improve the bonding quality of the substrate 100 and the carrier substrate 600. The annealing time process will cause the bonding bubbles to continue to grow, resulting in a change in the fit between the substrate 100 and the carrier substrate 600. Difference. After the annealing is completed, the substrate 100 is thinned, and processes such as microlenses and filter layers are performed to form a back-illuminated image sensor.

Please refer to Figures 13 and 14. In one embodiment of the present invention, Figure 13 shows another embodiment. After the second planarization process, a low deposition Tetraethylorthosilicate film (Low deposition Tetraethylorthosilicate, The electron microscopy of the back-illuminated image sensor produced by the method of depositing the bonding interface layer using the LDTEOS process. Figure 14 is the electron microscopy of the back-illuminated image sensor produced by the manufacturing method of the image sensor provided in this embodiment. picture. Combining Figures 13 and 14, it can be seen that the bonding bubbles in the back-illuminated image sensor produced using the image sensor production method provided by the present invention are greatly reduced, thus ensuring the reliability and yield of the image sensor.

To sum up, the present invention proposes a method for manufacturing an image sensor, which simplifies the process flow, reduces the number of annealing and other processes, reduces the process time, and greatly improves production efficiency. By forming steps on the substrate, the unexpected effect is to reduce chipping defects during the bonding process. The bonding material layer is formed through the HDPCVD process. The unexpected effect is to enhance the bonding strength of the bonding interface film layer of the substrate, which is beneficial to improving the bubble enhancement caused by rapid annealing during the subsequent bonding process of the CMOS transistor and the carrier substrate. effect. By adding the buffingCMP process after the CMP oxide layer removal process, the unexpected effect is to improve the fine scratches and surface roughness on the oxide layer surface. By adding the buffering CMP process after the bonding material layer is formed by the HDPCVD process, the unexpected effect is to improve the fine scratches and surface roughness of the bonding interface film layer, and improve the flatness and roughness of the bonding interface film layer. degree, and further increases the bonding strength, thereby suppressing the bubble enhancement effect caused by rapid annealing during the bonding process, thereby reducing the generation of bubbles during the bonding process, and improving the quality of the bonding between the CMOS transistor and the carrier substrate. Thereby improving the reliability and yield rate of the image sensor.

The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to technical solutions formed by specific combinations of the above technical features. , it should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are similar to those disclosed in this application (but not limited to). A technical solution formed by replacing the technical features of functions with each other.

Except for the technical features described in the description, the remaining technical features are known to those skilled in the art. In order to highlight the innovative features of the present invention, the remaining technical features will not be described in detail here.

Claims (10)

1. A method for manufacturing an image sensor, comprising at least the steps of:

providing a substrate, wherein the substrate comprises a device region and a non-device region;

forming a first oxide layer on the substrate, wherein the first oxide layer covers the device region and extends to part of the non-device region;

forming a step on the substrate of the non-device region;

forming a second oxide material layer on the substrate, wherein the second oxide material layer covers the first oxide layer, the surface of the step and the side wall;

forming a sacrificial layer on the surface of the second oxide material layer;

flattening the sacrificial layer at least twice to remove the sacrificial layer and part of the second oxide material layer, and polishing to form a second oxide layer;

forming a bonding contact layer on the second oxide layer; and

and bonding the bonding contact layer with the bearing substrate to form the image sensor.

2. The method of claim 1, wherein the bonding contact layer is formed by high-density plasma chemical vapor deposition.

3. The method of claim 1, wherein the polishing process applies a pressure that is half of the pressure applied by the planarization process.

4. The method of manufacturing an image sensor of claim 1, wherein the step of forming the second oxide layer comprises:

forming a first sacrificial layer on the surface of the second oxide material layer;

carrying out first planarization treatment on the first sacrificial layer to remove part of the thickness of the first sacrificial layer and form a second sacrificial layer;

performing a second planarization treatment on the second sacrificial layer to remove the second sacrificial layer and a part of the second oxide material layer with the thickness to form an intermediate oxide material layer; and

and performing first polishing treatment on the intermediate oxide material layer to remove part of the thickness of the intermediate oxide material layer, so as to form a second oxide layer, wherein the surface of the second oxide layer is smooth.

5. The method of manufacturing an image sensor according to claim 4, wherein the first polishing process is performed at a thickness of 70nm to 90nm for a period of 57s to 67s.

6. The method of manufacturing an image sensor according to claim 4, wherein the roughness of the surface of the second oxide layer after the first polishing process is 0.1nm to 0.3nm.

7. The method of manufacturing an image sensor of claim 4, wherein the step of forming the bonding contact layer comprises:

forming a bonding material layer on the surface of the second oxide layer;

and performing secondary polishing treatment on the bonding material layer to remove part of the bonding material layer to form a bonding contact layer.

8. The method of claim 7, wherein the bonding material layer has a thickness of 90nm-110nm.

9. The method of manufacturing an image sensor according to claim 7, wherein the roughness of the surface of the bonding contact layer after the second polishing process is 0.1nm to 0.3nm.

10. The method of manufacturing an image sensor of claim 7, further comprising: and after the bonding contact layer is formed, carrying out particle removal and cleaning treatment on the substrate.