CN117677275A - Semiconductor structure, manufacturing method thereof and memory - Google Patents

Abstract

The embodiment of the disclosure provides a semiconductor structure, a manufacturing method thereof and a memory, wherein the manufacturing method of the semiconductor structure comprises the following steps: a substrate; a magnetic tunnel junction stack structure on the substrate, comprising: the device comprises a fixed layer, a bottom barrier layer positioned on the fixed layer, and a plurality of free layers and barrier layers which are sequentially and alternately laminated on the bottom barrier layer; and a conductive layer covering a portion of a sidewall of the magnetic tunnel junction stack structure, at least a portion of the free layer in the magnetic tunnel junction stack structure being electrically connected by the conductive layer.

Description

Semiconductor structure, manufacturing method thereof and memory

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure, a method of manufacturing the same, and a memory.

Background

A magnetic Random Access Memory (MRAM, magnetoresistive Random Access Memory) is a Non-Volatile Magnetic Random Access Memory (MRAM) that has high-speed read-write capability of a Static Random Access Memory (SRAM) and high integration of a dynamic Random Access Memory (DRAM, dynamic Random Access Memory) and can be rewritten substantially indefinitely. The structure of the magnetic random access memory is mainly composed of a stacked structure of a Transistor (T, transistor) and a magnetic tunnel junction (MTJ, magnetic Tunnel Junction). However, with the miniaturization of memory devices, there are problems with the magnetic tunnel junction stack structure.

Disclosure of Invention

In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, and a memory.

An aspect of an embodiment of the present disclosure provides a semiconductor structure, including:

a substrate;

a magnetic tunnel junction stack structure on the substrate, comprising: the device comprises a fixed layer, a bottom barrier layer positioned on the fixed layer, and a plurality of free layers and barrier layers which are sequentially and alternately laminated on the bottom barrier layer; and

and a conductive layer covering a portion of the sidewall of the magnetic tunnel junction stack structure, at least a portion of the free layer in the magnetic tunnel junction stack structure being electrically connected by the conductive layer.

In the scheme, the side wall of the conductive layer is flush with the side wall of the fixed layer and the side wall of the bottom barrier layer.

In the above scheme, the side wall of the conductive layer is flush with the side wall of the fixed layer, the side wall of the bottom barrier layer and the side wall of the substrate.

In the above scheme, the conductive layer is located on the bottom barrier layer and covers all the free layers and the sidewalls of the barrier layer in the magnetic tunnel junction stack structure.

In the above scheme, the conductive layer is located on the bottommost free layer of the alternately stacked free layers and barrier layers and covers the sidewalls of the remaining free layers and barrier layers in the magnetic tunnel junction stack structure.

In the above aspect, the semiconductor structure further includes: and the insulating layer is positioned between the conductive layer and the bottom barrier layer, and the top surface of the insulating layer is higher than the top surface of the bottommost free layer in the free layer and the barrier layer which are alternately stacked.

In the above-described aspect, the top surface of the insulating layer is lower than the top surface of the bottommost barrier layer of the free layers and the barrier layers that are alternately stacked.

In the above scheme, the side wall of the insulating layer is flush with the side wall of the conductive layer, and the insulating layer is connected with a part of the free layer, the dimension of the insulating layer along the preset direction is greater than or equal to the dimension of the conductive layer along the preset direction, and the preset direction is perpendicular to the stacking direction of the free layer and the barrier layer.

In the above aspect, the material of the conductive layer includes at least one of tantalum, tungsten, copper, or titanium nitride.

In the above aspect, the semiconductor structure further includes: a cap layer on the magnetic tunnel junction stack structure; the conductive layer covers the sidewalls of the cap layer.

In the above aspect, the semiconductor structure further includes: and the bit line is positioned on the cap layer and the conductive layer and is electrically connected with the conductive layer.

In the above aspect, the semiconductor structure further includes: and the side wall protection layer is used for coating the conductive layer, the magnetic tunnel junction laminated structure, the cap layer and the bit line.

In the above aspect, the semiconductor structure further includes: and the buffer layer is positioned between the substrate and the fixed layer, and the side wall of the buffer layer is flush with the side wall of the substrate.

An aspect of an embodiment of the present disclosure provides a memory, including: one or more semiconductor structures as described in the above embodiments of the present disclosure.

An aspect of an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:

providing a substrate;

forming a magnetic tunnel junction stack structure on the substrate; forming the magnetic tunnel junction stack structure includes: forming a fixed layer, forming a bottom barrier layer on the fixed layer, and sequentially forming a plurality of free layers and barrier layers which are alternately stacked on the bottom barrier layer;

a conductive layer is formed overlying a portion of the sidewalls of the magnetic tunnel junction stack, at least a portion of the free layer in the magnetic tunnel junction stack being electrically connected by the conductive layer.

In the above aspect, the forming the magnetic tunnel junction stack structure includes:

Sequentially forming a fixed material layer, a bottom barrier material layer and a plurality of alternate free material layers and barrier material layers which are stacked;

removing portions of the alternating layers of free material and barrier material;

further removing part of the free material layers and barrier material layers except the bottommost free material layer in the rest of the plurality of alternating free material layers and barrier material layers, exposing part of the top surface of the bottommost free layer, and forming the barrier layer and the free layer;

after the conductive layer is formed, removing part of the fixed material layer and the bottom barrier material layer to obtain a fixed layer and a bottom barrier layer, so that the side wall of the fixed layer and the side wall of the bottom barrier layer are flush with the side wall of the conductive layer;

the forming of the conductive layer includes:

the conductive layer is formed on the exposed bottommost free layer to cover the remaining free layer and barrier layer.

In the above scheme, the method further comprises:

forming a buffer layer on the substrate before forming the magnetic tunnel junction stack structure;

forming the magnetic tunnel junction stack structure on the buffer layer;

forming a cap layer over the magnetic tunnel junction stack structure prior to forming the conductive layer;

Forming a conductive layer covering the cap layer sidewall and a portion of the sidewall of the magnetic tunnel junction stack structure;

forming a bit line on the conductive layer and the magnetic tunnel junction stack structure;

and forming a side wall protection layer which covers the conductive layer, the magnetic tunnel junction laminated structure, the cap layer and the bit line.

In various embodiments of the disclosure, a magnetic tunnel junction lamination structure is formed on a substrate, wherein the magnetic tunnel junction lamination structure comprises a fixed layer, a bottom barrier layer positioned on the fixed layer, and a plurality of free layers and barrier layers which are sequentially and alternately laminated on the bottom barrier layer; in addition, a conductive layer is disposed on a portion of the sidewall of the magnetic tunnel junction stack structure, the conductive layer electrically connecting at least a portion of the free layer in the magnetic tunnel junction stack structure. Thus, on one hand, by forming a plurality of free layers and barrier layers which are alternately stacked in the magnetic tunnel junction stacked structure, the magnetic tunnel junction stacked structure can be provided with a plurality of free layer and barrier layer interfaces, so that the magnetic tunnel junction stacked structure has higher thermal stability; on the other hand, the partial free layers in the magnetic tunnel junction laminated structure are electrically connected through the conductive layers, so that the Resistance of the magnetic tunnel junction laminated structure is equivalent to the Resistance in fewer barrier layers, even equivalent to the Resistance in the bottom barrier layer, and therefore the Resistance-Area product (RA) of the magnetic tunnel junction laminated structure is reduced, and the tunnel magnetoresistance ratio (TMR, tunnel Magnetoresistance Ratio) of the magnetic tunnel junction laminated structure is further increased, that is, the semiconductor structure provided by the embodiment of the disclosure has higher thermal stability and higher tunnel magnetoresistance ratio.

Drawings

FIGS. 1 a-1 c are schematic diagrams of architectures of three MRAM transistors provided in embodiments of the disclosure;

FIG. 2 is a schematic diagram of a circuit connection of an MRAM transistor provided in an embodiment of the disclosure;

FIGS. 3 a-3 c are schematic diagrams of three magnetic tunnel junction stacks with different numbers of contact interfaces provided in embodiments of the present disclosure;

FIG. 4 is a graph showing the trend of thermal stability of magnetic tunnel junction stack structures with different numbers of contact interfaces provided in embodiments of the present disclosure;

FIG. 5 is a graph showing the trend of the magnetoresistance ratio of magnetic tunnel junction stack structures with different numbers of contact interfaces provided in embodiments of the present disclosure;

FIG. 6 is a semiconductor structure provided in an embodiment of the present disclosure in which a conductive layer covers a portion of the sidewalls of the free layer and barrier layer;

FIG. 7a is a semiconductor structure provided in an embodiment of the present disclosure in which a conductive layer covers sidewalls of all free layers and barrier layers;

FIG. 7b is a semiconductor structure with another conductive layer provided in an embodiment of the present disclosure covering sidewalls of all the free layers and barrier layers;

FIG. 8a is a semiconductor structure having an insulating layer and a conductive layer not flush with a sidewall of a substrate provided in an embodiment of the present disclosure;

Fig. 8b is a semiconductor structure having an insulating layer and a conductive layer flush with a sidewall of a substrate provided in an embodiment of the present disclosure;

FIG. 9a is another semiconductor structure provided in an embodiment of the present disclosure having an insulating layer and a conductive layer not flush with a sidewall of a substrate;

fig. 9b is another semiconductor structure provided in an embodiment of the present disclosure having an insulating layer and a conductive layer flush with a sidewall of a substrate;

FIG. 10a is a semiconductor structure with a bit line and a sidewall protection layer provided in an embodiment of the present disclosure;

FIG. 10b is another semiconductor structure with bit lines and sidewall spacers as provided in an embodiment of the present disclosure;

fig. 11 is a schematic flow chart of a manufacturing process of a semiconductor structure provided in an embodiment of the disclosure;

fig. 12 a-12 d are schematic cross-sectional views illustrating a process for fabricating a semiconductor structure according to an embodiment of the present disclosure.

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the disclosure.

It will be understood that the meanings of "on … …", "over … …" and "over … …" in this disclosure should be interpreted in the broadest manner so that "on … …" means not only that it is "on" something with no intervening features or layers therebetween (i.e., directly on something), but also that it is "on" something with intervening features or layers therebetween.

Further, spatially relative terms such as "on … …," "above … …," "above … …," "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated for ease of description. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In the presently disclosed embodiments, the term "substrate" refers to a material upon which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a variety of semiconductor materials, such as silicon, silicon germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

In the presently disclosed embodiments, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.

In the presently disclosed embodiments, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

Embodiments of the present disclosure relate to semiconductor structures that will be used in subsequent processes to form at least a portion of a final device structure. Here, the final device may include a memory including, but not limited to, a mram, which will be described below by way of example only. It should be noted, however, that the following description of the embodiments with respect to the magnetic random access memory is only for illustrating the present disclosure, and is not intended to limit the scope of the present disclosure.

Magnetic random access memory is well anticipated in terms of speed, area, number of writes, and power consumption, and is therefore considered by the industry as one of the potential access devices for building next generation nonvolatile caches and mainframes. With the development of magnetic random access memory technology, the array architecture goes from spin-transfer torque magnetic random access memory (STT-MRAM), with reference to fig. 1a, to voltage-controlled magnetic random access memory (VCMA-MRAM), with reference to fig. 1b, to spin-orbit torque magnetic random access memory (SOT-MRAM), with reference to fig. 1c. However, whether STT-MRAM or SOT-MRAM, the memory is composed of a plurality of memory cell structures, each of which is composed mainly of a transistor T and a memory cell (magnetic tunnel junction stack structure MTJ) operated by the transistor, that is, the magnetic random access memory includes at least a transistor T and a magnetic tunnel junction stack structure MTJ.

The MTJ of the magnetic tunnel junction stack structure is mainly composed of a three-layer structure: free Layer, fixed Layer and barrier Layer (also called Oxide Layer). The main action principle is that the magnetic moment directions of the free layer and the fixed layer are utilized to store information, when the magnetic moment directions of the free layer and the fixed layer are in a Parallel state (parallell), the resistance is low resistance, and '1' is written; when the magnetic moment direction of the free layer and the magnetic moment direction of the fixed layer are in a non-Parallel state (Anti-Parallel), the resistance is high, and "0" is written. In addition, the memory reading circuit judges the information of the memory by loading the same voltage to judge the magnitude of the output current, thereby completing the reading operation.

FIG. 2 is a schematic diagram of a control circuit of a MRAM according to an embodiment of the disclosure, wherein the gate of the transistor T is connected to a Word Line (WL) as shown in FIG. 2; the Source (drain) electrode of the transistor T is electrically connected to the fixed layer of the MTJ of the magnetic tunnel junction stack structure through a Source Line (SL), while the free layer of the MTJ is connected to a Bit Line (BL); by applying different voltages between the bit line BL and the source line SL, a write current (Iwrite) is generated through the magnetic tunnel junction stack MTJ, which changes the magnetization direction of the free layer of the magnetic tunnel junction stack MTJ, changes the tunneling resistance, and completes the storage of "0" and "1". The read mechanism of the magnetic random access memory circuit is that current flows from the bit line BL and is output through the Magnetic Tunnel Junction (MTJ) and the transistor (T) tube, and the voltage is also dependent on the resistance of the MTJ, and the output voltages generated under the same read current are different. It is possible to determine whether the data stored in the memory cell is "0" or "1" according to the output voltage.

However, with the miniaturization development of electronic products, it is difficult for the MTJ of the magnetic tunnel junction stack structure to have both high thermal stability and high tunnel magnetoresistance ratio.

Based on this, a semiconductor structure is proposed in an embodiment of the present disclosure, referring to fig. 3 a-3 c, the semiconductor structure comprising:

a substrate 301;

a magnetic tunnel junction stack structure 302 on the substrate 301, comprising: a fixed layer 3021, a bottom barrier layer 3022 on the fixed layer 3021, and a plurality of free layers 3023 and barrier layers 3024 stacked alternately in this order on the bottom barrier layer 3022; and

a conductive layer 303 covering a portion of the sidewalls of the magnetic tunnel junction stack structure 302, at least a portion of the free layer 3023 in the magnetic tunnel junction stack structure 302 being electrically connected by the conductive layer 303.

Referring to fig. 3 a-3 c, the material of the substrate 301 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), etc.; in some embodiments, the substrate 301 may also be Silicon-On-Insulator (SOI) or Germanium-On-Insulator (GOI).

Here, a plurality of free layers 3023 and a plurality of barrier layers 3024 may be included in the magnetic tunnel junction stack structure 302, and only the case where the magnetic tunnel junction stack structure 302 includes two free layers 3023 and two barrier layers 3024 is illustrated in fig. 3 a; only the case where the magnetic tunnel junction stack structure 302 includes three free layers 3023 and three barrier layers 3024 is illustrated in fig. 3 b; only the case where the magnetic tunnel junction stack structure 302 includes four free layers 3023 and four barrier layers 3024 is illustrated in fig. 3 c. The top layer of the magnetic tunnel junction stack structure 302 is a barrier layer 3024.

The fixed layer 3021 is used to provide a fixed magnetic moment direction, and the material of the fixed layer 3021 is a ferromagnetic material, which is also called a ferromagnetic layer; the material of the fixation layer 3021 includes, but is not limited to, iron (Fe), cobalt (Co), cobalt-iron (CoFe) alloys, heusler alloys, cobalt-iron-boron (CoFeB), and the like.

The bottom barrier layer 3022 is an insulating layer for acting as an insulator between the two ferromagnetic layers; the material of the bottom barrier layer 3022 includes, but is not limited to, magnesium oxide (MgO).

The free layer 3023 is used to provide a varying magnetic moment direction, which is also referred to as a ferromagnetic layer; materials for the free layer 3023 include, but are not limited to, iron (Fe), cobalt (Co), cobalt-iron (CoFe) alloys, heusler alloys, cobalt-iron-boron (CoFeB), and the like.

The barrier layer 3024 and the bottom barrier layer 3022 have the same function and materials, and are not described herein.

It will be appreciated that the magnetic tunnel junction stack 302 may be used as a core memory cell of a memory, where the magnetization direction of the ferromagnetic layer (bottom barrier layer 3022 or barrier layer 3024) is generally along the plane as the recording density increases, and where in-plane magnetization of the memory cell has many problems, for example, if the size of the magnetic tunnel junction stack is small to some extent, the edge magnetization of the memory device will exhibit a vortex effect, which is detrimental to information writing and reading. This problem can be effectively solved if the ferromagnetic layer in the magnetic tunnel junction stack is a perpendicular magnetic anisotropic material, and further, since the magnetization state of the ferromagnetic layer (bottom barrier layer 3022 or barrier layer 3024) is very insensitive to shape, the smaller the device size is, the more advantageous the stabilization of the perpendicular magnetization. In addition, in magnetization switching driven by current based on spin torque effects, the perpendicular material has a lower critical switching current density, as well as higher thermal stability. Thus, increasing the total number of contact interfaces of the ferromagnetic layer (bottom barrier layer 3022 or barrier layer 3024) with the free layer 3023 may be employed in embodiments of the present disclosure to further increase the perpendicular magnetic anisotropy (PMA, perpendicular Magnetic Anisotropy) of the magnetic tunnel junction stack structure.

Illustratively, referring to FIG. 3a, the magnetic tunnel junction stack structure 302 is a four interface magnetic tunnel junction stack structure; wherein the magnetic tunnel junction stack structure 302 comprises a bottom barrier layer 3022, two barrier layers 3024, and two free layers 3023.

Illustratively, referring to FIG. 3b, the magnetic tunnel junction stack structure 302 is a six interface magnetic tunnel junction stack structure; wherein the magnetic tunnel junction stack structure 302 includes a bottom barrier layer 3022, three barrier layers 3024, and three free layers 3023.

Illustratively, referring to FIG. 3c, the magnetic tunnel junction stack structure 302 is an eight interface magnetic tunnel junction stack structure; the magnetic tunnel junction stack structure 302 includes, among other things, a bottom barrier layer 3022, four barrier layers 3024, and four free layers 3023.

FIG. 4 is a graph showing the trend of thermal stability of magnetic tunnel junction stack structures with different numbers of contact interfaces; as can be seen from fig. 4, the thermal stability coefficient (Δ) of the magnetic tunnel junction stack structure with four interfaces, six interfaces, eight interfaces in this order is gradually increased; that is, as the number of contact interfaces of the free layer and the barrier layer increases, the thermal stability of the magnetic tunnel junction stack structure increases.

Preferably, the magnetic tunnel junction stack structure 302 in the embodiments of the present disclosure is an eight interface magnetic tunnel junction stack structure.

However, as the number of stacked layers of the free layer and the barrier layer increases, the resistance in the magnetic tunnel junction stack structure 302 increases, thereby decreasing RA (resistance-area product) in the magnetic tunnel junction stack structure 302 while decreasing the critical current and tunnel magnetoresistance ratio (TMR, tunnel Magnetoresistance Ratio); illustratively, referring to FIG. 5, the tunnel magnetoresistance ratio TMR of the barrier layer is gradually reduced from four interfaces, to six interfaces, to eight interfaces, at the interface of the barrier layer with the free layer.

Based on this, in the presently disclosed embodiments, referring to fig. 3 a-3 c, a conductive layer 303 is provided in the semiconductor structure; the conductive layer 303 is located on a portion of the sidewall of the magnetic tunnel junction stack structure 302, wherein the conductive layer 303 electrically connects at least a portion of the free layer 3023 in the magnetic tunnel junction stack structure 302; in this manner, the resistance in the magnetic tunnel junction stack structure 302 with multiple barrier layers 3024 and free layer 3023 interfaces can be made equivalent to the resistance in only a few barrier layers, even only the bottom barrier layer 3022, thereby reducing the RA (resistance-area product) of the magnetic tunnel junction stack structure 302 and thereby increasing the critical current and the tunnel magnetoresistance ratio TMR of the magnetic tunnel junction stack structure.

That is, the semiconductor structure provided in the embodiments of the present disclosure has both higher thermal stability and higher tunnel magnetoresistance ratio by providing the conductive layer on a portion of the sidewall of the magnetic tunnel junction stack structure 302.

Here and hereinafter, for the sake of clarity in describing the inventive idea of the present disclosure, the magnetic tunnel junction stack structure 302 is exemplified as an eight-interface magnetic tunnel junction stack structure, but it should be noted that the description of the number of interfaces in the following embodiments is only for illustrating the present disclosure, and is not intended to limit the scope of the present disclosure.

In some embodiments, referring to fig. 3c, the sidewalls of the conductive layer 303 are flush with both the sidewalls of the fixed layer 3021 and the sidewalls of the bottom barrier layer 3022.

It should be noted that "flush" as used herein is understood to mean substantially flush or substantially flush, and the difference (or difference) between the sidewall of the conductive layer, the sidewall of the fixed layer, and the sidewall of the bottom barrier layer falls within the allowable error range in the process, and falls within the flush range as described in the embodiments of the present disclosure.

Here, the conductive layer 303 electrically connects the plurality of barrier layers 3024 and the bottom barrier layer 3022 so that the resistance of the semiconductor structure is only the resistance of the bottom barrier layer 3022; thereby increasing the tunnel magnetoresistance ratio TMR of the magnetic tunnel junction stack structure.

In some embodiments, referring to fig. 6, the sidewalls of the conductive layer 303 are flush with the sidewalls of the fixed layer 3021, the bottom barrier layer 3022, and the substrate 301.

The side wall of the conductive layer 303 may be flush with the side wall of the bottommost free layer 3023 of the alternately stacked free layers and barrier layers, or may cover the side wall of the bottommost free layer 3023 of the alternately stacked free layers and barrier layers. Here, referring to fig. 6, the conductive layer 303 is flush with the sidewall of the bottommost free layer 3023 of the alternately stacked free layers and barrier layers. The sidewalls of the conductive layer 303 may be flush with the sidewalls of the substrate 301.

In some embodiments, referring to fig. 7a and 7b, the conductive layer 303 is located on the bottom barrier layer 3022 and covers the sidewalls of all of the free layer 3023 and the barrier layer 3024 in the magnetic tunnel junction stack structure 302.

At this time, the side walls of the bottom barrier layer 3022 are flush with the side walls of all of the free layers and barrier layers 3024 in the plurality of free layers 3023 and barrier layers stacked alternately in this order. It should be noted that, in the embodiment of the present disclosure, the side wall of the conductive layer 303 is flush with the side wall of the fixed layer 3021 and the side wall of the bottom barrier layer 3022; further, the sidewall of the conductive layer 303 is not flush with the sidewall of the substrate 301, which may be the case with reference to fig. 7a, and the sidewall of the conductive layer 303 may be flush with the sidewall of the substrate 301, which may be the case with reference to fig. 7b.

In some embodiments, referring to fig. 3c, 6, the conductive layer 303 is located on the bottom-most free layer 3023 of the alternating stack of free layers 3023 and barrier layers 3024 and covers the sidewalls of the free layer 3023 and barrier layers 3024 remaining in the magnetic tunnel junction stack structure 302.

Here, the conductive layer 303 electrically connects the plurality of free layers 3023 to the bottom barrier layer 3022. The side walls of the conductive layer 303 are flush with the side walls of the fixed layer 3021 and the side walls of the bottom barrier layer 3022; further, the sidewall of the conductive layer 303 and the sidewall of the substrate 301 may not be flush, refer to fig. 3c; the sidewalls of the conductive layer 303 may also be flush with the sidewalls of the substrate 301, see fig. 6.

In some embodiments, referring to fig. 8a, 8b, 9a, 9b, the semiconductor structure further comprises: an insulating layer 306 located between the conductive layer 303 and the bottom barrier layer 3022, wherein a top surface of the insulating layer 306 is higher than a top surface of a bottommost free layer 3023 of the alternately stacked free layers and barrier layers.

Here, the insulating layer 306 serves to ensure electron tunneling into the bottommost free layer 3023 of the alternately stacked free layers and barrier layers, instead of the outer conductive layer 303. In order to prevent electron tunneling, the top surface of the insulating layer 306 may be higher than the top surface of the lowermost barrier layer of the alternately stacked free layers and barrier layers; here, the top surface of the insulating layer 306 is higher or lower than the top surface of the lowermost barrier layer of the alternately stacked free layers and barrier layers, and does not affect the resistance in the semiconductor structure.

In some embodiments, referring to fig. 8a, 8b, 9a, 9b, the top surface of the insulating layer is lower than the top surface of the lowermost barrier layer 3024 of the alternating stack of free layers 3023 and barrier layers 3024.

Here, the insulating layer 306 has a top surface lower than the top surface of the bottommost barrier layer 3024 of the alternately stacked free layers 3023 and barrier layers 3024, and the conductive layer 303 may be connected to more of the alternately stacked free layers 3023 and barrier layers 3024.

In some embodiments, the insulating layer sidewall is flush with the conductive layer sidewall, and a dimension of the insulating layer along a preset direction is greater than or equal to a dimension of the conductive layer along the preset direction, and the preset direction is perpendicular to a stacking direction of the free layer and the barrier layer.

Here, the direction in which the free layer and the barrier layer are stacked is perpendicular to the surface of the substrate 301; the direction in which the free layer and the barrier layer are stacked is illustratively the Z-axis direction in the drawing, and the preset direction may be the X-axis direction or the Y-axis direction (not shown in the drawing) or other directions between the X-axis and the Y-axis.

It should be noted that, the magnetic tunnel junction laminated structures shown in the embodiments of the present disclosure are all cross-sectional views, and in the cross-sectional views of the magnetic tunnel junction laminated structures corresponding to the cross-sectional views, the conductive layer and the insulating layer are matched with the shapes of the plurality of laminated layers; specifically, when the shape of the magnetic tunnel junction stack structure is circular, the shape of the conductive layer is a circular ring; when the shape of the magnetic tunnel junction laminated structure is a cylinder, the shape of the conductive layer is a cylinder; in addition, when the magnetic tunnel junction stack structure is in the shape of a circular ring, the conductive layer may be only a part or parts of the cylinder. Correspondingly, the insulating layer is positioned between the conductive layer and the bottom barrier layer, and the projection of the insulating layer on the surface of the substrate at least covers the projection of the conductive layer on the surface of the substrate; in other words, the insulating layer has a sidewall flush with the sidewall of the conductive layer, and a dimension of the insulating layer in the X-axis direction, the Y-axis direction, or other directions between the X-axis and the Y-axis is greater than or equal to a dimension of the conductive layer in the corresponding X-axis direction, Y-axis direction, or other directions between the X-axis and the Y-axis.

For example, referring to fig. 8a and 8b, the sidewall of the insulating layer 306 is flush with the sidewall of the conductive layer 303, and the dimension of the insulating layer 306 in the X-axis direction is equal to the dimension of the conductive layer 303 in the X-axis direction; referring to fig. 9a and 9b, the sidewall of the insulating layer 306 is flush with the sidewall of the conductive layer 303. Wherein, the side wall of the insulating layer 306 is partially connected with the conductive layer 303, and the dimension of the insulating layer 306 in the X-axis direction is larger than the dimension of the conductive layer 303 in the X-axis direction.

In some embodiments, the material of the conductive layer 303 includes at least one of tantalum, tungsten, copper, or titanium nitride. The material of the insulating layer 306 includes, but is not limited to, silicon oxide.

In some embodiments, referring to fig. 3 a-3 c, 6-10 b, the semiconductor structure further comprises: a cap layer 305 on the magnetic tunnel junction stack structure 302; the conductive layer 303 covers the sidewalls of the cap layer 305.

The top surface of the conductive layer 303 is flush with the top surface of the cap layer 305. The cap layer 305 serves to protect the barrier layer 3024 from damage. The material of the cap layer 305 includes, but is not limited to, ruthenium (Ru).

In some embodiments, referring to fig. 10a, 10b, the semiconductor structure further comprises: bit line 307 is disposed on cap layer 305 and conductive layer 303 and electrically connected to conductive layer 303.

The bit line 307 is connected to a plurality of free layers 3023 through the conductive layer 303 for enabling transmission of an electrical signal when a read operation is performed. The material of the bit line 307 includes, but is not limited to, tungsten (W).

In some embodiments, referring to fig. 10a, 10b, the semiconductor structure further comprises: and a sidewall protection layer 308 covering the conductive layer, the magnetic tunnel junction stack structure, the cap layer and the bit line.

The sidewall protection layer 308 may be used to protect the magnetic tunnel junction stack structure 302 from external factors; the material of the sidewall protection layer 308 is an insulating material, and exemplary materials of the sidewall protection layer 308 include, but are not limited to, silicon oxide.

In some embodiments, referring to fig. 3 a-3 c, 6-10 b, the semiconductor structure further comprises: a buffer layer 304 located between the substrate 301 and the fixing layer 3021, wherein a sidewall of the buffer layer 304 is flush with a sidewall of the substrate 301.

Here, the buffer layer 304 is located on the substrate 301, and the magnetic tunnel junction stack structure 302 is located on the buffer layer 304. The buffer layer 304 may be an antiferromagnetic film, which is used to ensure that the magnetic field direction of the pinned layer 3021 in the magnetic tunnel junction stack 302 is unchanged when the semiconductor structure exchanges information with an external circuit, thereby improving the reliability of the semiconductor structure. The material of the buffer layer 304 includes, but is not limited to, cobalt iron (CoFe) alloy, cobalt iron boron (CoFeB), and the like.

Based on the above, in embodiments of the disclosure, a magnetic tunnel junction stack structure is formed on a substrate, where the magnetic tunnel junction stack structure includes a fixed layer, a bottom barrier layer located on the fixed layer, and a plurality of free layers and barrier layers located on the bottom barrier layer and alternately stacked in sequence; in addition, a conductive layer is disposed on a portion of the sidewall of the magnetic tunnel junction stack structure, the conductive layer electrically connecting at least a portion of the free layer in the magnetic tunnel junction stack structure. Thus, on one hand, by forming a plurality of free layers and barrier layers which are alternately stacked in the magnetic tunnel junction stacked structure, the magnetic tunnel junction stacked structure can be provided with a plurality of free layer and barrier layer interfaces, so that the magnetic tunnel junction stacked structure has higher thermal stability; on the other hand, the partial free layers in the magnetic tunnel junction laminated structure are electrically connected through the conductive layers, so that the Resistance of the magnetic tunnel junction laminated structure is equivalent to the Resistance in fewer barrier layers, even equivalent to the Resistance in the bottom barrier layer, and therefore the Resistance-Area product (RA) of the magnetic tunnel junction laminated structure is reduced, and the tunnel magnetoresistance ratio (TMR, tunnel Magnetoresistance Ratio) of the magnetic tunnel junction laminated structure is further increased, that is, the semiconductor structure provided by the embodiment of the disclosure has higher thermal stability and higher tunnel magnetoresistance ratio.

According to another aspect of the present disclosure there is provided a memory comprising: one or more semiconductor structures as in any of the above embodiments of the present disclosure.

In other embodiments, the semiconductor structure further comprises peripheral circuitry; the peripheral circuit is used for controlling the semiconductor structure.

According to still another aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, and fig. 11 is a schematic flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; as shown in fig. 11, a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure includes the following steps:

s1101: providing a substrate;

s1102: forming a magnetic tunnel junction stack structure on the substrate; forming the magnetic tunnel junction stack structure includes: forming a fixed layer, forming a bottom barrier layer on the fixed layer, and sequentially forming a plurality of free layers and barrier layers which are alternately stacked on the bottom barrier layer;

s1103: a conductive layer is formed overlying a portion of the sidewalls of the magnetic tunnel junction stack, at least a portion of the free layer in the magnetic tunnel junction stack being electrically connected by the conductive layer.

It should be understood that the steps shown in fig. 11 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations. The steps shown in fig. 11 can be sequentially adjusted according to actual needs. The method for manufacturing the semiconductor structure according to the embodiment of the present disclosure will be described in detail with reference to fig. 11, 12a, 12b, 12c, 12d, 3c, 6, 10a, and 10 b.

It should be noted that the semiconductor structure in the foregoing embodiments has a plurality of different types, and only one semiconductor structure in the foregoing embodiments will be described in detail herein and hereinafter, with reference to fig. 10a and 10b. It should be understood that the methods of forming semiconductor structures described below are merely illustrative of the present disclosure and are not intended to limit the scope of the present disclosure.

Step S1101 is performed, and referring to fig. 12a, a substrate 301 is provided.

Step S1102 is performed to form a magnetic tunnel junction stack structure.

It should be noted that a buffer layer may be formed on the substrate before the magnetic tunnel junction stack structure is formed. Specifically, a buffer layer is formed overlying the substrate, and a magnetic tunnel junction stack structure is formed on the buffer layer 304. Methods of forming the buffer layer include, but are not limited to, physical vapor deposition (PVD, physical Vapor Deposition) processes, chemical vapor deposition (CVD, chemical Vapor Deposition) processes, atomic layer deposition (ALD, atomic Layer Deposition), and the like.

The magnetic tunnel junction stack structure includes: the device comprises a fixed layer, a bottom barrier layer positioned on the fixed layer, and a plurality of free layers and barrier layers which are sequentially and alternately laminated on the bottom barrier layer.

In some embodiments, the forming the magnetic tunnel junction stack structure includes:

sequentially forming a fixed material layer, a bottom barrier material layer and a plurality of alternate free material layers and barrier material layers which are stacked;

removing portions of the alternating layers of free material and barrier material;

further removing part of the free material layers and barrier material layers except the bottommost free material layer in the rest of the plurality of alternating free material layers and barrier material layers, exposing part of the top surface of the bottommost free layer, and forming the barrier layer and the free layer;

after the conductive layer is formed, removing part of the fixed material layer and the bottom barrier material layer to obtain a fixed layer and a bottom barrier layer, so that the side wall of the fixed layer and the side wall of the bottom barrier layer are flush with the side wall of the conductive layer;

the forming of the conductive layer includes:

the conductive layer is formed on the exposed bottommost free layer to cover the remaining free layer and barrier layer.

Referring to fig. 12a, a fixed material layer 1201 is formed on the buffer layer 304, a bottom barrier material layer 1202 is formed on the fixed material layer 1201, and a plurality of alternating free material layers 1203 and barrier material layers 1204 are formed on the bottom barrier material layer 1202; and forming a capping material layer 1205 on the barrier material layer 1204.

Methods of forming the fixed material layer 1201, the bottom barrier material layer 1202, the free material layer 1203, the barrier material layer 1204, the capping material layer 1205 include, but are not limited to, PVD processes, CVD processes, ALD processes, magnetron sputtering processes, and the like.

Referring to fig. 12b, a portion of the free material layer 1203 and a portion of the barrier material layer 1204 are removed.

Referring to fig. 12c, portions of the free material layer 1203 and barrier material layer 1204, except for the bottommost free material layer 1203, of the remaining number of alternating free material layers 1203 and barrier material layers 1204 are further removed to form a free layer 3023 and a barrier layer 3024.

Wherein a portion of cap material layer 1205 is removed to form cap layer 305.

The removal process includes, but is not limited to, a dry etching process; preferably, the removal process comprises a plasma dry etching process.

Step S1103 is performed, referring to fig. 12d, forming the conductive layer 303.

The conductive layer 303 covers a portion of the sidewalls of the magnetic tunnel junction stack structure 302 for electrically connecting at least a portion of the free layer 3023 in the magnetic tunnel junction stack structure; in this manner, the resistance in the magnetic tunnel junction stack structure 302 may be reduced.

Methods of forming the conductive layer 303 include, but are not limited to, PVD processes, CVD processes, ALD processes, and the like.

It should be noted that the sidewall of the conductive layer 303 may be only flush with the sidewall of the bottommost free layer 3023 of the plurality of alternating free layers and barrier layers, referring to fig. 12d; it may also be only flush with the sidewalls of the bottommost free layer 3023, the fixed layer 3021, and the bottom barrier layer 3022 of the number of alternating free and barrier layers, see fig. 3c; it may also be flush with the sidewalls of the substrate 301, buffer layer 304, bottom-most free layer 3023 of the number of alternating free and barrier layers, fixed layer 3021, bottom barrier layer 3022, referring to fig. 6; the structure is described before and will not be described again here.

In some embodiments, referring to fig. 3c, after forming the conductive layer 303, a portion of the fixing material layer 1201 is removed, forming a fixing layer 3021; and the bottom barrier material layer 1202 forming a bottom barrier layer 3022;

here, the sidewalls of the fixed layer 3021 and the bottom barrier layer 3022 are both flush with the sidewalls of the conductive layer 303.

The removal process includes, but is not limited to, a dry etching process; preferably, the removal process comprises a plasma dry etching process.

In some embodiments, referring to fig. 10a, the method further comprises:

Forming a bit line 307 over the conductive layer and the magnetic tunnel junction stack;

a sidewall protection layer 308 is formed to cover the conductive layer 303, the magnetic tunnel junction stack structure 302, the cap layer 305, and the bit line 307.

Methods of forming the bit line 307 and the sidewall protection layer 308 include, but are not limited to, PVD, CVD, ALD.

In some embodiments, referring to fig. 10b, the method further comprises:

forming an insulating layer 306 between the conductive layer 303 and the bottom barrier layer 3022; methods of forming the insulating layer 306 include, but are not limited to, PVD, CVD, ALD and the like.

Here, referring to fig. 10b, the top surface of the insulating layer 306 may be higher than the top surface of the bottommost free layer 3023 of the alternately stacked free and barrier layers; in other embodiments, the top surface of the insulating layer 306 may be lower than the top surface of the bottommost barrier layer of the alternating stack of free and barrier layers. In still other embodiments, the insulating layer 306 has a sidewall flush with the sidewall of the conductive layer 303, and the insulating layer 306 has a dimension in a predetermined direction that is perpendicular to the direction in which the free layer and the barrier layer are stacked, that is greater than or equal to the dimension of the conductive layer in the predetermined direction.

In several embodiments provided by the present disclosure, it should be understood that the disclosed apparatus and methods may be implemented in a non-targeted manner. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.

The units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (17)

1. A semiconductor structure, comprising:

a substrate;

a magnetic tunnel junction stack structure on the substrate, comprising: the device comprises a fixed layer, a bottom barrier layer positioned on the fixed layer, and a plurality of free layers and barrier layers which are sequentially and alternately laminated on the bottom barrier layer; and

and a conductive layer covering a portion of the sidewall of the magnetic tunnel junction stack structure, at least a portion of the free layer in the magnetic tunnel junction stack structure being electrically connected by the conductive layer.

2. The semiconductor structure of claim 1, wherein sidewalls of the conductive layer are flush with sidewalls of the fixed layer and sidewalls of the bottom barrier layer.

3. The semiconductor structure of claim 2, wherein sidewalls of the conductive layer are flush with sidewalls of the fixed layer, sidewalls of the bottom barrier layer, and sidewalls of the substrate.

4. A semiconductor structure according to claim 2 or 3, wherein the conductive layer is located on the bottom barrier layer and covers all of the free layer and the sidewalls of the barrier layer in the magnetic tunnel junction stack.

5. A semiconductor structure according to claim 2 or 3, wherein the conductive layer is located on a bottommost free layer of the alternately stacked free and barrier layers and covers sidewalls of the remaining free and barrier layers in the magnetic tunnel junction stack structure.

6. The semiconductor structure of claim 2 or 3, wherein the semiconductor structure further comprises: and the insulating layer is positioned between the conductive layer and the bottom barrier layer, and the top surface of the insulating layer is higher than the top surface of the bottommost free layer in the free layer and the barrier layer which are alternately stacked.

7. The semiconductor structure according to claim 6, wherein a top surface of the insulating layer is lower than a top surface of a bottommost barrier layer of the alternately stacked free layers and barrier layers.

8. The semiconductor structure of claim 6, wherein the insulating layer sidewall is flush with the conductive layer sidewall and the insulating layer meets a portion of the free layer, wherein a dimension of the insulating layer in a predetermined direction is greater than or equal to a dimension of the conductive layer in the predetermined direction, the predetermined direction being perpendicular to a direction in which the free layer and the barrier layer are stacked.

9. The semiconductor structure of claim 1, wherein the material of the conductive layer comprises at least one of tantalum, tungsten, copper, or titanium nitride.

10. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: a cap layer on the magnetic tunnel junction stack structure; the conductive layer covers the sidewalls of the cap layer.

11. The semiconductor structure of claim 10, wherein the semiconductor structure further comprises: and the bit line is positioned on the cap layer and the conductive layer and is electrically connected with the conductive layer.

12. The semiconductor structure of claim 11, wherein the semiconductor structure further comprises: and the side wall protection layer is used for coating the conductive layer, the magnetic tunnel junction laminated structure, the cap layer and the bit line.

13. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: and the buffer layer is positioned between the substrate and the fixed layer, and the side wall of the buffer layer is flush with the side wall of the substrate.

14. A memory, comprising: one or more semiconductor structures as claimed in any one of claims 1 to 13.

15. A method of fabricating a semiconductor structure, the method comprising:

providing a substrate;

forming a magnetic tunnel junction stack structure on the substrate; forming the magnetic tunnel junction stack structure includes: forming a fixed layer, forming a bottom barrier layer on the fixed layer, and sequentially forming a plurality of free layers and barrier layers which are alternately stacked on the bottom barrier layer;

A conductive layer is formed overlying a portion of the sidewalls of the magnetic tunnel junction stack, at least a portion of the free layer in the magnetic tunnel junction stack being electrically connected by the conductive layer.

16. The method of fabricating a semiconductor structure as claimed in claim 15, wherein,

the forming the magnetic tunnel junction stack structure includes:

sequentially forming a fixed material layer, a bottom barrier material layer and a plurality of alternate free material layers and barrier material layers which are stacked;

removing portions of the alternating layers of free material and barrier material;

further removing part of the free material layers and barrier material layers except the bottommost free material layer in the rest of the plurality of alternating free material layers and barrier material layers, exposing part of the top surface of the bottommost free layer, and forming the barrier layer and the free layer;

after the conductive layer is formed, removing part of the fixed material layer and the bottom barrier material layer to obtain a fixed layer and a bottom barrier layer, so that the side wall of the fixed layer and the side wall of the bottom barrier layer are flush with the side wall of the conductive layer;

the forming of the conductive layer includes:

the conductive layer is formed on the exposed bottommost free layer to cover the remaining free layer and barrier layer.

17. The method of fabricating a semiconductor structure of claim 15, further comprising:

forming a buffer layer on the substrate before forming the magnetic tunnel junction stack structure;

forming the magnetic tunnel junction stack structure on the buffer layer;

forming a cap layer over the magnetic tunnel junction stack structure prior to forming the conductive layer;

forming a conductive layer covering the cap layer sidewall and a portion of the sidewall of the magnetic tunnel junction stack structure;

forming a bit line on the conductive layer and the magnetic tunnel junction stack structure;

and forming a side wall protection layer which covers the conductive layer, the magnetic tunnel junction laminated structure, the cap layer and the bit line.