CN117675076A - Clock synchronization method and service board - Google Patents

Abstract

The present specification provides a method for clock synchronization and a service board, the method is applied to the service board, and the method includes: the service board is connected with a clock board in the main control board through a MUX circuit of the service board, and is used for receiving and transmitting a first signal and receiving a second signal, and the MUX circuit is connected with a receiving circuit, a transmitting circuit and a TSU module of the service board and is used for providing clock signals according to the first signal and the second signal. By the method, the number of clock signals between the clock board and the service board can be reduced, the number of service cards supported by the system can be increased on the premise of not increasing the size of the back board and the number of connectors, and development cost is saved.

Description

Clock synchronization method and service board

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to a clock synchronization method and a service board.

Background

In modern communication networks, time synchronization technology is widely used as a general technology. Common clock synchronization techniques are NTP and PTP, and their time synchronization accuracy is in the ms and ns levels, respectively. In the 5G era, high-precision time synchronization is required for unmanned, unmanned logistics and other industrial applications, and operators clearly propose that a single device cTE cannot exceed +/-10ns in the development indexes of 5G access/convergence/core devices, so that a PTP clock synchronization technology is required to meet the requirement.

Currently, PTP clock synchronization techniques have two modes:

1. 1588 non-hybrid mode: 1588 message realizing frequency and time synchronization

2. 1588 hybrid mode: SYNCE realizes frequency synchronization and 1588 message realizes time synchronization

In a distributed system, there is generally a clock board, on which a 1588 protocol stack is run, and time offsets of the local device and the upstream device are calculated by acquiring timestamp information in the local device and the upstream device 1588 message, so as to synchronize the offset values to all service boards.

In a distributed system, to ensure high precision time synchronization, the time and frequency information between the clock board and the service board need to be synchronized with each other, wherein the clock board on the master is unique, and the service board may have a plurality (commonly 4/6/8/16). To achieve high precision clock synchronization, the number of signals required on the backplane is 4*N (N is the number of service boards).

Disclosure of Invention

To overcome the problems in the related art, the present specification provides a method of clock synchronization and a service board.

According to a first aspect of embodiments of the present specification, there is provided a method of clock synchronization, the method comprising:

the service board is connected with a clock board in the main control board through a MUX circuit of the service board and is used for receiving and transmitting a first signal and receiving a second signal;

the MUX circuit is connected with the receiving circuit, the transmitting circuit and the TSU module of the service board and used for providing clock signals according to the first signal and the second signal.

Wherein the first signal comprises: a line_clk signal, the second signal comprising: a TXD_CLK signal;

the line_clk signal is used for sending a stamping clock and/or receiving LINE recovery clock, and the txd_clk signal is used for providing a sending data clock and/or sending a stamping clock.

Optionally, the method further comprises:

in 1588 non-hybrid mode, the line_clk signal is used to provide a stamping clock for the traffic board and the txd_clk signal is used to provide a transmit data clock;

in 1588 hybrid mode, the line_clk signal is used to receive the LINE recovery clock and the txd_clk signal is used to transmit the data clock and the stamping clock.

The MUX circuit is established through a CPLD or an FPGA.

According to the embodiment, the MUX circuit is connected with the clock board through the back board, so that the number of back board signals can be reduced in a system with the same number of service boards, the back board design is simplified, the number of service boards supported by the system can be increased on the premise that the size of the back board and the number of connectors are not increased, and development cost is saved.

According to a second aspect of embodiments of the present specification, there is provided a service board comprising: the system comprises a MUX circuit, wherein one side of the MUX circuit is connected with a clock board in a main control board through a back board, and the other side of the MUX circuit is connected with a receiving circuit, a transmitting circuit and a TSU module of a service board, and the MUX circuit comprises:

the receiving module is used for receiving the first signal and the second signal sent by the clock board;

and the transmitting module is used for providing clock signals for the receiving circuit, the transmitting circuit and the TSU module according to the first signal and the second signal.

Wherein the first signal comprises: a line_clk signal, the second signal comprising: a TXD_CLK signal;

the line_clk signal is used for sending a stamping clock and/or receiving LINE recovery clock, and the txd_clk signal is used for providing a sending data clock and/or sending a stamping clock.

In 1588, in non-hybrid mode, the transmitting module is specifically configured to transmit a line_clk signal for providing a stamping clock for a service board, and transmit a txd_clk signal for providing a transmitting data clock;

in 1588 hybrid mode, the transmitting module is specifically configured to transmit a txd_clk signal for transmitting a data clock and a stamping clock, and the receiving module is configured to receive a line recovery clock.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and together with the description, serve to explain the principles of the specification.

Fig. 1 is a block diagram schematic diagram of a backplane clock between a clock board and a service board according to an example embodiment of the present description.

Fig. 2 is a flow chart illustrating a method of clock synchronization according to an exemplary embodiment of the present disclosure.

Fig. 3 is a block diagram schematic diagram of a backplane clock between a clock board and a service board according to an example embodiment of the present description.

Fig. 4 is a block diagram schematic diagram of a backplane clock between a clock board and a service board according to an example embodiment of the present disclosure.

Fig. 5 is a block diagram schematic diagram of a backplane clock between a clock board and a service board according to an example embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present specification. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present description as detailed in the accompanying claims.

The terminology used in the description presented herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information, without departing from the scope of the present description. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.

Fig. 1 shows a block diagram of a backplane clock between a clock board and a service board, wherein the clock board on the master is unique, the service board may have a plurality (commonly 4/6/8/16), and the number of signals required on the backplane is 4*N (N is the number of service cards) to achieve high-precision clock synchronization. Then, the backplane signal resources are very precious, at present, 4 signals are needed for each service board to realize high-precision clock synchronization, and the more the number of service cards supported by the machine frame is, the more the backplane signals are needed to be occupied. The width and the height of the backboard master clock card are fixed, the number of backboard signals which can be provided is also fixed, and the backboard signal utilization rate of the current scheme is not high.

To solve the above technical problem, an embodiment of the present disclosure provides a method for clock synchronization, where the method is applied to a service board, as shown in fig. 2, and the method includes:

s201, the service board is connected with a clock board in the main control board through a MUX circuit of the service board and is used for receiving and transmitting a first signal and receiving a second signal;

and S202, the MUX circuit is connected with the receiving circuit, the transmitting circuit and the TSU module of the service board and used for providing clock signals according to the first signal and the second signal.

In this embodiment, the MUX circuit may provide a plurality of input/output interfaces, and the MUX circuit may be implemented by a CPLD/FPGA/discrete device, in this embodiment, the rcv_clk and sets_clk clocks are time-division multiplexed by the MUX circuit, and the signal after the back plane is combined is called line_clk.

In this embodiment, the LINE_CLK signal is used to transmit the stamping clocks SETS_CLK0-N and/or the receive LINE recovery clock RCV_CLK0-N and the TXD_CLK signal is used to provide the transmit data clocks TXD_CLK0-N and/or the transmit stamping clocks SETS_CLK0-N.

As shown in fig. 3, it can be seen that by adding the MUX circuit, the number of high-precision clock signals from the clock boards to each service board can be reduced from 4 to 3, and for a device having a plurality of service boards, the back board signal utilization rate can be greatly improved, and the number of service cards supported by the system can be increased without increasing the size of the back board and the number of connectors.

In an example of 1588 non-mixed mode, as shown in fig. 4, i.e., pure 1588 scenarios, the traffic board does not recover clock from the LINE, clock board line_clk is used as the transmit clock for time stamping the traffic card for use, and txd_clk is used to transmit the data clock.

In an example in 1588 hybrid mode, as shown in fig. 5, namely 1588+synce, the transmission data clock and the stamping clock of the service card may be shared, and the clock card line_clk is used as a receiving clock for synchronizing clocks of ports of the service card, namely SYNCE clock; TXD_CLK is used to transmit both the data clock and the stamping clock.

According to the embodiments, the method in the disclosure can greatly improve the signal utilization rate of the backboard, and can increase the number of service cards supported by the system without increasing the backboard size and the number of connectors, so that the development cost is saved.

The embodiment of the disclosure also provides a service board, which comprises: the system comprises a MUX circuit, wherein one side of the MUX circuit is connected with a clock board in a main control board through a back board, and the other side of the MUX circuit is connected with a receiving circuit, a transmitting circuit and a TSU module of a service board, and the MUX circuit comprises:

the receiving module is used for receiving the first signal and the second signal sent by the clock board;

and the transmitting module is used for providing clock signals for the receiving circuit, the transmitting circuit and the TSU module according to the first signal and the second signal.

The first signal includes: a line_clk signal, the second signal comprising: a TXD_CLK signal;

the line_clk signal is used for sending a stamping clock and/or receiving LINE recovery clock, and the txd_clk signal is used for providing a sending data clock and/or sending a stamping clock.

In 1588 non-hybrid mode, the transmitting module is specifically configured to transmit a line_clk signal for providing a stamping clock for the service board, and transmit a txd_clk signal for providing a transmit data clock;

in 1588 hybrid mode, the transmitting module is specifically configured to transmit a txd_clk signal for transmitting a data clock and a stamping clock, and the receiving module is configured to receive a line recovery clock.

For the device embodiments, reference is made to the description of the method embodiments for the relevant points, since they essentially correspond to the method embodiments. The apparatus embodiments described above are merely illustrative, wherein the modules illustrated as separate components may or may not be physically separate, and the components shown as modules may or may not be physical, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purposes of the present description. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

The foregoing describes specific embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Other embodiments of the present description will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This specification is intended to cover any variations, uses, or adaptations of the specification following, in general, the principles of the specification and including such departures from the present disclosure as come within known or customary practice within the art to which the specification pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the specification being indicated by the following claims.

It is to be understood that the present description is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.

The foregoing description of the preferred embodiments is provided for the purpose of illustration only, and is not intended to limit the scope of the disclosure, since any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.

Claims (7)

1. A method of clock synchronization, the method being applied to a service board, the method comprising:

the service board is connected with a clock board in the main control board through a MUX circuit of the service board and is used for receiving and transmitting a first signal and receiving a second signal;

the MUX circuit is connected with the receiving circuit, the transmitting circuit and the TSU module of the service board and used for providing clock signals according to the first signal and the second signal.

2. The method of claim 1, wherein the first signal comprises: a line_clk signal, the second signal comprising: a TXD_CLK signal;

the line_clk signal is used for sending a stamping clock and/or receiving LINE recovery clock, and the txd_clk signal is used for providing a sending data clock and/or sending a stamping clock.

3. The method according to claim 2, wherein the method further comprises:

in 1588 non-hybrid mode, the line_clk signal is used to provide a stamping clock for the traffic board and the txd_clk signal is used to provide a transmit data clock;

in 1588 hybrid mode, the line_clk signal is used to receive the LINE recovery clock and the txd_clk signal is used to transmit the data clock and the stamping clock.

4. The method of claim 1, wherein the MUX circuit is implemented by a CPLD or FPGA.

5. A service panel, the service panel comprising: the system comprises a MUX circuit, wherein one side of the MUX circuit is connected with a clock board in a main control board through a back board, and the other side of the MUX circuit is connected with a receiving circuit, a transmitting circuit and a TSU module of a service board, and the MUX circuit comprises:

the receiving module is used for receiving the first signal and the second signal sent by the clock board;

and the transmitting module is used for providing clock signals for the receiving circuit, the transmitting circuit and the TSU module according to the first signal and the second signal.

6. The service board of claim 5, wherein the first signal comprises: a line_clk signal, the second signal comprising: a TXD_CLK signal;

the line_clk signal is used for sending a stamping clock and/or receiving LINE recovery clock, and the txd_clk signal is used for providing a sending data clock and/or sending a stamping clock.

7. The service panel according to claim 5, wherein,

in 1588 non-hybrid mode, the transmitting module is specifically configured to transmit a line_clk signal for providing a stamping clock for the service board, and transmit a txd_clk signal for providing a transmit data clock;

in 1588 hybrid mode, the transmitting module is specifically configured to transmit a txd_clk signal for transmitting a data clock and a stamping clock, and the receiving module is configured to receive a line recovery clock.