CN117674839B - Automatic frequency correction circuit and method - Google Patents
Automatic frequency correction circuit and method Download PDFInfo
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- CN117674839B CN117674839B CN202311640622.6A CN202311640622A CN117674839B CN 117674839 B CN117674839 B CN 117674839B CN 202311640622 A CN202311640622 A CN 202311640622A CN 117674839 B CN117674839 B CN 117674839B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
本发明提供一种自动频率校正电路及方法，自动频率校正电路包括第一计数模块、第二计数模块、计数比较模块、高频四相位时钟生成模块、高频四相位时钟辅助判断模块、复合判断及最优选择模块、选段逻辑模块，高频四相位时钟辅助判断模块在四个高频时钟的控制下，对第一计数值的最低位与第二计数值的最低位进行采样、判断，判断反馈分频时钟相对于所述鉴相时钟的快慢，得到第二判断结果，基于引入的四个高频异相时钟进行采样检测，摆脱了选段精度和时间对鉴相时钟频率的依赖，即便面对低鉴相频率的应用场合，也可以快速准确地分辨鉴相时钟和反馈分频时钟的频率差异，应用于锁相环时提升了基于多段式压控振荡器的锁相环的输出频率校正速度和精度。
The present invention provides an automatic frequency correction circuit and method. The automatic frequency correction circuit comprises a first counting module, a second counting module, a counting comparison module, a high-frequency four-phase clock generating module, a high-frequency four-phase clock auxiliary judgment module, a composite judgment and optimal selection module, and a segment selection logic module. The high-frequency four-phase clock auxiliary judgment module samples and judges the lowest bit of a first counting value and the lowest bit of a second counting value under the control of four high-frequency clocks, judges the speed of a feedback frequency-dividing clock relative to the phase-locking clock, and obtains a second judgment result. Sampling and detection are performed based on the four introduced high-frequency out-of-phase clocks, thereby getting rid of the dependence of segment selection accuracy and time on the phase-locking clock frequency. Even in the application of low phase-locking frequency, the frequency difference between the phase-locking clock and the feedback frequency-dividing clock can be quickly and accurately distinguished. When applied to a phase-locked loop, the output frequency correction speed and accuracy of a phase-locked loop based on a multi-segment voltage-controlled oscillator are improved.
Description
Technical Field
The present invention relates to the field of phase-locked loop frequency synthesis technology, and in particular, to an automatic frequency correction circuit and method.
Background
Phase-locked loop type frequency synthesizer and clock generation circuit are widely used in analog, digital and radio frequency chips. The phase-locked loop combining the multi-voltage-controlled oscillator (VCO) and the multi-section voltage-controlled oscillator can realize broadband coverage, and more excellent spurious and phase noise performance is embodied. However, the output of the multi-stage voltage-controlled oscillator phase-locked loop inevitably adopts automatic frequency correction, so as to realize the selection of the voltage-controlled oscillator subsections with optimal locking frequency points, thereby achieving the optimal performance.
For process reasons, the coverage frequency range of the voltage controlled oscillator section is different from chip to chip. The voltage controlled oscillator segments corresponding to the same frequency point are not necessarily identical in different chips. There is no combination of a common divide value and a vco segment code so that each chip outputs the same frequency. The most effective solution is to use a special automatic frequency correction module to select the voltage controlled oscillator segment with the best performance for each chip.
The phase-locked loop is a feedback control system, and the output frequency of the voltage-controlled oscillator is divided by a frequency divider to obtain a feedback divided clock. According to the frequency phase relation between the phase discrimination clock and the feedback frequency division clock, the control voltage of the voltage-controlled oscillator is adjusted, so that the frequency of the feedback frequency division clock is adjusted, and then the frequency phase relation between the phase discrimination clock and the feedback frequency division clock is influenced. After such a cyclic reciprocating adjustment and feedback process, the phase locked loop eventually reaches a steady state. The phase-discriminating clock and the feedback frequency-dividing clock have the same frequency and relatively stable phase difference. The output frequency is equal to the phase discrimination frequency multiplied by the set division number of the frequency divider, i.e., the target frequency. For a multi-stage voltage controlled oscillator phase locked loop, there is a frequency range overlap between adjacent voltage controlled oscillator stages to ensure frequency continuous coverage. The frequency points in the overlapping range can be obtained by a plurality of voltage-controlled oscillator outputs participating in the overlapping. Different voltage controlled oscillator segments, whose control voltages are not identical, achieve the same frequency output. The voltage controlled oscillator can achieve optimal output performance when the control voltage is within a certain range. The automatic frequency correction circuit works by finding out the voltage-controlled oscillator segment with the output frequency closest to the target frequency at the set voltage. In other words, the voltage controlled oscillator segment with the closest feedback divided clock frequency and phase discrimination clock frequency is found.
The traditional automatic frequency correction algorithm uses a counting mode, takes a phase discrimination clock and a feedback frequency division clock as clock inputs, and counts independently. The results of the two counters are compared to distinguish the speed of the two clocks. And then adopting a dichotomy, and gradually approaching the voltage-controlled oscillator section corresponding to the target frequency point according to the comparison result. The accuracy of the comparison result depends on the number of comparison cycles. The larger the number of comparison periods is, the longer the comparison time is consumed, the more obvious the relative frequency difference of the two clocks is reflected, and the more accurate the comparison result is.
However, in the low phase-discrimination frequency application scenario, the phase-discrimination clock itself has a longer period, and it takes more total counting time to represent the frequency relative difference in the counting period. In this way the speed of the automatic frequency correction is dependent on the phase discrimination clock frequency.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an automatic frequency correction solution for shortening the automatic frequency correction time, so that the automatic frequency correction speed and accuracy are not affected by the phase discrimination frequency, and for improving the recognition accuracy and speed of the phase discrimination clock and the feedback frequency division clock frequency difference.
In order to achieve the above object and other related objects, the present invention provides the following technical solutions.
An automatic frequency correction circuit for correcting an output frequency of a phase locked loop based on a multi-stage voltage controlled oscillator, comprising:
The first counting module is connected with the phase discrimination clock of the phase-locked loop and counts the phase discrimination clock to obtain a first count value;
The second counting module is connected with the feedback frequency division clock of the phase-locked loop and counts the feedback frequency division clock to obtain a second count value;
The counting comparison module is respectively connected with the first counting module and the second counting module, compares the first counting value with the second counting value, and judges the speed of the feedback frequency division clock relative to the phase discrimination clock to obtain a first judging result;
The high-frequency four-phase clock generation module is used for generating four high-frequency clocks with the same frequency and different phases, and the frequency of the high-frequency clocks is higher than the frequency of the phase discrimination clock and the frequency of the feedback frequency division clock;
The high-frequency four-phase clock auxiliary judging module is respectively connected with the first counting module, the second counting module and the high-frequency four-phase clock generating module, and under the control of four high-frequency clocks, the lowest bit of the first counting value and the lowest bit of the second counting value are sampled and judged, and the speed of the feedback frequency division clock relative to the phase discrimination clock is judged, so that a second judging result is obtained;
The composite judgment and optimal selection module is respectively connected with the counting comparison module and the high-frequency four-phase clock auxiliary judgment module, and a composite judgment result is obtained according to the first judgment result and the second judgment result;
And the section selection logic module is connected with the composite judgment and optimal selection module, and searches the next section of the voltage-controlled oscillator by using a dichotomy according to the composite judgment result until the final section selection of the voltage-controlled oscillator is found.
Optionally, a second of said high frequency clocks is delayed by 90 ° from a first of said high frequency clocks, a third of said high frequency clocks is delayed by 90 ° from the second of said high frequency clocks, and a fourth of said high frequency clocks is delayed by 90 ° from the third of said high frequency clocks.
Optionally, the high-frequency four-phase clock generating module includes four differential amplifying units, the four differential amplifying units are in reverse cascade connection in turn, and the differential output end of the fourth differential amplifying unit is fed back and is in forward cascade connection to the differential input end of the first differential amplifying unit.
Optionally, the phase shift contributed by the differential amplifying unit is 45 °, a first high-frequency clock is obtained at the negative end of the differential output of the second differential amplifying unit, a second high-frequency clock is obtained at the negative end of the differential output of the fourth differential amplifying unit, a third high-frequency clock is obtained at the positive end of the differential output of the second differential amplifying unit, and a fourth high-frequency clock is obtained at the positive end of the differential output of the fourth differential amplifying unit.
Optionally, the high-frequency four-phase clock auxiliary judging module comprises eight sampling units and a high-frequency counting unit,
The four sampling units are respectively connected with the first counting module and the high-frequency four-phase clock generating module, sample the lowest bit of the first counting value under the control of one-to-one correspondence of the four high-frequency clocks to obtain a first sampling value and a second sampling value,
The other four sampling units are respectively connected with the second counting module and the high-frequency four-phase clock generating module, sample the lowest bit of the second counting value under the control of one-to-one correspondence of the four high-frequency clocks to obtain a third sampling value and a fourth sampling value,
The high-frequency counting unit receives the first sampling value and the third sampling value, and controls the high-frequency counting unit to obtain a high-frequency counting value by taking the first sampling value and the third sampling value as indication signals.
Optionally, the high-frequency four-phase clock auxiliary judging module further comprises a high-frequency clock period level deviation calculating unit, a high-frequency clock phase level deviation correcting calculating unit and two adding units,
The high-frequency clock period level deviation calculating unit is connected with the high-frequency counting unit and the two sampling units, takes the first sampling value and the third sampling value as indication signals, obtains the high-frequency count value at corresponding time, calculates and obtains the initial period level phase difference and the current period level phase difference between the feedback frequency division clock and the phase discrimination clock,
The high-frequency clock phase level deviation correction calculation unit receives the second sampling value and the fourth sampling value, calculates and obtains an initial phase deviation correction value and a current phase deviation correction value between the feedback frequency division clock and the phase discrimination clock according to the second sampling value and the fourth sampling value,
The first adding unit is respectively connected with the high-frequency clock period level deviation calculating unit and the high-frequency clock phase level deviation correcting calculating unit, and calculates and obtains the initial clock phase difference between the feedback frequency division clock and the phase discrimination clock according to the initial period level phase difference and the initial phase deviation correcting value,
The second adding unit is respectively connected with the high-frequency clock cycle level deviation calculating unit and the high-frequency clock phase level deviation correcting calculating unit, and calculates and obtains the current clock phase difference between the feedback frequency division clock and the phase discrimination clock according to the current cycle level phase difference and the current phase deviation correcting value.
Optionally, the high-frequency four-phase clock auxiliary judging module further comprises two storage units, a subtracting unit and a comparing unit,
A first one of said memory units is coupled to a first one of said adders for receiving and storing said initial clock phase difference,
A second one of said memory units is coupled to a second one of said adders for receiving and storing said current clock phase difference,
The subtracting unit is respectively connected with the two storage units, calculates the difference value between the current clock phase difference and the initial clock phase difference to obtain the current clock phase difference variation,
The comparison unit is connected with the subtraction unit and compares the current clock phase difference variation with a threshold value to obtain the second judgment result.
Optionally, the composite judgment and optimal selection module preferentially obtains the composite judgment result according to the second judgment result.
An automatic frequency correction method applied to the automatic frequency correction circuit as claimed in any one of the above, comprising:
Determining an initial selection of the voltage controlled oscillator using a dichotomy;
comparing by the high-frequency four-phase clock auxiliary judging module, judging the speed of the feedback frequency division clock relative to the phase discrimination clock, and obtaining the second judging result and the composite judging result;
If the state of the composite judgment result is that the difference is judged in a preset period, ending the comparison of the sections and recording the current continuous period number when the difference is judged, and if the state of the composite judgment result is that the difference is not judged in the preset period, ending the comparison of the sections and directly judging that the corresponding selected section is the final selected section of the voltage-controlled oscillator;
If the state of the composite judgment result is the difference judged in the preset period, updating the optimal selection section according to the current continuous period number, determining the next selection section of the voltage-controlled oscillator by using a bisection method according to the composite judgment result, updating the selection section of the voltage-controlled oscillator, and repeating the comparison judgment step until the state of the composite judgment result in all the bisection method selection sections is the difference judged in the preset period, or until the state of the composite judgment result is the difference not judged in the preset period;
if the state of the composite judgment result under all the dichotomy segments is the difference judged in the preset period after traversing all the dichotomy segments, the optimal segment with the longest duration period is selected as the final segment of the voltage-controlled oscillator.
Optionally, the step of updating the optimal selection according to the current duration period number includes:
And judging whether the current duration period number is larger than the previous duration period number, if so, updating the current selection section into the optimal selection section, and if not, reserving the optimal selection section.
As described above, the automatic frequency correction circuit and method of the present invention have at least the following advantages:
The automatic frequency correction circuit is designed by combining a first counting module, a second counting module, a counting comparison module, a high-frequency four-phase clock generation module, a high-frequency four-phase clock auxiliary judgment module, a compound judgment and optimal selection module and a section selection logic module, the high-frequency four-phase clock auxiliary judgment module samples and judges the lowest position of a first counting value and the lowest position of a second counting value under the control of four high-frequency clocks, the speed of a feedback frequency division clock relative to a phase discrimination clock is judged, a second judgment result is obtained, sampling detection is carried out based on the introduced four high-frequency heterogeneous clocks, the dependence of section selection precision and time on the phase discrimination clock frequency is eliminated, even if the frequency difference of the phase discrimination clock and the feedback frequency division clock is faced to the application occasion of low phase discrimination frequency, the frequency of the high-frequency clock is higher than the frequency of the phase discrimination clock and the frequency of the feedback frequency division clock, the sampling recognition precision is improved, meanwhile, the accuracy of recognition is also dependent on the phase difference between the high-frequency four-phase clocks, the phase difference is small, the accuracy of the detection is high, and the detection precision is more simple, and the problem of the detection clock and the accuracy is more limited is solved.
Drawings
Fig. 1 is a block diagram showing the structure of an automatic frequency correction circuit according to the present invention.
Fig. 2 is a block diagram showing the structure of the high-frequency four-phase clock generating module according to the present invention.
Fig. 3 is a block diagram showing a high-frequency four-phase clock auxiliary judging module according to the present invention.
Fig. 4 is a timing diagram showing the deviation Φ between the phase-discriminating clock fr and the feedback frequency-dividing clock fv according to an alternative embodiment of the present invention.
Fig. 5 is a timing diagram showing the deviation Φ between the phase-discrimination clock fr and the feedback divided clock fv according to another alternative embodiment of the invention.
Fig. 6 is a flowchart showing the comparison and judgment performed by the high-frequency four-phase clock auxiliary judgment module and the selection of the most preferred segment of the VCO according to an alternative embodiment of the present invention.
FIG. 7 is a diagram showing an automatic frequency correction process using an automatic frequency correction circuit according to an alternative embodiment of the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 7. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. The structures, proportions, sizes, etc. shown in the drawings herein are shown in detail for purposes of illustration only, and are not intended to limit the scope of the invention, which is defined in the claims, any structural modification, proportional change or size adjustment should still fall within the scope of the disclosure without affecting the efficacy and achievement of the present invention.
As shown in fig. 1, the present invention provides an automatic frequency correction circuit for correcting an output frequency of a phase-locked loop based on a multi-stage voltage-controlled oscillator, comprising:
The first counting module is connected with a phase discrimination clock fr of the phase-locked loop and counts the phase discrimination clock fr to obtain a first count value Dfr;
The second counting module is connected with the feedback frequency division clock fv of the phase-locked loop and counts the feedback frequency division clock fv to obtain a second count value Dfv;
The counting comparison module is respectively connected with the first counting module and the second counting module, compares the first counting value Dfr with the second counting value Dfv, and judges the speed of the feedback frequency division clock fv relative to the phase discrimination clock fr to obtain a first judging result P1;
The high-frequency four-phase clock generation module generates four high-frequency clocks ck 0-ck 3 with the same frequency and different phases, and the frequency of the high-frequency clocks ck 0-ck 3 is higher than the frequency of the phase discrimination clock fr and the frequency of the feedback frequency division clock fv;
The high-frequency four-phase clock auxiliary judging module is respectively connected with the first counting module, the second counting module and the high-frequency four-phase clock generating module, and under the control of four high-frequency clocks ck 0-ck 3, the lowest bit of the first counting value Dfr and the lowest bit of the second counting value Dfv are sampled and judged, and the speed of the feedback frequency division clock fv relative to the phase discrimination clock fr is judged to obtain a second judging result P2;
the composite judgment and optimal selection module is respectively connected with the counting comparison module and the high-frequency four-phase clock auxiliary judgment module, and a composite judgment result P0 is obtained according to the first judgment result P1 and the second judgment result P2;
And the section selection logic module is connected with the composite judgment and optimal selection module, and searches the next section of the voltage-controlled oscillator VCO by using a dichotomy according to the composite judgment result P0 until the final section selection of the voltage-controlled oscillator VCO is found.
In detail, as shown in fig. 1, the segment selection logic module searches for the next segment of VCO by using a dichotomy according to the composite determination result P0, so as to obtain a VCO segment code, that is, the automatic frequency correction circuit (shown in the dashed frame of fig. 1) adjusts and controls the VCO segment code according to the comparison determination result of the feedback divided clock fv and the phase discrimination clock fr in the phase-locked loop, so as to control the output frequency fvco of the multi-segment VCO in the phase-locked loop, and the output frequency fvco of the multi-segment VCO is fed back and divided by the frequency divider, so as to generate the feedback divided clock fv.
In more detail, as shown in fig. 1, the first counting module counts the phase discrimination clock fr, the phase discrimination clock fr is used as an input clock of the first counting module, the corresponding first counting value Dfr is increased by 1 when one clock rising edge occurs in the phase discrimination clock fr, the second counting module counts the feedback frequency division clock fv, the feedback frequency division clock fv is used as an input clock of the second counting module, and the corresponding second counting value Dfv is increased by 1 when one clock rising edge occurs in the feedback frequency division clock fv.
The increment speeds of the first count value Dfr and the second count value Dfv reflect the frequency speeds of two clocks, and the higher the clock frequency, the faster the increment speed, and the larger the count value reached at the same time.
In more detail, as shown in fig. 1, a conventional counting mode is determined by a counting comparison module, and the first count value Dfr and the second count value Dfv are compared to determine the speed of the feedback frequency division clock fv relative to the phase discrimination clock fr, so as to obtain a first determination result P1.
In detail, in an alternative embodiment of the present invention, the second high frequency clock ck1 lags behind the first high frequency clock ck090 °, the third high frequency clock ck2 lags behind the second high frequency clock ck1 ° and the fourth high frequency clock ck3 lags behind the third high frequency clock ck2 ° 90 °.
In detail, in an alternative embodiment of the present invention, as shown in fig. 2, the high-frequency four-phase clock generating module includes four differential amplifying units, where the four differential amplifying units are sequentially and reversely cascaded, the differential output end of the previous differential amplifying unit is reversely connected with the differential input end of the next differential amplifying unit (i.e. the differential output positive end of the previous differential amplifying unit is connected with the differential input negative end of the next differential amplifying unit, the differential output negative end of the previous differential amplifying unit is connected with the differential input positive end of the next differential amplifying unit), and the differential output end of the fourth differential amplifying unit is fed back and forward cascaded to the differential input end of the first differential amplifying unit (i.e. the differential output positive end of the fourth differential amplifying unit is connected with the differential input positive end of the first differential amplifying unit, and the differential output negative end of the fourth differential amplifying unit is connected with the differential input negative end of the first differential amplifying unit), so that the four differential amplifying units form a feedback loop to form a differential ring oscillator.
Wherein the positive power supply of each differential amplifying unit is connected with a positive power supply VCC, and the negative power supply of each differential amplifying unit is connected with a negative power supply VSS.
In more detail, as shown in fig. 2, the differential ring oscillator (i.e., the high-frequency four-phase clock generating module) has a phase shift of 180 ° contributed by a four-stage differential amplifier (with a delay function) during oscillation, i.e., a phase shift of 180 °/4=45° contributed by each stage of differential amplifying unit, a signal phase shift of 90 ° contributed by two stages of differential amplifying units, and a high-frequency clock with high frequency out of phase can be obtained by taking the differential signals of two stages at intervals.
Specifically, a first high-frequency clock ck0 is obtained at the negative end of the differential output IP of the second differential amplifying unit, a second high-frequency clock ck1 is obtained at the negative end QP of the differential output QP of the fourth differential amplifying unit, a third high-frequency clock ck2 is obtained at the positive end IN of the differential output of the second differential amplifying unit, and a fourth high-frequency clock ck3 is obtained at the positive end QN of the differential output of the fourth differential amplifying unit. Taking the phase of the first high-frequency clock ck0 as a reference zero point, the phase of the first high-frequency clock ck0 is 0 DEG, the phase of the second high-frequency clock ck1 is 90 DEG, the phase of the third high-frequency clock ck2 is 180 DEG, and the phase of the fourth high-frequency clock ck3 is 270 deg.
It can be understood that four high-frequency clocks ck0 to ck3 may be obtained at the output end of the first differential amplifying unit and the output end of the third differential amplifying unit, and meanwhile, the high-frequency clocks are not limited to four, five, six, eight and the like, and the phase difference between two adjacent high-frequency clocks is not limited to 90 degrees, 45 degrees, 60 degrees and the like, and can be flexibly adjusted according to the sampling judgment precision in the frequency correction, which is not limited herein.
In detail, in an alternative embodiment of the present invention, as shown in fig. 3, the high-frequency four-phase clock auxiliary judging module includes eight sampling units and a high-frequency counting unit,
The four sampling units are respectively connected with the first counting module and the high-frequency four-phase clock generating module, under the control of one-to-one correspondence of the four high-frequency clocks ck 0-ck 3, the lowest bit LSB_ Dfr of the first counting value Dfr is sampled to obtain a first sampling value fr_s0 and a second sampling value sample_fr,
The other four sampling units are respectively connected with the second counting module and the high-frequency four-phase clock generating module, under the control of one-to-one correspondence of the four high-frequency clocks ck 0-ck 3, the lowest bit LSB_ Dfv of the second counting value Dfv is sampled to obtain a third sampling value fv_s0 and a fourth sampling value sample_fv,
The high-frequency counting unit receives the first sampling value fr_s0 and the third sampling value fv_s0, takes the first sampling value fr_s0 and the third sampling value fv_s0 as indication signals, controls a high-frequency counter inside the high-frequency counting unit, and outputs high-frequency count values Dfr & fv corresponding to time points.
The output samples of the first four sampling units are fr_s0, fr_s1, fr_s2 and fr_s3, the second sample value sample_fr is a combination of the three samples fr_s1, fr_s2 and fr_s3, the output samples of the second four sampling units are fv_s0, fv_s1, fv_s2 and fv_s3, and the fourth sample value sample_fv is a combination of the three samples fv_s1, fv_s2 and fv_s3, which are not described herein.
In detail, as shown in fig. 3, the high-frequency four-phase clock auxiliary judging module further comprises a high-frequency clock period level deviation calculating unit, a high-frequency clock phase level deviation correcting calculating unit and two adding units,
The high-frequency clock period level deviation calculating unit is connected with the high-frequency counting unit and the two sampling units, takes the first sampling value fr_s0 and the third sampling value fv_s0 as indication signals, obtains the high-frequency count value Dfr & fv at corresponding time, calculates and obtains the initial period level phase difference T0 and the current period level phase difference T (T) between the feedback frequency division clock fv and the phase discrimination clock fr according to the high-frequency count value Dfr & fv,
The high-frequency clock phase level deviation correction calculation unit receives a second sampling value sample_fr and a fourth sampling value sample_fv, and calculates an initial phase deviation correction value between a feedback frequency division clock fv and a phase discrimination clock fr according to the second sampling value sample_fr and the fourth sampling value sample_fvCurrent phase deviation correction value
The first adding unit is connected with the high-frequency clock period level deviation calculating unit and the high-frequency clock phase level deviation correcting calculating unit respectively and is used for correcting the value according to the initial period level phase difference T0 and the initial phase deviationThe initial clock phase difference phi 0 between the feedback divided clock fv and the phase discrimination clock fr is calculated,
The second adding unit is respectively connected with the high-frequency clock period level deviation calculating unit and the high-frequency clock phase level deviation correcting calculating unit and is used for correcting the value according to the current period level phase difference T (T) and the current phase deviationThe current clock phase difference phi (t) between the feedback frequency division clock fv and the phase discrimination clock fr is calculated.
In detail, as shown in fig. 3, the high-frequency four-phase clock auxiliary judging module further comprises two storage units, a subtracting unit and a comparing unit,
The first memory unit is connected with the first adder, receives and stores the initial clock phase difference phi 0,
The second memory unit is connected with the second adder and receives and stores the current clock phase difference phi (t),
The subtracting unit is respectively connected with the two storage units, calculates the difference value between the current clock phase difference phi (t) and the initial clock phase difference phi 0, obtains the current clock phase difference variation delta phi (t),
The comparison unit is connected with the subtraction unit and compares the current clock phase difference variation delta phi (t) with the threshold value to obtain a second judgment result P2.
In more detail, as shown in fig. 3, in the high-frequency four-phase clock auxiliary judging module, in combination with two sampling units and a high-frequency counting unit, the high-frequency clock ck0 is used for identifying a time difference between a change edge of the lowest bit lsb_ Dfr of the first count value Dfr obtained by counting the phase discrimination clock fr and a change edge of the lowest bit lsb_ Dfv of the second count value Dfv obtained by counting the corresponding feedback frequency division clock fv, the high-frequency count values Dfr & fv represent the time difference, the time difference is in units of clock periods of the high-frequency clock ck0, and a period level deviation between the phase discrimination clock fr and the feedback frequency division clock fv can be calculated based on the high-frequency count values Dfr & fv.
Meanwhile, the lowest bit lsb_ Dfr of the first count value Dfr obtained by counting the phase discrimination clock fr and the lowest bit lsb_ Dfv of the second count value Dfv obtained by counting the feedback frequency division clock fv are respectively sampled by combining the other six sampling units and the high-frequency clocks ck1, ck2 and ck3, so as to obtain a second sampling value sample_fr and a fourth sampling value sample_fv. Because of the characteristic that the phases of the four-phase clocks ck0 to ck3 are sequentially arranged, the value of the second sampling value sample_fr can reflect the position of the change edge of the least significant bit LSB_ Dfr of the first counting value Dfr obtained by counting the phase discrimination clock fr between the clock edges of the four-phase clocks ck0 to ck3, and the value of the fourth sampling value sample_fv can reflect the position of the change edge of the least significant bit LSB_ Dfv of the second counting value Dfv obtained by counting the feedback frequency division clock fv between the clock edges of the four-phase clocks ck0 to ck 3. Due to the characteristic of equal-interval delay of the phases of the four-phase clocks ck 0-ck 3, along with the difference of the positions between the rising edges of the four-phase clocks ck 0-ck 3 at the change moment of the LSB_ Dfr or the LSB_ Dfv, the sampling result also shows a specific rule. According to the law, the positions of the change moments among the rising edges of the four out-of-phase clocks ck 0-ck 3 can be calculated. This is equivalent to considering four equally spaced rising edges of the high frequency four-phase clocks ck 0-ck 3 as four scales, the time of change of LSB_ Dfr or LSB_ Dfv being placed in a measurement system with a measurement accuracy of one quarter of the high frequency clock period.
In detail, as shown in FIG. 3, when calculating the deviation between the phase discrimination clock fr and the feedback frequency division clock fv, the high-frequency clock cycle deviation calculating unit calculates the cycle deviation T between the phase discrimination clock fr and the feedback frequency division clock fv according to the high-frequency count value Dfr & fv, the cycle deviation T is in the unit of the clock cycle of the high-frequency clock ck0, and the high-frequency clock phase deviation correcting calculating unit calculates the phase deviation between the feedback frequency division clock fv and the phase discrimination clock fr according to the second sampling value sample_fr and the fourth sampling value sample_fvDeviation of phase levelIn units of one quarter of a clock cycle of the high-frequency clock ck0, and finally, the cycle level deviation T and the phase level deviation are superimposedThe deviation phi between the phase discrimination clock fr and the feedback frequency division clock fv can be calculated.
In detail, in an alternative embodiment of the present invention, as shown in fig. 4, counting is performed with the high frequency clock ck0, by rounding up, the difference between the rising edge of lsb_ Dfr and the rising edge of lsb_ Dfv spans about 3 clock periods of the high frequency clock ck0, and further, the phase level deviation of one fourth of the high frequency clock periods is accurate, the corresponding second sampling value sample_fr is 001, the fourth sampling value sample_fv is 001, and the phase level deviation correction value of the two is 0, so that the deviation Φ between the phase discrimination clock fr and the feedback frequency division clock fv is 3 clock periods of the high frequency clock ck 0.
In detail, in an alternative embodiment of the present invention, as shown in fig. 5, counting is performed with the high frequency clock ck0, by rounding up, the difference between the rising edge of lsb_ Dfr and the rising edge of lsb_ Dfv spans approximately 2 clock periods of the high frequency clock ck0, and further, the phase level deviation of one fourth of the high frequency clock periods is accurate, the corresponding second sampling value sample_fr is 000, the fourth sampling value sample_fv is 001, and the phase level deviation correction value of the two is-1, so that the deviation Φ between the phase discrimination clock fr and the feedback frequency division clock fv is (2-1/4) clock periods of the high frequency clock ck 0.
Thus, the time interval from the change edge of lsb_ Dfr to the change edge of lsb_ Dfv can be modified according to the value change of the second sample value sample_fr to the fourth sample value sample_fv. The correction accuracy can reach the accuracy of the phase difference between two adjacent four-phase clocks, namely, one quarter of the period of the high-frequency detection clock.
In more detail, as shown in fig. 3, by setting the start flag, the initial period stage phase difference T0 between the feedback divided clock fv and the phase discrimination clock fr is calculated by the high-frequency clock period stage deviation calculating unit, and the initial phase deviation correction value between the feedback divided clock fv and the phase discrimination clock fr is calculated by the high-frequency clock phase stage deviation correction calculating unitSuperimposing the initial period phase difference T0 and the initial phase deviation correction value by an addition unitThe initial phase difference (i.e., the initial clock phase difference Φ0, in quarter of the high frequency clock period) between the feedback divided clock fv and the phase-discriminating clock fr at the start of the comparison can be derived. The same calculation is performed on the rising edge of each of lsb_ Dfr and lsb_ Dfv, and the same calculation is subtracted from the initial phase difference value, so that the change amount of the phase difference value (i.e., the current clock phase difference change amount ΔΦ (t)) can be obtained, and the change amount is derived from the accumulation of the period difference values of the phase discrimination clock fr and the feedback frequency division clock fv, and reflects the frequency difference of the phase discrimination clock fr and the feedback frequency division clock fv. When the change amount of the phase difference value exceeds the set threshold value, the judgment of the frequency speed of the phase discrimination clock fr and the feedback frequency division clock fv can be obtained, and a second judgment result P2 is obtained.
In more detail, as shown in fig. 1, the composite judgment and optimal selection module is respectively connected with the count comparison module and the high-frequency four-phase clock auxiliary judgment module, and a composite judgment result P0 is obtained according to the first judgment result P1 and the second judgment result P2. That is, the composite judgment logic in the invention supports the high-frequency four-phase clock auxiliary judgment of the high-frequency four-phase clock auxiliary judgment module or the traditional counting mode judgment of the counting comparison module, and the composite judgment and optimal selection module preferentially supports the high-frequency four-phase clock auxiliary judgment of the high-frequency four-phase clock auxiliary judgment module. When the high-frequency four-phase clock auxiliary judging function of the high-frequency four-phase clock auxiliary judging module is closed, the first count value Dfr and the second count value Dfv are directly compared through the count comparing module to obtain a first judging result P1, and judging of the frequency speed of the phase discrimination clock fr and the frequency speed of the feedback frequency division clock fv is completed. When the high-frequency four-phase clock auxiliary judging function of the high-frequency four-phase clock auxiliary judging module is started, the least significant bit LSB_ Dfr of the first count value Dfr and the least significant bit LSB_ Dfv of the second count value Dfv are introduced into the high-frequency four-phase clock auxiliary judging module for judging the clock speed. The varying frequency of lsb_ Dfr and lsb_ Dfv is equivalent to two frequency halves of their input clocks, thereby reducing the frequency requirements for the high frequency detection clock. Meanwhile, the influence caused by the uncertainty of the duty ratio of the phase discrimination clock fr and the feedback frequency division clock fv is eliminated. The segment selection logic module searches the next segment of the voltage-controlled oscillator VCO according to the conclusion (namely the composite judgment result P0) obtained by the composite judgment until the final segment selection of the voltage-controlled oscillator VCO is found.
In detail, fig. 6 shows a comparison judgment based on the high-frequency four-phase clock auxiliary judgment module and a selection flow of the most preferred segment of the VCO.
In detail, as shown in fig. 6, the first counting module for counting the phase discrimination clock fr is also approaching to the set maximum comparison cycle number while the high-frequency four-phase clock auxiliary judging module is operating. Before the first count value Dfr output by the first count module reaches the maximum comparison cycle number, if the high-frequency four-phase clock auxiliary judging module identifies the frequency difference between the phase discrimination clock fr and the feedback frequency division clock fv, the first count value Dfr at the moment is recorded. This value represents the time required to identify the frequency deviation between the phase-discriminating clock fr and the feedback divided clock fv. As described above, the amount of change in the phase difference identifying lsb_ Dfr and lsb_ Dfv results from the accumulation of the period difference between the phase discrimination clock fr and the feedback frequency division clock fv. The larger the difference between the two clock cycles, the faster the accumulation and the shorter the identification time. The smaller the period difference, the slower the accumulation, the longer the identification time, and the closer the selected output frequency fvco of the voltage controlled oscillator VCO to the target frequency. The value of the selection with the longest identification time is saved as the historical best selection. When the segment selection logic module sequentially compares all possible segments according to the dichotomy, the historical optimal segment selection is selected as a final target segment.
After receiving the second determination result P2 provided by the high-frequency four-phase clock auxiliary determination module, the composite determination and optimal selection module records the count value (i.e., the first count value Dfr) of the current phase-discrimination clock fr. Theoretically, the longer the time required for making the judgment, the smaller the frequency difference between the phase discrimination clock fr and the feedback frequency division clock fv. This judgment time is reflected on the count value of the phase discrimination clock fr, and the longer the time to reach the judgment conclusion, the larger the count value of the phase discrimination clock fr. The smaller the frequency difference between the phase discrimination clock fr and the feedback divided clock fv, the more representative the accuracy of the selected VCO segment under fixed control voltage conditions. After the comparison of all VCO segments is completed, if no segment is found for which the two clock frequencies are exactly identical, the segment selection logic module will select the VCO segment for which the difference was most recently identified.
The method comprises the steps of determining the next selected section of a voltage-controlled oscillator according to a compound judgment result by using a dichotomy, updating the selected section of the voltage-controlled oscillator, repeating the comparison judgment step until the counted value of all the dichotomy selected sections or the counted value of the phase discrimination clock fr reaches the set maximum comparison period number, the high-frequency four-phase clock auxiliary judgment module still does not recognize the frequency difference between the phase discrimination clock fr and the feedback frequency division clock fv after traversing all the dichotomy selected sections of the voltage-controlled oscillator, and selecting the voltage-controlled oscillator section from which the difference is detected if all the selected sections can recognize the frequency difference between the phase discrimination clock fr and the feedback frequency division clock fv before the counted value of the phase discrimination clock fr reaches the set maximum comparison period number after traversing all the dichotomy selected sections of the voltage-controlled oscillator, namely the high-frequency four-phase clock auxiliary judgment module still does not recognize the frequency difference between the phase discrimination clock fr and the feedback frequency division clock fv when the counted value of the phase discrimination clock fr reaches the set maximum comparison period number (namely, the frequency of the phase discrimination clock fr is not recognized as the maximum comparison period number after traversing all the dichotomy selected sections of the voltage-controlled oscillator), and the phase discrimination clock fr is automatically judged to be one of the maximum comparison period number after traversing the phase-division clock fr, and the frequency difference is not recognized by the greatest than the preset threshold value of the greatest frequency of the phase discrimination clock fV, and the frequency is counted by the greatest frequency of the phase discrimination clock f (namely the phase discrimination clock f is detected by the greatest than the greatest frequency threshold value after the greatest frequency is detected by the greatest frequency and the greatest frequency division value is detected by the greatest frequency and the phase comparison clock cycle).
It should be emphasized that only the process of comparing and judging by the high-frequency four-phase clock auxiliary judging module is developed, and the process of performing conventional comparison and judging by the counting and comparing module can be analyzed by referring to the prior art, and is not repeated here.
Meanwhile, the invention also provides an automatic frequency correction method based on fig. 1 and 6, which is applied to the automatic frequency correction circuit and comprises the following steps:
s1, determining an initial section of a voltage-controlled oscillator by using a dichotomy;
s2, comparing by a high-frequency four-phase clock auxiliary judging module, judging the speed of the feedback frequency division clock fv relative to the phase discrimination clock fr, and obtaining a second judging result P2 and a composite judging result P0;
S3, if the state of the composite judgment result P0 is that the difference is judged in a preset period, ending the comparison of the sections and recording the current continuous period number when the difference is judged, and if the state of the composite judgment result P0 is that the difference is not judged in the preset period, ending the comparison of the sections and directly judging that the corresponding selected section is the final selected section of the voltage-controlled oscillator;
S4, if the state of the composite judgment result P0 is the difference in the preset period, updating the optimal section according to the current continuous period number, determining the next section of the voltage-controlled oscillator by using a dichotomy according to the composite judgment result P0, updating the section of the voltage-controlled oscillator, and repeating the steps S2-S3 until the state of the composite judgment result P0 in the preset period is judged in the state of the composite judgment result P0 in the preset period after traversing all the dichotomy sections, or until the state of the composite judgment result P0 is found out;
And S5, if the state of the composite judgment result P0 under all the dichotomy segments is the difference judged in the preset period after traversing all the dichotomy segments, selecting the optimal segment with the longest duration period as the final segment of the voltage-controlled oscillator.
In detail, in step S4, the step of updating the best selection according to the current number of continuous periods further includes:
and judging whether the current duration period number is larger than the previous duration period number, if so, updating the current selection section to be the optimal selection section, and if not, reserving the optimal selection section.
In an alternative embodiment of the present invention, the technical effect of the automatic frequency correction circuit is verified, and a graph of the control voltage v_tune of the VCO and the time variation of the output frequency freq (i.e., fvco) during operation is shown in fig. 7. As can be seen from FIG. 7, the graph is divided into three phases according to the change of the control voltage v_tune, wherein the first phase is a code transmitting phase for configuring parameters such as frequency dividing value, the second phase is an automatic frequency correcting phase, the control voltage v_tune is an open-loop fixed voltage, the third phase is a closed-loop phase locking phase, and the control voltage v_tune is switched from the open-loop fixed voltage to the closed-loop phase locking voltage to finish the final phase locking operation. The automatic frequency correction process can accurately identify the voltage-controlled oscillator section with smaller frequency deviation under the assistance of the high-frequency four-phase clock auxiliary judging module, and can rapidly screen out the voltage-controlled oscillator section with larger frequency deviation, so that the correction speed and accuracy are improved.
The implementation result shows that the automatic frequency correction circuit provided by the invention has the advantages of accuracy and high efficiency, and can be applied to a multistage VCO clock phase-locked loop chip which needs to quickly finish frequency hopping locking.
In summary, in the automatic frequency correction circuit and the method provided by the invention, the first counting module, the second counting module, the counting comparison module, the high-frequency four-phase clock generation module, the high-frequency four-phase clock auxiliary judgment module, the compound judgment and optimal selection module and the section selection logic module are combined to design the automatic frequency correction circuit, the high-frequency four-phase clock auxiliary judgment module samples and judges the lowest position of the first counting value and the lowest position of the second counting value under the control of four high-frequency clocks, judges the speed of the feedback frequency division clock relative to the phase discrimination clock to obtain a second judgment result, carries out sampling detection based on the introduced four high-frequency heterogeneous clocks, gets rid of the dependence of the section selection precision and time on the phase discrimination clock frequency, can rapidly and accurately distinguish the frequency difference of the phase discrimination clock and the feedback frequency division clock even facing the application occasion of low phase discrimination frequency, improves the frequency correction speed and precision of a phase-locked loop, and improves the frequency of the phase discrimination clock, and the frequency of the feedback frequency division clock, simultaneously, the accuracy of the phase discrimination clock is higher than the frequency of the phase discrimination clock, the phase difference between the four phase discrimination clocks is higher than the frequency, the phase difference between the phase discrimination clock is more accurate, the phase difference detection efficiency is higher, and the phase difference is more accurate, and the problem is avoided, and the process is more limited.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. An automatic frequency correction circuit for correcting an output frequency of a phase locked loop based on a multi-stage voltage controlled oscillator, comprising:
The first counting module is connected with the phase discrimination clock of the phase-locked loop and counts the phase discrimination clock to obtain a first count value;
The second counting module is connected with the feedback frequency division clock of the phase-locked loop and counts the feedback frequency division clock to obtain a second count value;
The counting comparison module is respectively connected with the first counting module and the second counting module, compares the first counting value with the second counting value, and judges the speed of the feedback frequency division clock relative to the phase discrimination clock to obtain a first judging result;
The high-frequency four-phase clock generation module is used for generating four high-frequency clocks with the same frequency and different phases, and the frequency of the high-frequency clocks is higher than the frequency of the phase discrimination clock and the frequency of the feedback frequency division clock;
The high-frequency four-phase clock auxiliary judging module is respectively connected with the first counting module, the second counting module and the high-frequency four-phase clock generating module, and under the control of four high-frequency clocks, the lowest bit of the first counting value and the lowest bit of the second counting value are sampled and judged, and the speed of the feedback frequency division clock relative to the phase discrimination clock is judged, so that a second judging result is obtained;
The composite judgment and optimal selection module is respectively connected with the counting comparison module and the high-frequency four-phase clock auxiliary judgment module, and a composite judgment result is obtained according to the first judgment result and the second judgment result;
And the section selection logic module is connected with the composite judgment and optimal selection module, and searches the next section of the voltage-controlled oscillator by using a dichotomy according to the composite judgment result until the final section selection of the voltage-controlled oscillator is found.
2. The automatic frequency correction circuit of claim 1, wherein a second one of said high frequency clocks lags a first one of said high frequency clocks by 90 °, a third one of said high frequency clocks lags a second one of said high frequency clocks by 90 °, and a fourth one of said high frequency clocks lags a third one of said high frequency clocks by 90 °.
3. The automatic frequency correction circuit according to claim 2, wherein the high-frequency four-phase clock generation module comprises four differential amplification units, the four differential amplification units are reversely cascaded in turn, and the differential output terminal of the fourth differential amplification unit is fed back and forwardly cascaded to the differential input terminal of the first differential amplification unit.
4. An automatic frequency correction circuit according to claim 3, characterized in that the phase shift contributed by said differential amplifying units is 45 °, a first said high frequency clock is obtained at the negative end of the differential output of the second said differential amplifying unit, a second said high frequency clock is obtained at the negative end of the differential output of the fourth said differential amplifying unit, a third said high frequency clock is obtained at the positive end of the differential output of the second said differential amplifying unit, and a fourth said high frequency clock is obtained at the positive end of the differential output of the fourth said differential amplifying unit.
5. The automatic frequency correction circuit according to claim 1, wherein,
The high-frequency four-phase clock auxiliary judging module comprises eight sampling units and a high-frequency counting unit,
The four sampling units are respectively connected with the first counting module and the high-frequency four-phase clock generating module, and sample the lowest bit of the first count value under the control of one-to-one correspondence of the four high-frequency clocks to obtain a first sampling value and a second sampling value, wherein the four sampling units comprise a first sampling unit, a second sampling unit, a third sampling unit and a fourth sampling unit, the first sampling value is the sampling value of the first sampling unit, and the second sampling value is the combination of the sampling values of the second sampling unit, the third sampling unit and the fourth sampling unit;
The other four sampling units are respectively connected with the second counting module and the high-frequency four-phase clock generating module, and sample the lowest bit of the second counting value under the control of one-to-one correspondence of the four high-frequency clocks to obtain a third sampling value and a fourth sampling value, wherein the other four sampling units comprise a fifth sampling unit, a sixth sampling unit, a seventh sampling unit and an eighth sampling unit, the third sampling value is a sampling value of the fifth sampling unit, and the fourth sampling value is a combination of sampling values of the sixth sampling unit, the seventh sampling unit and the eighth sampling unit;
the high-frequency counting unit receives the first sampling value and the third sampling value, and controls the high-frequency counting unit to obtain a high-frequency counting value by taking the first sampling value and the third sampling value as indication signals.
6. The automatic frequency correction circuit according to claim 5, wherein,
The high-frequency four-phase clock auxiliary judging module also comprises a high-frequency clock period level deviation calculating unit, a high-frequency clock phase level deviation correcting calculating unit and two adding units,
The high-frequency clock period level deviation calculating unit is connected with the high-frequency counting unit, the first sampling unit and the fifth sampling unit, takes the first sampling value and the third sampling value as indication signals, obtains the high-frequency count value at corresponding time, calculates and obtains the initial period level phase difference and the current period level phase difference between the feedback frequency division clock and the phase discrimination clock,
The high-frequency clock phase level deviation correction calculation unit receives the second sampling value and the fourth sampling value, calculates and obtains an initial phase deviation correction value and a current phase deviation correction value between the feedback frequency division clock and the phase discrimination clock according to the second sampling value and the fourth sampling value,
The first adding unit is respectively connected with the high-frequency clock period level deviation calculating unit and the high-frequency clock phase level deviation correcting calculating unit, and calculates and obtains the initial clock phase difference between the feedback frequency division clock and the phase discrimination clock according to the initial period level phase difference and the initial phase deviation correcting value,
The second adding unit is respectively connected with the high-frequency clock cycle level deviation calculating unit and the high-frequency clock phase level deviation correcting calculating unit, and calculates and obtains the current clock phase difference between the feedback frequency division clock and the phase discrimination clock according to the current cycle level phase difference and the current phase deviation correcting value.
7. The automatic frequency correction circuit according to claim 6, wherein,
The high-frequency four-phase clock auxiliary judging module also comprises two storage units, a subtracting unit and a comparing unit,
A first one of said storage units is connected to a first one of said addition units, receives and stores said initial clock phase difference,
The second storage unit is connected with the second addition unit and receives and stores the current clock phase difference,
The subtracting unit is respectively connected with the two storage units, calculates the difference value between the current clock phase difference and the initial clock phase difference to obtain the current clock phase difference variation,
The comparison unit is connected with the subtraction unit and compares the current clock phase difference variation with a threshold value to obtain the second judgment result.
8. The automatic frequency correction circuit according to claim 1, wherein the composite determination and optimal selection module preferentially obtains the composite determination result according to the second determination result.
9. An automatic frequency correction method, characterized by being applied to an automatic frequency correction circuit according to any one of claims 1 to 8, comprising:
Determining an initial selection of the voltage controlled oscillator using a dichotomy;
comparing by the high-frequency four-phase clock auxiliary judging module, judging the speed of the feedback frequency division clock relative to the phase discrimination clock, and obtaining the second judging result and the composite judging result;
If the state of the composite judgment result is that the difference is judged in a preset period, ending the comparison of the sections and recording the current continuous period number when the difference is judged, and if the state of the composite judgment result is that the difference is not judged in the preset period, ending the comparison of the sections and directly judging that the corresponding selected section is the final selected section of the voltage-controlled oscillator;
If the state of the composite judgment result is the difference judged in the preset period, updating the optimal selection section according to the current continuous period number, determining the next selection section of the voltage-controlled oscillator by using a bisection method according to the composite judgment result, updating the selection section of the voltage-controlled oscillator, and repeating the comparison judgment step until the state of the composite judgment result in all the bisection method selection sections is the difference judged in the preset period, or until the state of the composite judgment result is the difference not judged in the preset period;
if the state of the composite judgment result under all the dichotomy segments is the difference judged in the preset period after traversing all the dichotomy segments, the optimal segment with the longest duration period is selected as the final segment of the voltage-controlled oscillator.
10. The automatic frequency correction method of claim 9, wherein the step of updating the optimal selection according to the current number of sustain periods comprises:
And judging whether the current duration period number is larger than the previous duration period number, if so, updating the current selection section into the optimal selection section, and if not, reserving the optimal selection section.
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| CN102868395B (en) * | 2012-10-11 | 2015-12-16 | 广州润芯信息技术有限公司 | Phase-locked loop frequency integrator and open loop frequency coarse tuning method |
| CN203104411U (en) * | 2012-12-28 | 2013-07-31 | 重庆西南集成电路设计有限责任公司 | A phase-locking frequency synthesizer and an adaptive frequency calibrating circuit |
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