CN117667467A - A method for dealing with memory failures and related equipment - Google Patents

Abstract

This application discloses a method for handling memory faults and related equipment, which are applied in the storage field. The method includes: obtaining the uncorrectable error information of the first memory, the uncorrectable error information including the fault address, then obtaining the first target data corresponding to the fault address from the second memory, and writing the first target data into the first memory. Fault address, where the first memory and the second memory are mirror memories of each other, and the second target data located at the fault address of the first memory is verified. The second target data is to write the fault address of the first memory into the first target. After the data is retrieved, if the second target data is verified to be fault data, the fault address of the first memory is marked as the address to be isolated, and a page soft isolation operation is performed on the address to be isolated. In this application, the page soft isolation operation is performed on the faulty address to ensure the normal use of other memory spaces in the first memory without the need to release the mirror mode of the memory.

Description

A method for dealing with memory failures and related equipment

Technical field

Embodiments of the present application relate to the field of storage, and in particular, to a method of handling memory faults and related equipment.

Background technique

Most current computing devices use memory mirroring mode, which sets the memory spaces of two independent physical memory channels to back up each other. The two memory spaces have the same address space and store the same data at the same address, and among them One memory channel is set as the primary channel, and the other memory channel is set as the backup channel. This ensures that even if the main channel memory fails, correct data can still be obtained from the memory device of the backup channel, ensuring the normal operation of the computing device.

After the computing device turns on the memory mirroring mode, if the memory controller detects that an uncorrectable error (UCE) fault occurs in the memory data on the main channel during operation, the memory controller will start from the same memory space corresponding to the backup channel. The data is read from the address and the faulty memory address in the memory space corresponding to the main channel is repaired. However, when the data cannot be repaired, the UCE fault is considered to be a memory hard failure UCE. At this time, the memory controller will remove the main channel. In the mirroring relationship between the memory space corresponding to the channel and the memory space corresponding to the backup channel, only the memory space corresponding to the backup channel is used.

However, undoing the mirroring relationship between the memory space corresponding to the main channel and the memory space corresponding to the backup channel causes the memory space corresponding to the entire main channel to be unavailable except for the failed memory address.

Contents of the invention

This application provides a method for handling memory failures and related equipment, which are applied in the storage field. This method of handling memory faults can accurately locate the precise location of the memory fault without removing the mirror mode of the memory.

The first aspect provides a method for handling memory failures, including:

Obtain uncorrectable error information of the first memory, where the uncorrectable error information includes the fault address.

Obtain the first target data corresponding to the fault address from the second memory, and write the first target data to the fault address of the first memory, where the first memory and the second memory are mirror memories of each other.

Verify the second target data located at the fault address of the first memory. If the second target data is verified to be fault data, mark the fault address of the first memory as the address to be isolated.

Perform page soft isolation operation on the address to be isolated.

In the implementation of this application, the fault address of a hard failure UCE fault is marked as an address to be isolated, and a page soft isolation operation is performed on it, thereby achieving accurate isolation of the fault address without causing any impact on other memory addresses. Therefore, there is no need to cancel the mirror relationship between the first memory and the second memory, so that the remaining memory space in the first memory except the fault address can still support reading and writing normally, avoiding the normal memory in the first memory after canceling the mirror relationship. The space cannot be used, which increases the probability of using the first memory, reduces the scope of adverse effects of memory hard failure UCE, avoids wasting memory resources, and greatly reduces the probability of the memory mirroring mode being released.

In a possible implementation of the first aspect, the fault address of the first memory is marked as the address to be isolated based on the identification to be isolated.

In the embodiment of the present application, multiple methods are used to realize that the to-be-isolated identification marks the fault address of the first memory as the to-be-isolated address, which reflects the diversity and selectivity of the solution.

In a possible implementation of the first aspect, the operating system (operating system, OS) performs a page soft isolation operation on the isolation address.

In the implementation of the present application, the computing device performs the page soft isolation operation on the address to be isolated through the OS, which embodies the specific implementation of the solution. It will not affect other normal memory spaces of the first memory, and there is no need to release the first memory from the third memory. The mirror relationship between the two memories.

In a possible implementation of the first aspect, a general hardware error source (GHES) table is generated, and the GHES table includes the fault address and the corresponding identification to be isolated.

In the embodiment of the present application, by including the fault address and the corresponding identification to be isolated in the GHES table, the corresponding fault address can be determined as the address to be isolated based on the identification to be isolated from the GHES table, which embodies the specific implementation of the solution and embodies the The reliability of the scheme.

In a possible implementation of the first aspect, the fault level of the fault address in the GHES table is correctable.

In the embodiment of the present application, this reflects that the fault occurring at the fault address will not have a negative impact on the operation of the computing device.

In a possible implementation of the first aspect, the OS performs a page soft isolation operation on the fault address in the GHES table whose fault level is correctable and whose fault level is to be isolated and corresponding to the isolation identification.

In the implementation manner of this application, the specific implementation manner of the solution is reflected, and the reliability of the solution is reflected.

In a second aspect, a computing device is provided. The computing device includes a processor, a first memory, a second memory, and a memory controller. The first memory and the second memory are connected to the memory controller, and the memory controller is connected to the processor. And the first memory and the second memory are mirror memories of each other.

Wherein, the memory controller is used to obtain uncorrectable error information of the first memory, where the uncorrectable error information includes a fault address.

The memory controller is also used to obtain the first target data corresponding to the fault address from the second memory, and write the first target data into the fault address of the first memory.

The memory controller is also used to verify the second target data located at the fault address of the first memory.

The processor is configured to mark the fault address of the first memory as the address to be isolated if the second target data is verified to be fault data.

The processor is also used to perform page soft isolation operations on the addresses to be isolated.

In the embodiment of the present application, the processor is specifically configured to mark the fault address of the first memory as the address to be isolated based on the identification to be isolated.

In a possible implementation of the second aspect, the processor generates a GHES table, and the GHES table includes the fault address and the corresponding identification to be isolated.

In a possible implementation of the second aspect, the fault level of the fault address in the GHES table is correctable.

In a possible implementation of the second aspect, the processor is specifically configured to perform the page soft isolation operation through the OS on the fault address in the GHES table whose fault level is correctable and corresponding to the identification to be isolated.

For the beneficial effects of the second aspect, please refer to the first aspect and will not be described again here.

In a third aspect, another computing device is provided, which may include a processor coupled to a memory, where the memory is used to store instructions, and the processor is used to execute instructions in the memory so that the computing device executes the first aspect of the present application or the third aspect. On the one hand any of the methods described in the possible implementations.

In a fourth aspect, another computing device is provided, including a processor for executing a computer program (or computer-executable instructions) stored in a memory. When the computer program (or computer-executable instructions) is executed, the computer program (or computer-executable instructions) is executed as described in the fourth aspect. Methods in one aspect and various possible implementations of the first aspect.

In one possible implementation, the processor and memory are integrated;

In another possible implementation, the above-mentioned memory is located outside the computing device.

The computing device also includes a communication interface for the computing device to communicate with other devices, such as the transmission or reception of data and/or signals. For example, the communication interface may be a transceiver, a circuit, a bus, a module, or other types of communication interfaces.

The fifth aspect provides a computer-readable storage medium that includes computer-readable instructions. When the computer-readable instructions are run on a computer, the first aspect of the present application or any one of the first aspects may be implemented.

In a sixth aspect, a computer program product is provided, which includes computer-readable instructions. When the computer-readable instructions are run on a computer, the first aspect of the present application or any one of the first aspects may be implemented.

Description of drawings

Figure 1 is a schematic diagram of the processing flow of the mirror scrub mechanism;

Figure 2 is an architectural schematic diagram of a computing device provided by an embodiment of the present application;

Figure 3 is a schematic flowchart of a method for handling memory failures provided by an embodiment of the present application;

Figure 4 is a schematic diagram of determining the hard failure type UCE provided by the embodiment of the present application;

Figure 5 is a schematic diagram of the GHES table provided by the embodiment of the present application;

Figure 6 is a schematic structural diagram of a computing device provided by an embodiment of the present application;

FIG. 7 is another schematic structural diagram of a computing device provided by an embodiment of the present application.

Detailed ways

Embodiments of the present application provide a method for handling memory faults and related equipment, which are applied in the storage field. This method of handling memory faults can accurately locate the precise location of the memory fault without removing the mirror mode of the memory.

The terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the terms so used are interchangeable under appropriate circumstances, and are merely a way of distinguishing objects with the same attributes in describing the embodiments of the present application. Furthermore, the terms "include" and "having" and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, system, product or apparatus comprising a series of elements need not be limited to those elements, but may include not explicitly other elements specifically listed or inherent to such processes, methods, products or equipment.

The embodiments of this application involve a lot of relevant knowledge about the memory mirroring mode. In order to better understand the solutions of the embodiments of this application, the relevant terms and concepts that may be involved in the embodiments of this application are first introduced below.

Address space: Address space refers to the range of memory encoding (encoding addresses). The so-called encoding is to assign a number to each physical storage unit (one byte), usually called "addressing". The purpose of assigning a number to a storage unit is to facilitate finding it and completing the reading and writing of data. This is called "addressing" (so some people also call the address space an addressing space).

Memory mirroring mode: Set the memory spaces of two independent physical memory devices to back up each other. This backup relationship is called mirroring. The computing device will allocate exactly the same address space as the memory space for the two mirrored memories (for example, the address spaces corresponding to the two memories are both 4G), and connect one of the memories to the memory controller. The connected channel is the main channel, and the channel connected between a memory and the memory controller is a backup channel. Its working principle is to make two copies of the memory data when writing data, and write them into the memory space corresponding to the main channel and the backup channel respectively. In the memory space, when reading data, it is mainly read from the memory space corresponding to the main channel. When an error occurs in the memory space of the main channel, the computing device will read data from the memory space corresponding to the backup channel to ensure that the main channel Even if the corresponding memory space fails, the correct data stored in the memory space corresponding to the backup channel can still be obtained to ensure the continuous normal operation of the computing device.

Mirror scrub (mirror scrub): In the memory mirror mode, when reading data, if the memory controller cannot correct the erroneous data in the memory space corresponding to the main channel through its own error correction capability (that is, the memory corresponding to the main channel When a UCE failure occurs in the space), the memory controller will send a data read request to the backup channel. If the read is successful (no error is returned), the memory controller will pass the correct data to the data read module and then send the correct data to the backup channel. The data is written back to the main channel memory to try to correct the erroneous data in the main channel. After the write-back action is completed, the data written back to the main channel will be read again for verification. This action is called mirror scrub.

As shown in Figure 1, Figure 1 is a schematic diagram of the processing flow of the mirror scrub mechanism. When the processor core of the central processing unit (CPU) reads data, the memory controller of the CPU first reads data from the main channel. The corresponding memory device reads the first data. When the Rank (the manufacturer refers to a 64-bit memory set as a Rank) of the memory device corresponding to the main channel to store data fails, the first data obtained is incorrect after verification. At that time, the memory controller will re-read the first data from the memory device corresponding to the main channel. If the first data error is still obtained and cannot be corrected, the memory controller will read the correct second data from the memory device corresponding to the backup channel. , where the addresses of the second data and the first data are the same, and the correct second data is returned to the core to complete the reading. In addition, the correct second data is written back to the address of the first data in the memory device corresponding to the main channel. middle.

Hard failure UCE: After the computing device turns on the memory mirroring mode, the memory controller finds through mirror scrubbing during operation that the correct data is written back to the main channel through the backup channel and still fails to be verified and cannot be corrected. This fault is considered to be a memory fault. Hard failure class UCE.

Mirror failover: refers to the lifting of the mirroring relationship between memory channels configured in mirror mode. After the mirroring relationship is lifted, the memory controller will only use the memory of the backup channel and no longer use the memory of the main channel.

Page: In the operating system (OS), Page refers to a fixed-length continuous virtual memory block. It is the smallest data unit used for memory management in the operating system and will be mapped to a block of the same length. The size of a contiguous physical memory block is usually determined by the processor architecture. Pages in the OS generally have a uniform size, usually 4096 bytes.

Page soft isolation (soft Page offline): This function is to copy the contents of the Page to be isolated to other places (or directly delete the contents of this Page if not needed), and the original Page will be removed from the memory management system of the operating system. Removed and no longer used, this feature will not kill or otherwise affect any applications.

System management interruption (SMI): An interrupt triggered by hardware and processed by the basic input output system (BIOS). The hardware can be triggered by corresponding instructions. After triggering, the CPU will enter the system management mode (system management mode). management mode (SMM) mode. At this time, the OS-related execution process will be suspended and the SMI interrupt service program registered in the BIOS will be executed.

System control interruption (SCI): It is an interrupt triggered by the BIOS and then processed by the OS. It is usually triggered after the BIOS has processed the related SMI interrupt. After the SCI interrupt is triggered, it is triggered by the SCI interrupt service routine registered in the OS kernel. For processing, this interrupt is used for communication between BIOS and OS.

Before introducing the embodiments of the present application, a brief description will be given of the current processing method of hard failure UCE in the memory mirroring mode, so as to facilitate subsequent understanding of the embodiments of the present application.

Current computing devices experience memory hard failure UCE. At this time, the memory controller will mark this fault type as a mirror failover error and trigger an SMI interrupt. The BIOS responds to the SMI interrupt and executes the corresponding interrupt service routine to implement mirror failover. During the execution of the operation, after performing the mirror failover operation, the memory controller no longer accesses the memory of the main channel when performing read and write operations, and only uses the memory of the backup channel.

Among them, there is at least one physical memory of Rank (manufacturers call a 64-bit memory set a Rank) on one channel, and the capacity of a Rank's physical memory may reach about 16GB, and with the development of technology, this capacity It will continue to increase, and when a memory hard failure UCE occurs in a certain bit of a Rank, performing a mirrorfailover operation to release the mirror relationship will cause the remaining normal memories in the entire main channel to be unavailable except for the failed memory location. , thus increasing the scope of adverse effects of memory hard failure UCE, wasting memory resources, and greatly increasing the probability of the memory mirroring mode being released.

In order to solve the above problems, embodiments of the present application provide a method and related equipment for handling memory failures, which are applied in the storage field. After determining that the memory fault of the main channel is a hard failure UCE, obtain the fault address through the BIOS and set it as the address to be isolated, and perform the soft page offline operation on the address to be isolated through the OS to achieve accurate isolation of the fault address. It will have an impact on other memory addresses, and there is no need to cancel the mirror relationship. Therefore, the rest of the memory in the main channel except the fault address can still support reading and writing normally. This prevents the normal memory in the main channel from being unusable after the mirror relationship is cancelled, and improves the performance of the main channel. Memory usage probability.

First, as an example, to facilitate understanding of subsequent embodiments, the architecture of a computing device applying the method for handling memory faults provided by embodiments of the present application is briefly described. Please refer to Figure 2 for details. Figure 2 is an architectural schematic diagram of a computing device provided by an embodiment of the present application. The hardware of the computing device specifically includes:

At least one CPU, a first memory, a second memory and a memory controller, the first memory and the second memory are connected to the memory controller, and the memory controller is connected to the processor. Its memory controller can support memory mirroring mode and can support error detection and correction capabilities of memory data. The first memory is accessed through the first channel, the second memory is accessed through the second channel, and the first memory is accessed through the memory controller. The memory and the second memory are configured in a mirroring mode, that is, the first memory and the second memory are mirror memories of each other. And the BIOS and OS can be run on the CPU. The BIOS as a software can be stored in the CPU or in a memory independent of the CPU. In addition, the OS as a software can also be stored in the memory. The CPU can call the memory in the memory. BIOS initializes the configuration of the hardware device of the computing device and collects status information of some component modules through interrupt response during operation, such as information related to the failure of the first memory or second memory, and can communicate with the OS. Interaction, that is, the CPU can perform relevant operations based on relevant information from the BIOS by calling the OS.

It should be noted that the aforementioned Figure 2 is only used as an example for the embodiment of the present application and does not substantially limit the present application. It can be understood that in actual situations, the memory controller can be independent of the CPU as shown in Figure 2 A chip can also be integrated into the CPU, or integrated into the north bridge, or integrated into the south bridge. There is no specific limit here.

Exemplarily, the computing device specifically executes a method for handling a memory failure including: obtaining uncorrectable error information of the first memory, where the uncorrectable error information includes the fault address, and then obtaining the first target data corresponding to the fault address from the second memory. , and writes the first target data to the fault address of the first memory, where the first memory and the second memory are mirror memories of each other, and verifies the second target data located at the fault address of the first memory. The second target data After the fault address of the first memory is written into the first target data, the data in the fault address of the first memory. If the second target data is verified as fault data, the fault address of the first memory is marked as the address to be isolated. And perform page soft isolation operation on the address to be isolated.

In order to better understand the embodiments of the present application, the method for handling memory faults provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings. Persons of ordinary skill in the art know that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems. Please refer to Figure 3 for details. Figure 3 is a schematic flowchart of a method for handling a memory failure provided by an embodiment of the present application, which specifically includes:

301. Obtain the uncorrectable error information of the first memory.

The computing device obtains uncorrectable error information for the first memory, the uncorrectable error information including the fault address.

Illustratively, to facilitate understanding of the example of FIG. 3 , this application uses the aforementioned computing device of FIG. 2 as an example for description. When a UCE fault is sent in the first memory, the memory controller of the computing device obtains uncorrectable error information for the first memory, the uncorrectable error information including the fault address. Among them, the memory controller supports actions such as memory mirroring mode, memory data verification, error type identification, fault address recording, mirror scrub data writeback, and SMI interrupt triggering. For example, the memory controller reads the data and its check bit from the first memory. After reading the data, it will check the data to obtain a newly generated check bit. If the check bit is the same as the check bit in the first memory, If the read check bits are different, it is determined that the read data is incorrect, and the address storing the data in the first memory is determined to be the fault address.

Then, after obtaining the uncorrectable error information of the first memory, the computing device repairs the data in the fault address in the first memory. Specifically as shown in step 302:

302. Obtain the first target data corresponding to the fault address from the second memory, and write the first target data to the fault address of the first memory. The first memory and the second memory are mirror memories of each other.

For example, the CPU of the computing device configures the first memory and the second memory under the memory controller into mirroring mode by calling the BIOS, that is, the first memory and the second memory are mirror memories of each other. After the mirroring mode is turned on, the first memory and the second memory are configured as mirroring modes. The same data is stored at the same address in the second memory. The memory controller can write back the correct second data to the fault address of the first memory through the mirror scrub mechanism. Specifically, after obtaining the uncorrectable error information of the first memory, the memory controller can obtain the first target data corresponding to the fault address from the second memory, that is, the memory controller can obtain the first target data corresponding to the fault address from the second memory. The first target data and its corresponding check digit are obtained from the address, and the newly generated check digit obtained after verifying the first target data is the same as the obtained check digit, that is, the first target data is determined to be correct data. , and then write the first target data to the fault address in the first memory, and repair the data in the fault address of the first memory.

303. Verify the second target data located at the fault address of the first memory. If the second target data is verified to be fault data, mark the fault address of the first memory as the address to be isolated.

After the memory controller writes the first target data obtained from the second memory to the fault address of the first memory, it will re-obtain the data, that is, the second target data (specifically, the second target data) from the fault address of the first memory. The target data may be the same as the first target data or may be different from the first target data), and the check code of the second target data is also obtained. Then the memory controller verifies the second target data. If the new target data is obtained If the generated check code is the same as the check code obtained from the first memory, it proves that the second target data is the same as the first target data, that is, the data in the fault address of the first memory has been restored to the correct data; if The newly generated check code is different from the check code obtained from the first memory, which proves that the second target data is different from the first target data, that is, the second target data is fault data, and the first target data can be considered A hard failure UCE fault occurs at the faulty address of the memory. At this time, the second target data is verified to be faulty data, and the faulty address of the first memory is marked as the address to be isolated.

In a possible implementation, the computing device marks the fault address of the first memory as the address to be isolated based on the identification to be isolated. For example, the identification to be isolated can be characters, numbers, strings, words, word combinations, etc., and there is no specific limitation here.

In the embodiment of the present application, multiple methods are used to realize that the to-be-isolated identification marks the fault address of the first memory as the to-be-isolated address, which reflects the diversity and selectivity of the solution.

In a possible implementation, the computing device generates a general hardware error source (GHES) table, which includes a fault address and a corresponding identification to be isolated.

Optionally, the fault level of the fault address in the GHES table is correctable. For example, the fault level of the fault address is set to corrected in the GHES table, which means that the fault level is correctable (since the correct first address can still be obtained from the second memory through the backup channel, that is, the second channel) Target data, so the fault at this fault address is correctable for the computing device), which reflects that the fault at this fault address will not have a negative impact on the operation of the computing device.

And the computing device performs a page soft isolation operation on the address to be isolated. Step 304 is as follows:

304. Perform page soft isolation operation on the address to be isolated.

Specifically, the computing device performs a soft page offline operation on the address to be isolated. The address to be isolated will be deleted from the memory management system of the operating system and no longer used. This achieves soft isolation of the faulty address. Therefore, there is no need to release the first memory and the third memory. The mirroring relationship between the two memories will not delete or otherwise affect the use of the memory space in the first memory except the address to be isolated.

In one possible implementation manner, the computing device calls the OS to perform a page soft isolation operation on the fault address in the GHES table whose fault level is correctable and whose fault level is to be isolated and corresponding to the identification to be isolated. In the implementation manner of this application, the specific implementation manner of the solution is reflected, and the reliability of the solution is reflected.

In an embodiment of the present application, the uncorrectable error information of the first memory is obtained, the uncorrectable error information includes the fault address, and then the first target data corresponding to the fault address is obtained from the second memory, and the first target data is Write the fault address of the first memory, where the first memory and the second memory are mirror memories of each other, and verify the second target data located at the fault address of the first memory, if the second target data is verified to be fault data , mark the fault address of the first memory as the address to be isolated, and perform a page soft isolation operation on the address to be isolated. In this way, the faulty address can be accurately isolated without affecting other memory addresses. There is no need to cancel the mirror relationship between the first memory and the second memory. Therefore, the remaining memory space in the first memory except the faulty address remains. It can support reading and writing normally, preventing the normal memory space in the first memory from being unusable after the mirroring relationship is released, improving the usage probability of the first memory, reducing the scope of adverse effects of memory hard failure UCE, avoiding wasting memory resources, and to a large extent Reduces the probability of memory mirroring mode being released.

Illustratively, in order to better understand the embodiment shown in Figure 3, a specific application scenario of the computing device in Figure 2 will be described below as an example. Specifically refer to FIG. 4 , which is a schematic diagram of determining a hard failure type UCE provided by an embodiment of the present application.

Among them, the computing device configures the memory connected to the memory controller into mirroring mode through the BIOS. For example, in Figure 2, the first memory is set to the memory space under the first channel, and the second memory is set to the memory space under the second channel. You can use the first channel as the main channel and the second channel as the backup channel.

When its memory controller writes data for storage, it writes the same data to the first memory and the second memory in mirror mode simultaneously through the first channel and the second channel to achieve backup of memory data. When the memory controller reads the data in the memory, it will read the data from the first memory through the first channel, and the memory controller will verify the read data every time it reads, specifically. , when the memory controller reads data, it will also read the check code corresponding to the data from the first memory, and generate a new check code based on the read data. If the newly generated check code is consistent with the read check code, If the check code is the same, the data is considered to be correct data, without errors and faults, and is sent to the processor; if the newly generated check code of the acquired data is inconsistent with the read check code, it is determined that the read A data sending failure means that a UCE error is detected in the first memory, and the memory controller cannot correct the faulty data, and the memory controller determines that the address where the faulty data is stored in the first memory is the fault address, and obtains the first memory. The memory contains uncorrectable error information for the faulty address. At this time, the memory controller reads the corresponding correct backup data, that is, the first target data, from the address that is the same as the fault address in the second memory through the second channel through the mirror scrub mechanism, and writes back the first target data to the first target data. In the fault address of the memory, the memory controller then obtains the second target data written back in the first memory from the first channel and verifies it. The specific verification is similar to the above, and will not be described again here. If after verification, the second target data is correct data, the fault that just occurred can be marked as mirror corrected, which means that the fault is marked as a correctable fault. If the second target data is still faulty data after verification, the fault can be marked as a mirror failover error, which indicates that the fault is a hard failure UCE.

Optionally, hard failure UCE or correctable faults can also be identified through other numbers, characters, strings, Chinese characters, words, combinations of words, or combinations of numbers and characters, etc. In actual situations, it can also be other Formal identification, specific details are not limited here.

And the memory controller triggers the SMI interrupt, and the CPU executes the SMI interrupt service program in the BIOS. For example, as shown in Figure 4, after the memory controller triggers the SMI interrupt, it enters the SMM mode. At this time, the CPU executes the SMI interrupt service routine in the BIOS to obtain the fault address marked as mirror failover error, and sets it to be isolated. address.

In one possible implementation, the CPU sets a corresponding identifier for the fault address through the BIOS. The identifier is used to indicate that the fault address needs to be isolated, thereby indicating that the fault address is an address to be isolated.

Optionally, the CPU generates a GHES table through the BIOS. The GHES table may include the fault address and an identifier indicating that the fault address is to be isolated. For example, in Figure 4, a corresponding GHES table is generated for the fault address through the SMI interrupt service routine, and the fault level of the fault address is set to corrected in the GHES table. Corrected indicates that the fault level is correctable. (Since the correct first target data can still be obtained from the second memory through the backup channel, that is, the second channel, the failure of this fault address is correctable for the computing device), and the corresponding flag (flag) Marked as error threshold exceeded, error threshold exceeded is used as an indicator to indicate that the faulty address is in the isolation state.

Please refer to Figure 5 for details. Figure 5 is a schematic diagram of the GHES table provided by the embodiment of the present application. The fault addresses include addresses 0xa2 and 0x3b. The fault levels are both corrected. The corresponding flags, i.e., flags, are all errorthreshold exceeded, which means that the address 0xa2 and 0x3b are addresses to be isolated. Optionally, the flag can also be soft Page offline, indicating the need to perform a soft Page offline operation on the fault address, that is, identifying the fault address as an address to be isolated, or it can also be other numbers, characters, strings, Chinese characters, words, A combination of words or a combination of numbers and characters, etc., indicates that the fault address is in a state of isolation. In actual situations, it can also be identified in other forms, and the specifics are not limited here.

In the embodiment of the present application, the fault address is set as the address to be isolated by generating a GHES table, so that the subsequent OS can obtain the address to be isolated, which reduces data transmission between the BIOS and the OS and improves work efficiency.

In addition, it is understandable that other implementation methods are used to set a corresponding identification for the fault address and identify it as an address to be isolated. For example, a register is defined to indicate the status of the error address, and one of the bit positions in the register 1 indicates that the fault address is the address to be isolated, or corresponding flags are set in other tables to indicate that the fault address is the address to be isolated. In actual situations, this can also be achieved in other ways, and there are no restrictions here.

Then run the SMI interrupt service program of the BIOS to report an SCI interrupt to the OS, thereby triggering the CPU to execute the relevant SCI interrupt service program in the OS to obtain the address to be isolated, and perform the soft page offline operation on the address to be isolated. For example, in Figure 4, after the GHES table is generated, the SCI interrupt is triggered, and then the CPU runs the SCI interrupt service program in the OS to obtain the fault address with the flag error threshold exceeded from the GHES table, that is, the address to be isolated, and then performs the softPage offline operation. , in this way, the fault address is softly isolated, and memory reading and writing are no longer supported.

Or, in a possible implementation, the CPU runs the BIOS to send a message carrying the address to be isolated to the OS, so that the OS obtains the address to be isolated from the message carrying the address to be isolated and performs a soft Pageoffline operation on the address to be isolated. Optionally, the message can carry the address to be quarantined and the corresponding identifier, which are not limited here. In the implementation of this application, the address to be isolated is obtained through a message sent by the BIOS carrying the address to be isolated, which increases the implementation and application scenarios and improves the flexibility of the solution.

In the embodiment of this application, the fault address of the hard failure UCE is set through the BIOS to the address to be isolated that needs to perform a soft isolation operation, and then the fault address is accurately isolated through the soft page offline operation of the OS, completely eliminating the impact of the fault, and There is no need to perform a mirror failover operation to release the mirror mode of the memory, which will not affect other memory addresses. There is no need to release the mirror relationship between the first memory and the second memory, so that the remaining memory space in the first memory except the fault address is It can still support reading and writing normally, preventing the normal memory space in the first memory from being unusable after the mirroring relationship is released, improving the usage probability of the first memory, reducing the scope of adverse effects of memory hard failure UCE, and avoiding the waste of memory resources, which is very large. This greatly reduces the probability of the memory mirroring mode being released.

It should be noted that the aforementioned Figure 4 is only used as an example to understand the embodiments of the present application, and does not substantially limit this solution. It is understandable that this solution can also be implemented in other ways, and is not specifically limited here.

The above is a detailed introduction to the method of detecting memory faults provided by the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the detection of the present application. Memory failure methods and their core ideas. At the same time, for those of ordinary skill in the art, there will be changes in the specific implementation and application scope based on the ideas of the present application. In summary, the content of this description should not be understood as a limitation of the present application.

As shown in Figure 6, an embodiment of the present application also provides a computing device, which is applied in the storage field. Please refer to FIG. 6 for details. FIG. 6 is a schematic structural diagram of a computing device provided by an embodiment of the present application. In a possible implementation, the computing device may include modules or units that perform one-to-one correspondence with the methods/operations/steps/actions in Figure 3 in the above method embodiment. The unit may be a hardware circuit, software, or It is a combination of hardware circuit and software implementation. In a possible implementation, the computing device may include: a processor 601, a memory controller 602, a first memory 603 and a second memory 604. Among them, the first memory 603 and the second memory 604 are connected to the memory controller 602, the memory controller 602 is connected to the processor 601, and the first memory 603 and the second memory 604 are mirror memories of each other. The memory controller 602 may be used to perform the above method embodiment to obtain the uncorrectable error information of the first memory 603, where the uncorrectable error information includes the fault address, and obtain the first target corresponding to the fault address from the second memory 604. data, and the steps of writing the first target data to the fault address of the first memory 603, and verifying the second target data located at the fault address of the first memory 603, the processor 601 can be used to perform the steps as in the above method embodiment. If the second target data is fault data, mark the fault address of the first memory 603 as the address to be isolated, and perform the page soft isolation operation step on the address to be isolated.

In other possible designs, the above-mentioned processor 601 and the memory controller 602 can execute the methods/operations/steps/actions in various possible implementations of the energy storage device in the above method embodiment in one-to-one correspondence.

In one possible design, the above-mentioned processor 601 is specifically configured to mark the fault address of the first memory 603 as the address to be isolated based on the identification to be isolated.

In one possible design, the above-mentioned processor 601 is specifically configured to perform a page soft isolation operation on the address to be isolated through the OS.

In one possible design, the above-mentioned processor 601 is specifically configured to generate a GHES table, which includes the fault address and the corresponding identification to be isolated.

In one possible design, the fault level of the fault address in the above GHES table is correctable.

In one possible design, the above-mentioned processor 601 is specifically configured to perform a page soft isolation operation through the OS on fault addresses in the GHES table whose fault level is correctable and corresponding to the identification to be isolated.

For the beneficial effects of the computing devices of various designs mentioned above in this application, please refer to the beneficial effects of the various implementation methods corresponding to each other in the method embodiments in FIG. 3 and FIG. 4, which will not be described again here.

It should be noted that the information interaction, execution process, etc. between the modules/units in the computing device corresponding to the embodiment in Figure 6 are based on the same concept as the method embodiment corresponding to Figure 3 in this application. For specific content, please refer to this application. The descriptions in the method embodiments shown above will not be repeated here.

In addition, each functional module or unit in various embodiments of the present application can be integrated in a processor, and the above integrated modules or units can be implemented in the form of hardware or software function modules.

Next, a computing device provided by an embodiment of the present application is introduced. Please refer to FIG. 7 . FIG. 7 is another schematic structural diagram of a computing device provided by an embodiment of the present application. The computing device may be, for example, a server, a computer, or other electronic device. Specifically, the computing device 700 includes a CPU 701 and at least one memory 702, where the memory 702 may be a short-term storage or a persistent storage. The program stored in the memory 702 may include one or more modules (not shown in the figure), such as BIOS and/or OS application programs stored in the memory 702 , and each module may include a series of instruction operations on the computing device 700 . Furthermore, the CPU 701 may be configured to communicate with the memory 702 and execute a series of instruction operations in the memory 702 on the computing device 700 .

In the embodiment of the present application, the CPU 701 is used to execute the method in the corresponding embodiment of Figure 3. For example, the CPU 701 can be used to: obtain the uncorrectable error information of the first memory, where the uncorrectable error information includes the fault address, and then obtain the first target data corresponding to the fault address from the second memory, and write the first target data Enter the fault address of the first memory, where the first memory and the second memory are mirror memories of each other, and verify the second target data located at the fault address of the first memory. The second target data is the fault address of the first memory. After writing the first target data, if the data in the fault address of the first memory is verified as fault data, mark the fault address of the first memory as the address to be isolated, and perform page soft isolation on the address to be isolated. operate. In this way, the fault address can be accurately isolated, the impact of the fault can be completely eliminated, and there is no need to perform a mirror failover operation to release the mirror mode of the first memory and the second memory, so that the remaining memory space in the first memory except the fault address can still be used. Normally supports reading and writing, preventing the normal memory space in the first memory from being unusable after the mirroring relationship is released, increasing the usage probability of the first memory, reducing the scope of adverse effects of memory hard failure UCE, avoiding wasting memory resources, and greatly reducing the The probability of the memory mirroring mode being released.

Embodiments of the present application also provide a computer-readable storage medium, which includes computer-readable instructions. When the computer-readable instructions are run on a computer, they cause the computer to execute any of the implementations shown in the foregoing method embodiments.

Embodiments of the present application also provide a computer program product. The computer program product includes a computer program or instructions. When the computer program or instructions are run on a computer, it causes the computer to execute any of the implementation methods shown in the foregoing method embodiments.

This application also provides a chip or chip system, and the chip may include a processor. The chip may also include a memory (or storage module) and/or a transceiver (or communication module), or the chip may be coupled with a memory (or storage module) and/or a transceiver (or communication module), where the transceiver ( or communication module) can be used to support the chip to perform wired and/or wireless communications. The memory (or storage module) can be used to store a program or a set of instructions. The processor can call the program or the set of instructions to implement the above method embodiments. Operations performed by the terminal or network device in any possible implementation of the method embodiment. The chip system may include the above chip, or may include the above chip and other separate devices, such as a memory (or storage module) and/or a transceiver (or communication module).

In addition, it should be noted that the device embodiments described above are only illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. , that is, it can be located in one place, or it can be distributed across multiple units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the drawings of the device embodiments provided in this application, the connection relationship between modules indicates that there are communication connections between them, which can be specifically implemented as one or more communication buses or signal lines.

Through the above description of the embodiments, those skilled in the art can clearly understand that the present application can be implemented by software plus necessary general hardware. Of course, it can also be implemented by dedicated hardware including dedicated integrated circuits, dedicated CPUs, dedicated memories, Special components, etc. to achieve. In general, all functions performed by computer programs can be easily implemented with corresponding hardware. Moreover, the specific hardware structures used to implement the same function can also be diverse, such as analog circuits, digital circuits or special-purpose circuits. circuit etc. However, for this application, software program implementation is a better implementation in most cases. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product in essence or that contributes to the existing technology. The computer software product is stored in a readable storage medium, such as a computer floppy disk. , U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc., including several instructions to make a computer device (which can be a personal computer, training equipment, or network equipment, etc.) to execute the methods of various embodiments of this application.

Claims (10)

1. A method for handling a memory failure, comprising:

obtaining uncorrectable error information of a first memory, wherein the uncorrectable error information comprises a fault address;

acquiring first target data corresponding to the fault address from a second memory, and writing the first target data into the fault address of the first memory, wherein the first memory and the second memory are mirror memories;

checking second target data of the fault address of the first memory, and marking the fault address of the first memory as an address to be isolated if the second target data is checked to be the fault data;

and executing page soft isolation operation on the address to be isolated.

2. The method of claim 1, wherein the marking the failed address of the first memory as an address to be isolated comprises:

and marking the fault address of the first memory as the address to be isolated based on the identification to be isolated.

3. The method of claim 1 or 2, wherein performing a page soft isolation operation on the address to be isolated comprises:

and executing the page soft isolation operation on the address to be isolated through an operating system OS.

4. The method of claim 3, wherein marking the failed address of the first memory as the address to be isolated based on an identification to be isolated comprises:

and generating a general hardware error source GHES table, wherein the GHES table comprises the fault address and the corresponding identification to be isolated.

5. The method of claim 4, wherein the failure level of the failed address in the GHES table is correctable.

6. The method of claim 5, wherein performing a page soft isolate operation on the address to be isolated comprises:

and executing the page soft isolation operation on the fault address corresponding to the fault level correctable and the identification to be isolated in the GHES table through the OS.

7. The computing device is characterized by comprising a processor, a first memory, a second memory and a memory controller, wherein the first memory and the second memory are connected with the memory controller, the memory controller is connected with the processor, and the first memory and the second memory are mirror images;

the memory controller is configured to obtain uncorrectable error information of the first memory, where the uncorrectable error information includes a failure address;

The memory controller is further configured to obtain first target data corresponding to the failure address from the second memory, and write the first target data into the failure address of the first memory;

the memory controller is further configured to verify second target data located at the failure address of the first memory;

the processor is configured to mark the failure address of the first memory as an address to be isolated if the second target data is verified to be failure data;

and the processor is also used for executing page soft isolation operation on the address to be isolated.

8. The computing device of claim 7, wherein the processor is specifically configured to tag the failed address of the first memory as the address to be isolated based on an identification to be isolated.

9. The computing device of claim 8, wherein the processor is configured to generate a generic hardware error source GHES table, wherein the GHES table includes the failure address and the corresponding identification to be isolated.

10. The computing device of claim 9, wherein the processor is specifically configured to perform, by the OS, the page soft isolation operation on the failed address corresponding to the identity to be isolated and the failure level in the GHES table being correctable.