CN117666688A - Linear voltage stabilizer with wide power supply range - Google Patents

Abstract

The invention relates to a technical improvement of an analog integrated circuit, in particular to a linear voltage stabilizer with a wide power supply range, which aims to solve the problem of narrow power supply range of a traditional LDO circuit and widen the application of the linear voltage stabilizer circuit in a wide power supply voltage system. The circuit is applicable to low-voltage and high-voltage application systems and comprises a pre-voltage stabilizing circuit (100), a low-voltage control circuit (200) and a voltage stabilizer main body circuit (300); the low-voltage control circuit (200) comprises a power supply sampling module (201) and a power supply comparison module (202); the voltage stabilizer main body circuit (300) consists of an error amplifying module (301), a buffer module (302) and a power output stage (303); the error amplifier and the comparator are powered by the pre-stabilizing circuit, and when the power supply voltage is changed in a wide range, the performance of the error amplifier is not changed greatly. Meanwhile, the two modules can be designed by using normal pressure pipes, so that the number of high-voltage devices is greatly reduced, the area of a chip is reduced, and the cost is reduced.

Description

Linear voltage stabilizer with wide power supply range

Technical Field

The invention relates to a technical improvement of an analog integrated circuit, in particular to a linear voltage stabilizer with a wide power supply range.

Background

The low dropout linear regulator (LDO, low dropout regulator) has the advantages of low cost, low power consumption, simple peripheral circuits and the like, and plays a vital role in a power management system. LDOs are commonly used in battery-powered devices and portable electronic products, where the operating voltage is low, typically around 5V.

With the rapid development of electronic industries such as new energy automobiles, the power supply voltage range of the power supply management chip is wider, which limits the application of the LDO. Under the high-voltage application scene, a switching power supply (DC-DC) is generally adopted as a power supply chip, and compared with LDO, the switching power supply has the defects of large noise and large output ripple, and cannot be used in some high-precision equipment. As shown in FIG. 1, the conventional LDO circuit generates feedback signals by dividing output voltages by resistors R1 and R2; the error amplifier amplifies the difference between the feedback signal VFB and the reference voltage VREF generated by the reference circuit to control the gate of the PMOS driving transistor PM1, thereby forming a negative feedback loop and generating a stable output voltage VOUT.

The LDO circuit in fig. 1 includes an error amplifier AMP, a PMOS drive transistor PM1, and resistors R1, R2. The error amplifier AMP is used for amplifying the difference value between the feedback voltage VFB and the reference voltage VREF, and outputting a signal to control the grid electrode of the PMOS tube PM 1; PM1 changes the current flowing through PM1 according to the change of the grid voltage, and adjusts the output voltage VOUT; the resistors R1 and R2 act as voltage divider to generate the feedback voltage signal VFB at the positive input of the error amplifier.

When the LDO circuit works and the load current increases, the output voltage VOUT decreasesVFB also decreases, the feedback voltage VFB is smaller than the reference voltage VREF, the output voltage of the error amplifier AMP decreases, the gate-source voltage VGS of the PMOS tube PM1 increases, the current flowing through the PM1 tube increases, and the output voltage VOUT increases. When the output voltage VOUT increases, VFB will also increase, the feedback voltage VFB is greater than the reference voltage VREF, the output voltage of the error amplifier AMP increases, the gate-source voltage VGS of the PMOS tube PM1 decreases, and the current flowing through the PM1 tube decreases, so that the output voltage is increasedThe output voltage VOUT drops. Based on the above negative feedback relationship, when the LDO stabilizes the output voltage VOUT, vfb=vref, i.e.>

In the LDO circuit described above, the input power supply voltage VCC is not high, and generally does not exceed 5V. When the high-voltage power supply is applied in a high-power-supply voltage scene, most circuits including an error amplifier need to be designed by adopting a high-voltage tube if the high-power supply is directly used for supplying power. This greatly increases the area due to the larger area of the high pressure tube, resulting in increased chip cost. If low-voltage application is required, various indexes of the error amplifier are difficult to meet the requirements in a very wide power supply range, and various indexes of the LDO are affected.

Disclosure of Invention

The invention aims to provide a linear voltage stabilizer with a wide power supply range, so as to solve the problem of narrow power supply range of the traditional LDO circuit, and widen the application of the linear voltage stabilizer circuit in a wide power supply voltage system.

In order to achieve the above purpose, the present invention provides the following technical solutions: a linear voltage stabilizer with wide power supply range comprises a pre-voltage stabilizing circuit, a low-voltage control circuit and a voltage stabilizer main body circuit; the low-voltage control circuit comprises a power supply sampling module and a power supply comparison module; the voltage stabilizer main body circuit consists of an error amplifying module, a buffer module and a power output stage;

the pre-voltage stabilizing circuit is used for stabilizing the wide-range input power supply voltage VDDH and outputting a voltage VDDL not higher than 5.5V; when the power supply voltage is less than 5.5V, the output voltage VDDL follows the power supply voltage variation, namely vddl=vddh, and when the power supply voltage is higher than or equal to 5.5V, the output voltage vddl=5.5V;

the low-voltage control circuit comprises a power supply sampling module and a power supply comparison module, wherein the power supply of the power supply sampling module is input power supply voltage VDDH, and the power supply of the power supply comparison module is output voltage VDDL of the pre-voltage stabilizing circuit; the power supply sampling module samples an input power supply voltage VDDH, and the sampled voltage is compared with a reference voltage by the power supply comparison module; when the VDDH voltage is higher than the theoretical output voltage of the voltage stabilizer, the controlled switching tube is disconnected; when the VDDH voltage is lower than the theoretical output voltage of the voltage regulator, the power tube of the main body circuit of the voltage regulator is controlled through the switching tube, so that the output voltage of the voltage regulator changes along with the input power supply voltage, namely VOUT=VDDH;

the voltage regulator main body circuit consists of an error amplifying module, a buffer module and a power output stage, wherein the error amplifying module is powered by the output voltage VDDL of the pre-voltage regulator circuit, and the buffer module and the power output stage are powered by VDDH; the voltage stabilizer main body circuit converts an input power supply voltage into a stable power supply output;

the pre-voltage stabilizing circuit comprises a first current mirror formed by a resistor R1, a resistor R2 and a resistor R3, a first current mirror formed by a normal-pressure NMOS tube NM0 and a normal-pressure NMOS tube NM1, a second current mirror formed by a high-voltage PLDMOS tube PMH0 and a high-voltage PLDMOS tube PMH1, a high-voltage PLDMOS driving tube PMH2, a voltage stabilizing diode Z1 and a voltage stabilizing diode Z2, a high-voltage NLDMOS tube NMH0 and a high-voltage NLDMOS tube NMH1 and an output voltage stabilizing capacitor C; one end of the resistor R1 is connected with the power supply VDDH, and the other end of the resistor R1 is intersected with the negative end of the voltage stabilizing diode Z1, the gate ends of the high-voltage NLDMOS tube NMH0 and the high-voltage NLDMOS tube NMH1 in VGN; the positive end of the voltage stabilizing diode Z1 is connected with the gate end and the drain end of the normal-pressure NMOS tube NM0 and the gate end of the normal-pressure NMOS tube NM1, and the source ends of the normal-pressure NMOS tube NM0 and the normal-pressure NMOS tube NM1 are grounded; the drain end of the normal-pressure NMOS tube NM1 is connected with the source end of the high-pressure NLDMOS tube NMH 0; the drain end of the high-voltage NLDMOS tube NMH0 is connected with the gate end and the drain end of the high-voltage PLDMOS tube PMH0 and the gate end of the high-voltage PLDMOS tube PMH 1; the source ends of the high-voltage PLDMOS tube PMH0 and the high-voltage PLDMOS tube PMH1 are connected with a power supply VDDH; the drain end of the high-voltage PLDMOS tube PMH1, one end of the resistor R2, the positive end of the zener diode Z2 and the gate end of the high-voltage PLDMOS tube PMH2 are intersected at VGP; the other end of the resistor R2 is grounded; the negative end of the zener diode Z2, the source end of the high-voltage PLDMOS tube PMH2 and the drain end of the high-voltage NLDMOS tube NMH1 are connected with a power supply VDDH; the drain end of the high-voltage PLDMOS tube PMH2, the source end of the high-voltage NLDMOS tube NMH1 and one end of the resistor R3 and the capacitor C are intersected at the output VDDL of the voltage stabilizing circuit, and the other ends of the resistor R3 and the capacitor C are grounded;

the power supply sampling module consists of a resistor R7 and a resistor R8, and the power supply comparison module consists of a comparator COMP and a high-voltage NLDMOS tube NMH 4; one end of the resistor R7 is connected with the power supply VDDH, the other end of the resistor R7 is connected with one end of the resistor R8 and is connected to the negative input end of the comparator COMP, and the other end of the resistor R8 is grounded; the power supply of the comparator COMP is the output VDDL of the pre-voltage stabilizing circuit, the positive input end is connected with the reference voltage VREF2, and the output end is connected with the gate end of the high-voltage NLDMOS tube NMH 4; the source end of the high-voltage NLDMOS tube NMH4 is grounded, and the drain end of the high-voltage NLDMOS tube NMH4 is connected with the gate end of the driving tube PMH4 in the power output stage.

The error amplifying module comprises an error amplifier AMP, a normal-pressure NMOS tube NM2 and a constant current source I1; the power end of the error amplifier AMP and the drain end of the normal-pressure NMOS tube NM2 are connected with the output VDDL of the pre-voltage stabilizing circuit; the negative input end of the error amplifier AMP is connected with the reference voltage VREF1, the positive input end of the error amplifier AMP is connected with the feedback voltage VFB, and the output end of the error amplifier AMP is connected with the gate end of the normal-pressure NMOS tube NM 2; the source end of the normal-pressure NMOS tube NM2 is connected with a constant current source I1, and the other end of the constant current source I1 is connected with GND;

the buffer module comprises a high-voltage NLDMOS tube NMH2, a high-voltage NLDMOS tube NMH3, a high-voltage PLDMOS tube PMH4, a resistor R5 and a resistor R6, a zener diode Z3, a constant current source I2 and a constant current source I3; the gate end of the high-voltage NLDMOS tube NMH2 is connected with the bias voltage VB, the source end of the high-voltage NLDMOS tube NMH2 is connected with the source end of the normal-voltage NMOS tube NM2, and the drain end of the high-voltage NLDMOS tube NMH3 is connected with one end of the resistor R4; the other end of the resistor R4, the drain end of the high-voltage NLDMOS tube NMH3, the negative end of the zener diode Z3 and one end of the constant current source I3 are connected to a power supply VDDH; the source end of the high-voltage NLDMOS tube NMH3 is connected with one end of the constant current source I2, the positive end of the zener diode Z3 and the gate end of the high-voltage PLDMOS tube PMH 3; the other end of the constant current source I2 and the drain end of the high-voltage PLDMOS tube PMH3 are grounded; the source end of the high-voltage PLDMOS tube PMH3 is connected with the other end of the constant current source I3;

the power output stage comprises a voltage stabilizing diode Z4, an output high-voltage PLDMOS power tube PMH4, a resistor R5 and a resistor R6; the negative end of the voltage stabilizing diode Z4 and the source end of the output high-voltage PLDMOS power tube PMH4 are connected with a power supply VDDH, and the positive end of the voltage stabilizing diode Z4 and the gate end of the output high-voltage PLDMOS power tube PMH4 are connected with the source end of the high-voltage PLDMOS power tube PMH 3; the drain end of the output high-voltage PLDMOS power tube PMH4 and one end of the resistor R5 are connected with the output end VOUT of the linear voltage stabilizer; the other end of the resistor R5 and one end of the resistor R6 are connected to the VFB and to the positive input end of the error amplifier AMP; the other end of the resistor R6 is grounded.

Preferably, the voltage stabilizing values of the zener diode Z1, the zener diode Z2, the zener diode Z3, and the zener diode Z4 are 5.5V.

Preferably, the high-voltage NLDMOS tube and the high-voltage PLDMOS tube are thin gate oxide devices, and the gate-source voltage withstand voltage is about 5.5V.

The linear voltage stabilizer with wide power supply range has the following advantages:

the linear voltage stabilizer with wide power supply range supplies power to the error amplifier and the comparator through the pre-voltage stabilizing circuit, and the performance of the error amplifier is not greatly changed when the power supply voltage is changed within a wide range. Meanwhile, the two modules can be designed by using normal pressure pipes, so that the number of high-voltage devices is greatly reduced, the area of a chip is reduced, and the cost is reduced.

The linear voltage stabilizer with wide power supply range can stably output LDO in a high power supply voltage scene; when the power supply voltage is low, the output driving tube is controlled by the low-voltage control circuit, so that the output voltage accurately follows the power supply change, the power supply voltage regulator has good performance in a wide power supply range, and the application of the linear voltage regulator circuit in a system with a wide power supply voltage range is widened.

Drawings

FIG. 1 is a conventional LDO circuit structure of the prior art;

FIG. 2 is a block diagram of a wide power range linear voltage regulator of the present invention;

FIG. 3 is a schematic diagram of a wide power range linear voltage regulator of the present invention;

FIG. 4 is a schematic diagram of a partial amplification of a wide power range linear regulator according to the present invention;

FIG. 5 is a schematic diagram showing a second partial amplification of the wide power range linear regulator of the present invention;

FIG. 6 is a schematic diagram of a linear voltage regulator with wide power range according to the present invention.

Reference numerals: 100. a pre-voltage stabilizing circuit; 101. a first current mirror; 102. a second current mirror; 200. a low voltage control circuit; 201. a power supply sampling module; 202. a power supply comparison module; 300. a voltage regulator main body circuit; 301. an error amplifying module; 302. a buffer module; 303. a power output stage.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

As shown in fig. 2, the wide power range linear voltage regulator of the present invention includes a pre-voltage regulator circuit 100, a low voltage control circuit 200, and a regulator main body circuit 300; wherein the low voltage control circuit 200 comprises a power supply sampling module 201 and a power supply comparing module 201; the regulator body circuit 300 is composed of an error amplifying module 301, a buffer module 302 and a power output stage 303.

The pre-voltage stabilizing circuit 100 stabilizes the wide-range input power supply voltage VDDH and outputs a voltage VDDL not higher than 5.5V; when the power supply voltage is low (< 5.5V), the output voltage VDDL follows the power supply voltage variation, i.e., vddl=vddh; when the power supply voltage is high (. Gtoreq.5.5V), the output voltage VDDL=5.5V.

The low voltage control circuit 200 includes a power sampling module 201 and a power comparing module 202, wherein the power of the power sampling module is an input power voltage VDDH, and the power of the power comparing module 202 is an output voltage VDDL of the pre-voltage stabilizing circuit 100; the power sampling module 201 samples the input power voltage VDDH, and the sampled voltage is compared with a reference voltage by the power comparing module 202; when the VDDH voltage is higher than the theoretical output voltage of the voltage stabilizer, the controlled switching tube is disconnected, so that the work of the main circuit of the voltage stabilizer is not influenced; when the VDDH voltage is lower than the theoretical output voltage of the voltage regulator, the power tube of the main circuit of the voltage regulator is controlled by the switching tube, so that the output voltage of the voltage regulator follows the input power supply voltage, i.e., vout=vddh.

The regulator body circuit 300 is composed of an error amplification block 301, a buffer block 302 and a power output stage 303, wherein the error amplification block 301 is powered by the output voltage VDDL of the pre-regulator circuit 100, and the buffer block 302 and the power output stage 303 are powered by VDDH. The module converts an input power supply voltage to a stable power supply output.

As shown in fig. 3 to 6, the pre-voltage stabilizing circuit 100 includes a first current mirror 101 formed by a resistor R1, a resistor R2, a resistor R3, a normal-voltage NMOS transistor NM0 and a normal-voltage NMOS transistor NM1, a second current mirror 102 formed by a high-voltage PLDMOS transistor PMH0 and a high-voltage PLDMOS transistor PMH1, a high-voltage PLDMOS driving transistor PMH2, two voltage stabilizing diodes Z1 and Z2 (voltage stabilizing value 5.5V), a high-voltage NLDMOS transistor NMH0 and a high-voltage NLDMOS transistor NMH1, and an output voltage stabilizing capacitor C. One end of the resistor R1 is connected with the power supply VDDH, and the other end of the resistor R1 is intersected with the negative end of the zener diode Z1, the gate ends of the high-voltage NLDMOS tube NMH0 and the high-voltage NLDMOS tube NMH1 at VGN. The positive terminal of the zener diode Z1 is connected to the gate terminal and the drain terminal of the normal-pressure NMOS transistor NM0 and the gate terminal of the normal-pressure NMOS transistor NM1, and the source terminals of the normal-pressure NMOS transistor NM0 and the normal-pressure NMOS transistor NM1 are grounded. The drain end of the normal-pressure NMOS tube NM1 is connected with the source end of the high-pressure NLDMOS tube NMH 0. The drain terminal of the high-voltage NLDMOS tube NMH0 is connected with the gate terminal and the drain terminal of the high-voltage PLDMOS tube PMH0 and the gate terminal of the high-voltage PLDMOS tube PMH 1. The source ends of the high-voltage PLDMOS tube PMH0 and the high-voltage PLDMOS tube PMH1 are connected with a power supply VDDH. The drain end of the high-voltage PLDMOS tube PMH1, one end of the resistor R2, the positive end of the zener diode Z2 and the gate end of the high-voltage PLDMOS driving tube PMH2 are intersected at VGP, the other end of the resistor R2 is grounded, and the negative end of the zener diode Z2, the source end of the high-voltage PLDMOS driving tube PMH2 and the drain end of the high-voltage NLDMOS tube NMH1 are connected with a power supply VDDH. The drain end of the high-voltage PLDMOS driving tube PMH2 and the source end of the high-voltage NLDMOS tube NMH1 are intersected with one ends of the resistor R3 and the capacitor C at the output VDDL of the voltage stabilizing circuit, and the other ends of the resistor R3 and the capacitor C are grounded.

The low-voltage control circuit 200 comprises a power supply sampling module 201 and a power supply comparing module 202; the power sampling module 201 is composed of a resistor R7 and a resistor R8, and the power comparing module 202 is composed of a comparator COMP and a high-voltage NLDMOS tube NMH 4. One end of the resistor R7 is connected with the power supply VDDH, the other end of the resistor R7 is connected with one end of the resistor R8 and is connected to the negative input end of the comparator, and the other end of the resistor R8 is grounded. The power supply of the comparator COMP is the output VDDL of the pre-voltage stabilizing circuit, the positive input end is connected with the reference voltage VREF2, the output end is connected with the gate end of the high-voltage NLDMOS tube NMH4, the source end of the high-voltage NLDMOS tube NMH4 is grounded, and the drain end is connected with the gate end of the driving tube PMH4 in the power output stage 303.

The regulator body circuit 300 is composed of an error amplification module 301, a buffer module 302, and a power output stage 303.

The error amplifying module 301 includes an error amplifier AMP, a normal-pressure NMOS tube NM2, and a constant current source I1; the power end of the error amplifier AMP and the drain end of the normal-pressure NMOS tube NM2 are connected with the output VDDL of the pre-voltage stabilizing circuit; the negative input end of the error amplifier AMP is connected with the reference voltage VREF1, the positive input end of the error amplifier AMP is connected with the feedback voltage VFB, and the output end of the error amplifier AMP is connected with the gate end of the normal-pressure NMOS tube NM 2. The source end of the normal-pressure NMOS tube NM2 is connected with a constant current source I1, and the other end of the constant current source I1 is connected with GND.

The buffer module 302 includes a high voltage NLDMOS transistor NMH2 and a high voltage NLDMOS transistor NMH3, a high voltage PLDMOS transistor PMH3 and a high voltage PLDMOS transistor PMH4, a resistor R5, a resistor R6, a zener diode Z3 (a zener value of 5.5V), and constant current sources I2, I3. The gate end of the high-voltage NLDMOS tube NMH2 is connected with the bias voltage VB, the source end of the high-voltage NLDMOS tube NMH2, and the drain end of the high-voltage NLDMOS tube NMH2 is connected with one end of the resistor R4 and the gate end of the high-voltage NLDMOS tube NMH 3. The other end of the resistor R4 is connected to the power supply VDDH with the drain of the high-voltage NLDMOS transistor NMH3, the negative end of the zener diode Z3, and one end of the constant current source I3. The source end of the high-voltage NLDMOS tube NMH3 is connected with one end of the constant current source I2, the positive end of the zener diode Z3 and the gate end of the high-voltage PLDMOS tube PMH 3; the other end of the constant current source I2 and the drain end of the high-voltage PLDMOS tube PMH3 are grounded, and the source end of the high-voltage PLDMOS tube PMH3 is connected with the other end of the constant current source I3.

The power output stage 303 includes a zener diode Z4 (with a regulated voltage of 5.5V), an output high voltage PLDMOS power tube PMH4, and a resistor R5, R6; the negative end of the voltage stabilizing diode Z4 and the source end of the output high-voltage PLDMOS power tube PMH4 are connected with a power supply VDDH, and the positive end of the voltage stabilizing diode Z4 and the gate end of the output high-voltage PLDMOS power tube PMH4 are connected with the source end of the high-voltage PLDMOS power tube PMH 3; the drain end of the output high-voltage PLDMOS power tube PMH4 and one end of the resistor R5 are connected with the output end VOUT of the linear voltage stabilizer; the other end of the resistor R5 and one end of the resistor R6 are connected to the VFB and to the positive input end of the error amplifier AMP; the other end of the resistor R6 is grounded.

The high-voltage NLDMOS tube and the high-voltage PLDMOS tube in the circuit are thin gate oxide devices, and the gate-source voltage withstand voltage is about 5.5V.

In implementation, as shown in fig. 3 and 4, the pre-voltage stabilizing circuit 100 detects the power supply voltage VDDH through the voltage stabilizing diode Z1; when the power supply voltage VDDH is lower than the regulated voltage Vz (5.5V) of the zener diode, no current flows through the zener diode Z1, and neither the current mirror 101 nor the current mirror 102 flows, so the gate voltage VGN of the N-type driving transistor NMH1 is connected to the power supply voltage VDDH through the resistor R1, and the gate voltage VGP of the P-type driving transistor PMH2 is connected to the ground through the resistor R2. At this time, the gate-source voltage difference of the P-type driving tube PMH2 is the power voltage VDDH, the P-type driving tube PMH2 is turned on, and the output voltage VDDL varies along with the power voltage VDDH, vddl=vddh. When the power supply voltage is higher than the regulated voltage of the zener diode Z1, a current flows through the zener diode Z1, and after the current is mirrored through the first current mirror 101 and the second current mirror 102, the current flows through the resistor R2, so that the VGP voltage increases. When the current is large enough, VGP voltage is close to the power supply voltage VDDH, and the P-type driving tube PMH2 is cut off; at this time, the gate voltage VGN of the N-type driving tube NMH1 is stabilized at Vz+V _GS,NM0 Almost no longer follows the VDDH change. The N-type driving transistor NMH1 is turned on, and the output voltage VOUT is equal to VGN minus the gate-source voltage difference of the N-type driving transistor NMH1, i.e., vout=vz+v _GS,NM0 -V _GS,NMH1 The output voltage is stabilized at about 5.5V. When the voltage stabilizing circuit is in low power supply voltage, the voltage stabilizing circuit is driven by the P-type driving tube, and the output voltage can be changed along with the power supply voltage; at a high power supply voltage, the output is stabilized at about 5.5V by the N-type driving tube, so that the operation can be performed in a wide power supply range. By adjusting the resistance of the resistor R1 and the resistor R2 and the mirror current ratio of the first current mirror 101 and the second current mirror 102, a proper switching point voltage can be obtained. The voltage stabilizing tube Z2 is used for protecting the high-voltage PLDMOS tube PMH2, and the gate-source voltage difference of the high-voltage PLDMOS tube PMH2 is ensured not to exceed the voltage-resistant value of the device. The high-voltage NLDMOS tube NMH0 is used for protecting the normal-pressure tube NM1, so that the drain voltage of the high-voltage NLDMOS tube NMH does not exceed the withstand voltage of the device.To reduce the quiescent current, the values of the resistors R1, R2 and R3 are generally large.

As shown in fig. 3 and 5, the error amplification block 300, the buffer block 301, and the power output stage 303 in the regulator body circuit 300 form a negative feedback loop; the zener diode Z3 and the zener diode Z4 are respectively used for protecting the high-voltage PLDMOS transistor PMH3 and the high-voltage PLDMOS transistor PMH4, so that the gate-source voltage difference of the high-voltage PLDMOS transistor PMH3 and the high-voltage PLDMOS transistor PMH4 cannot exceed the device voltage-withstanding value. The error amplifier AMP amplifies the difference value between the first reference voltage VREF1 and the feedback voltage VFB and outputs the difference value to the grid electrode of the normal-pressure NMOS tube NM 2; the normal-pressure NMOS tube NM2 and the constant current source I1 form a source following structure, when the grid voltage of the normal-pressure NMOS tube NM2 changes, the source voltage also changes, the voltage change is converted into a VDDH voltage domain through the high-voltage NLDMOS tube NMH2 and the resistor R4, and meanwhile, the high-voltage NLDMOS tube NMH2 also protects the normal-pressure tube generating the constant current source I1, so that the drain-source voltage does not exceed the withstand voltage. The high-voltage NLDMOS tube NMH3, the constant current source I2, the high-voltage PLDMOS tube PMH3 and the constant current source I3 all form a source electrode following structure, and voltage change is transmitted to the grid electrode of the high-voltage driving tube PMH4 after level shift through the two-stage source electrode following structure, so that the change of the output voltage VOUT is caused. The change in VOUT in turn causes a change in the feedback voltage VFB through the voltage dividing resistor R5 and the resistor R6. Through the negative feedback loop, the output VOUT can be stabilized

When the power supply voltage VDDH is lower thanWhen the output VOUT does not reach the stable voltage valueThe feedback loop may cause the gate voltage of the high voltage driving tube PMH4 to drop. However, the voltage of the grid electrode is the output of a source follower consisting of a high-voltage PLDMOS tube PMH3 and a constant current source I3, and the voltage is less than 0 and the minimum voltage is V _GS,PMH3 The grid-source voltage difference of the high-voltage driving tube PMH4 is at most VDDH-V _GS,PMH3 . When VDDH is low, the gate-source voltage difference is small and highThe on-resistance of the voltage driving tube PMH4 is large and the driving capability is severely degraded. This problem can be solved by the low voltage control circuit 200.

As shown in fig. 3 and 6, the low voltage control circuit 200 samples the power supply voltage VDDH through the voltage dividing resistor R7 and the resistor R8 to obtain a sampled voltageThis voltage is compared with the second reference voltage VREF2 by the comparator COMP. When->When the comparator outputs low level, the switching tube NMH4 is disconnected, and the work of the main circuit of the voltage stabilizer is not affected. When-> When the comparator outputs high level, the switching tube NMH4 is conducted, the grid voltage of the high-voltage driving tube PMH4 output by the voltage stabilizer is pulled down, so that the grid-source voltage difference of the high-voltage driving tube PMH4 is VDDH, the on-resistance of the high-voltage driving tube PMH4 is reduced, the driving capacity is increased, and the output VOUT can change along with the VDDH. In design, the resistance ratio of the resistor R7 and the resistor R8 and the voltage value of VREF2 can be adjusted to enable +.>A stable output voltage slightly lower than the linear voltage regulator +.>

The output end of the linear voltage stabilizer is provided with a large off-chip capacitor, so that the dominant pole is positioned at the output end. In order to stabilize the loop, the secondary pole in the slice needs to be far from the primary pole. In the voltage regulator main circuit 302, the output end of the error amplifier is a high-resistance node, the size of the driving tube is generally larger, and the parasitic capacitance is also larger. In the circuit, the level shift is carried out through a plurality of stages of source follower structures and then the source follower structures are connected to a driving tube, so that on one hand, the output of an error amplifier can be converted from a VDDL voltage domain to a VDDH voltage domain, and on the other hand, as the output impedance of the source follower is smaller, nodes with large resistance and capacitance do not exist, the secondary pole point close to the main pole point is converted into a plurality of poles far away from the main pole point, and the loop becomes stable.

In the linear voltage stabilizer circuit, the power supplies of the error amplifier and the comparator are the output VDDL of the pre-voltage stabilizing circuit, and the voltage is not more than 5.5V, so that the design can be carried out by adopting a normal-pressure pipe, the use quantity of high-pressure pipes is reduced, and the chip area can be greatly reduced. Meanwhile, when the power supply voltage VDDH varies within a wide range, VDDL remains relatively stable, and the performance of the error amplifier does not vary greatly.

In summary, when the power supply voltage VDDH is higher, the linear voltage regulator outputs a stable voltage When the power supply voltage VDDH is lower than +.>When the gate voltage of the driving transistor PMH4 is pulled down by the low voltage control module, the output VOUT follows VDDH, i.e., vout=vddh.

According to the wide power range linear voltage stabilizer disclosed by the invention, the pre-voltage stabilizing circuit 100 is used for stabilizing the power supply voltage and supplying power to the error amplifier and the comparator, the error amplifier and the comparator can be designed by using a normal-pressure pipe, the performance is hardly changed along with the power supply voltage, the use quantity of high-voltage devices is greatly reduced, and the chip cost is lower.

The linear voltage stabilizer with the wide power supply range converts the output of the error amplifier from a normal voltage domain to a high voltage domain through the buffer module of the source electrode follower structure, drives the output power tube, and has the internal pole far away from the main output pole, so that the loop is stable.

The linear voltage stabilizer with the wide power supply range detects the power supply voltage through the low-voltage control circuit, and the grid electrode of the output driving tube is pulled down through the comparator when the power supply voltage is low, so that the output voltage changes along with the power supply voltage, and the output driving capability when the power supply voltage is low is improved.

Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (3)

1. A wide power range linear voltage regulator, comprising a pre-regulator circuit (100), a low voltage control circuit (200) and a regulator body circuit (300); the low-voltage control circuit (200) comprises a power supply sampling module (201) and a power supply comparison module (202); the voltage stabilizer main body circuit (300) consists of an error amplifying module (301), a buffer module (302) and a power output stage (303);

the pre-voltage stabilizing circuit (100) is used for stabilizing the wide-range input power supply voltage VDDH and outputting a voltage VDDL not higher than 5.5V; when the power supply voltage is less than 5.5V, the output voltage VDDL follows the power supply voltage variation, namely vddl=vddh, and when the power supply voltage is higher than or equal to 5.5V, the output voltage vddl=5.5V;

the low-voltage control circuit (200) comprises a power supply sampling module (201) and a power supply comparison module (202), wherein the power supply of the power supply sampling module (201) is input power supply voltage VDDH, and the power supply of the power supply comparison module (202) is output voltage VDDL of the pre-voltage stabilizing circuit (100); the power supply sampling module (201) samples an input power supply voltage VDDH, and the sampled voltage is compared with a reference voltage by the power supply comparison module (202); when the VDDH voltage is higher than the theoretical output voltage of the voltage stabilizer, the controlled switching tube is disconnected; when the VDDH voltage is lower than the theoretical output voltage of the voltage regulator, the power tube of the main body circuit (300) of the voltage regulator is controlled through the switching tube, so that the output voltage of the voltage regulator changes along with the input power supply voltage, namely VOUT=VDDH;

the voltage regulator main body circuit (300) is composed of an error amplifying module (301), a buffer module (302) and a power output stage (303), wherein the error amplifying module (301) is powered by the output voltage VDDL of the pre-voltage regulator circuit (100), and the buffer module (302) and the power output stage (303) are powered by VDDH; the voltage stabilizer main body circuit (300) converts an input power supply voltage into a stable power supply output;

the pre-voltage stabilizing circuit (100) comprises a resistor R1, a resistor R2 and a resistor R3, a first current mirror (101) formed by a normal-pressure NMOS tube NM0 and a normal-pressure NMOS tube NM1, a second current mirror (102) formed by a high-voltage PLDMOS tube PMH0 and a high-voltage PLDMOS tube PMH1, a high-voltage PLDMOS driving tube PMH2, a voltage stabilizing diode Z1 and a voltage stabilizing diode Z2, a high-voltage NLDMOS tube NMH0 and a high-voltage NLDMOS tube NMH1 and an output voltage stabilizing capacitor C; one end of the resistor R1 is connected with the power supply VDDH, and the other end of the resistor R1 is intersected with the negative end of the voltage stabilizing diode Z1, the gate ends of the high-voltage NLDMOS tube NMH0 and the high-voltage NLDMOS tube NMH1 in VGN; the positive end of the voltage stabilizing diode Z1 is connected with the gate end and the drain end of the normal-pressure NMOS tube NM0 and the gate end of the normal-pressure NMOS tube NM1, and the source ends of the normal-pressure NMOS tube NM0 and the normal-pressure NMOS tube NM1 are grounded; the drain end of the normal-pressure NMOS tube NM1 is connected with the source end of the high-pressure NLDMOS tube NMH 0; the drain end of the high-voltage NLDMOS tube NMH0 is connected with the gate end and the drain end of the high-voltage PLDMOS tube PMH0 and the gate end of the high-voltage PLDMOS tube PMH 1; the source ends of the high-voltage PLDMOS tube PMH0 and the high-voltage PLDMOS tube PMH1 are connected with a power supply VDDH; the drain end of the high-voltage PLDMOS tube PMH1, one end of the resistor R2, the positive end of the zener diode Z2 and the gate end of the high-voltage PLDMOS tube PMH2 are intersected at VGP; the other end of the resistor R2 is grounded; the negative end of the zener diode Z2, the source end of the high-voltage PLDMOS tube PMH2 and the drain end of the high-voltage NLDMOS tube NMH1 are connected with a power supply VDDH; the drain end of the high-voltage PLDMOS tube PMH2, the source end of the high-voltage NLDMOS tube NMH1 and one end of the resistor R3 and the capacitor C are intersected at the output VDDL of the voltage stabilizing circuit, and the other ends of the resistor R3 and the capacitor C are grounded;

the power supply sampling module (201) consists of a resistor R7 and a resistor R8, and the power supply comparison module (202) consists of a comparator COMP and a high-voltage NLDMOS tube NMH 4; one end of the resistor R7 is connected with the power supply VDDH, the other end of the resistor R7 is connected with one end of the resistor R8 and is connected to the negative input end of the comparator COMP, and the other end of the resistor R8 is grounded; the power supply of the comparator COMP is the output VDDL of the pre-voltage stabilizing circuit, the positive input end is connected with the reference voltage VREF2, and the output end is connected with the gate end of the high-voltage NLDMOS tube NMH 4; the source end of the high-voltage NLDMOS tube NMH4 is grounded, and the drain end of the high-voltage NLDMOS tube NMH4 is connected with the gate end of the driving tube PMH4 in the power output stage (303).

The error amplifying module (301) comprises an error amplifier AMP, a normal-pressure NMOS tube NM2 and a constant-current source I1; the power end of the error amplifier AMP and the drain end of the normal-pressure NMOS tube NM2 are connected with the output VDDL of the pre-voltage stabilizing circuit; the negative input end of the error amplifier AMP is connected with the reference voltage VREF1, the positive input end of the error amplifier AMP is connected with the feedback voltage VFB, and the output end of the error amplifier AMP is connected with the gate end of the normal-pressure NMOS tube NM 2; the source end of the normal-pressure NMOS tube NM2 is connected with a constant current source I1, and the other end of the constant current source I1 is connected with GND;

the buffer module (302) comprises a high-voltage NLDMOS tube NMH2, a high-voltage NLDMOS tube NMH3, a high-voltage PLDMOS tube PMH4, a resistor R5 and a resistor R6, a voltage stabilizing diode Z3, a constant current source I2 and a constant current source I3; the gate end of the high-voltage NLDMOS tube NMH2 is connected with the bias voltage VB, the source end of the high-voltage NLDMOS tube NMH2 is connected with the source end of the normal-voltage NMOS tube NM2, and the drain end of the high-voltage NLDMOS tube NMH3 is connected with one end of the resistor R4; the other end of the resistor R4, the drain end of the high-voltage NLDMOS tube NMH3, the negative end of the zener diode Z3 and one end of the constant current source I3 are connected to a power supply VDDH; the source end of the high-voltage NLDMOS tube NMH3 is connected with one end of the constant current source I2, the positive end of the zener diode Z3 and the gate end of the high-voltage PLDMOS tube PMH 3; the other end of the constant current source I2 and the drain end of the high-voltage PLDMOS tube PMH3 are grounded; the source end of the high-voltage PLDMOS tube PMH3 is connected with the other end of the constant current source I3;

the power output stage (303) comprises a zener diode Z4, an output high-voltage PLDMOS power tube PMH4, a resistor R5 and a resistor R6; the negative end of the voltage stabilizing diode Z4 and the source end of the output high-voltage PLDMOS power tube PMH4 are connected with a power supply VDDH, and the positive end of the voltage stabilizing diode Z4 and the gate end of the output high-voltage PLDMOS power tube PMH4 are connected with the source end of the high-voltage PLDMOS power tube PMH 3; the drain end of the output high-voltage PLDMOS power tube PMH4 and one end of the resistor R5 are connected with the output end VOUT of the linear voltage stabilizer; the other end of the resistor R5 and one end of the resistor R6 are connected to the VFB and to the positive input end of the error amplifier AMP; the other end of the resistor R6 is grounded.

2. The wide power range linear regulator of claim 1, wherein the voltage regulator values of the voltage regulator diodes Z1, Z2, Z3 and Z4 are 5.5V.

3. The wide power range linear voltage regulator of claim 1, wherein the high voltage NLDMOS and high voltage PLDMOS transistors are thin gate oxide devices with a gate-to-source voltage withstand of about 5.5V.