CN117650175B - A vertical GaN HEMT semiconductor device and a manufacturing method thereof - Google Patents

Abstract

The present invention relates to a vertical GaN HEMT semiconductor device and a manufacturing method thereof. The device includes a stacked structure and a surface drift layer epitaxially grown on a substrate. The stacked structure includes an inner drift layer, a current-balancing layer, and an inner barrier layer interposed therein; a deep trench with a non-flat sidewall is formed on the substrate, penetrating the surface drift layer and the stacked structure, and the inner barrier layer has a protruding portion protruding from the sidewall of the deep trench; the conductivity type of the protruding portion is modified; the surface barrier layer is continuously formed on the surface drift layer and the non-flat sidewall of the deep trench; and a first gate structure is arranged in the deep trench. The present invention has the effect of being able to establish a longitudinal channel in a GaN device and effectively cut off the channel when the device is miniaturized. In a preferred example, a second gate structure is arranged on the surface barrier layer, located between the first gate structure and the source structure.

Description

A vertical GaN HEMT semiconductor device and a manufacturing method thereof

Technical Field

The present invention relates to the technical field of semiconductor devices, and in particular to a vertical GaN HEMT semiconductor device and a manufacturing method thereof, with a specific application being the new energy industry.

Background technique

GaN HEMT semiconductor devices are semiconductor devices prepared with GaN (gallium nitride) as the substrate, and one specific application is high-power semiconductor devices. HEMT is the abbreviation of High Electron Mobility Transistors, which is a wide bandgap power semiconductor device. Compared with silicon-based and silicon carbide-based devices, it has higher electron mobility, saturated electron velocity and breakdown field resistance in high-frequency power applications. Early GaN HEMT semiconductor devices were lateral channel structures, and the current blocking layer (CBL) in the device did not need to be patterned, occupying a large chip area, which was not conducive to the miniaturization of chip products. Gradually, some people proposed a quasi-vertical or vertical channel structure, but the current blocking layer (CBL) needs to be patterned for carrier flow to pass through, resulting in excessively high manufacturing costs. There are two methods for preparing the current blocking layer patterning technology with a channel pattern. One is the epitaxial patterning process during the epitaxial stage. The channel pattern of the current blocking layer is patterned during the epitaxial process. This will lead to a significant increase in the cost of raw materials and the materials are not universal. The other is a post-patterning process after the epitaxial stage. The channel pattern of the current blocking layer is formed by patterned ion implantation. This post-patterning process cannot be prepared to control the concentration and position of the doped ions in the current blocking layer.

Invention patent publication number CN106449727A discloses an avalanche-proof quasi-vertical HEMT, wherein the semiconductor device comprises: a semiconductor body, wherein the first device region located at the bottom layer comprises a drift region of the first conductivity type (equivalent to the channel pattern in the current blocking layer) and a drift current control region of the second conductivity type (equivalent to the patterned current blocking layer), wherein the drift current control region is separated from the second lateral surface by the drift region. The second device region located at the upper layer comprises a blocking layer (equivalent to the surface blocking layer) and a buffer layer (equivalent to the surface drift layer), wherein the buffer layer has a band gap different from that of the blocking layer, so that a two-dimensional charge carrier gas channel (lateral carrier gas channel) appears along the interface between the buffer layer and the blocking layer. The substrate contact forms a low-ohmic connection between the two-dimensional charge carrier gas channel and the drift region. The gate structure is configured to control the conduction state of the two-dimensional charge carrier gas. The drift current control region (equivalent to the patterned current blocking layer) is configured to block the vertical current in the drift region via a space charge region. In the related existing patent technology, the gate structure is a planar gate structure, and there is no vertical carrier gas channel in the drift region of the first conductivity type between the adjacent drift current control regions of the second conductivity type (equivalent to the channel pattern in the current blocking layer), so the architecture can only constitute a quasi-vertical GaN HEMT device. The related existing patent technology does not disclose the specific semiconductor manufacturing process, and those skilled in the art can only infer from the pattern of the drift current control region of the second conductivity type combined with the integrally connected structure of the drift region of the first conductivity type and the drift layer that the patterning method of the drift current control region of the second conductivity type doped with P-type is patterned ion implantation, and the photolithography process required for the patterning mask is inevitable, and it is proved by the nucleation layer on the bottom first device region that the epitaxial growth of the second device region is implemented after the patterning process of the drift current control region (equivalent to the patterned current blocking layer), so the photolithography process is implemented in the multi-layer epitaxial growth. Based on the setting of the nucleation layer in the architecture, it can be inferred that there is secondary epitaxial growth after ion implantation, so it is not only difficult to implement but also will cause the epitaxial wafer to be non-universal.

Invention patent publication number CN113611731A discloses a GaN-based enhanced vertical HEMT device and its preparation method. The structure of the GaN-based enhanced vertical HEMT device includes a drain, a substrate, a drift region, a vertical channel barrier layer, a channel layer, a barrier layer, an interlayer film, a trench gate and a source from bottom to top. The GaN channel layer (equivalent to the surface drift layer) and the AlGaN barrier layer (equivalent to the surface barrier layer) on its upper side and the AlxGa _1-x N vertical channel barrier layer below it form a double heterojunction structure. The structure forms a barrier layer in the vertical channel direction through the GaN/AlGaN heterostructure, thereby blocking the transport of carriers in the vertical direction under the off-state condition, thereby turning off the channel and realizing enhanced characteristics. This structure is to effectively avoid the negative effects of the traditional Mg-doped P-GaN barrier layer. However, there is a risk that the devices of the related existing patent technology cannot be implemented. This is because the carrier gas channel of the GaN device is formed on the side of the surface drift layer (GaN) close to the surface barrier layer (AlGaN) (equivalent to the lateral carrier gas channel), and the two sides and bottom of the buried gate metal below the surface drift layer are the vertical channel barrier layer (equivalent to the inner barrier layer) and the trench gate dielectric, respectively. Under this barrier, the two sides of the gate metal cannot establish a longitudinal carrier flow channel and a longitudinal carrier gas channel that connects the source and the drain, which is an unfinished invention.

Invention patent publication number CN105845724A discloses an accumulation-type vertical HEMT device. In the forward conduction state, a high-concentration electron accumulation layer (equivalent to a longitudinal carrier gas channel) is formed at the sidewall of the insulating gate structure, reducing the on-resistance of the device, thereby ensuring that the device has a good forward current driving capability; in the reverse blocking state, the insulating gate structure (embedded gate) can effectively improve the electric field concentration effect at the interface between the device barrier layer (equivalent to the inner barrier layer) and the buffer layer, and introduce a new electric field spike at the end of the insulating gate structure to make the device electric field uniform. Based on this related existing patent technology, those skilled in the art can know that the lateral carrier gas channel is formed on the side of the channel layer (equivalent to the surface drift layer) close to the barrier layer (equivalent to the surface barrier layer), and the two sides of the insulating gate structure (embedded gate) cannot actually establish a truncated longitudinal carrier gas channel, which is not significantly helpful for the miniaturization of the chip structure. In addition, the built-in multi-layer current blocking layer (equivalent to the inner blocking layer) separated from top to bottom is obviously a patterned structure to form a longitudinal channel extending downward from both sides of the gate, but there is no disclosure and no technical revelation to teach whether there is a cut-off longitudinal carrier gas channel formed here. In addition, the relevant prior art only discloses the device architecture, but does not disclose the manufacturing method of the device architecture. Those skilled in the art can only infer the possible manufacturing method from the prior art. Whether the current blocking layer patterning technology of the channel pattern adopts the epitaxial patterning process during the epitaxial stage or the post-patterning process after the epitaxial stage, it will cause any technical problem of the first problem that the cost of raw materials is greatly increased and the materials are not universal, and the second problem that the concentration and position of the doped ions in the current blocking layer cannot be controlled.

Summary of the invention

The main purpose of the present invention is to provide a vertical GaN HEMT semiconductor device. The main improvement is that a vertical channel of the vertical GaN HEMT semiconductor device can be established without a patterned ion implantation process. Specifically, a vertical carrier gas channel can be provided, so that the development of chip surface miniaturization will not cause an improper shortening of the channel length, thereby eliminating the need for the vertical GaN HEMT to produce a channel pattern of a patterned current blocking layer, which leads to an increase in the cost of the pre-patterning process, lack of material commonality, or post-patterning causing chip function instability.

The second main purpose of the present invention is to provide a semiconductor chip device, including a vertical GaN HEMT semiconductor device, which conforms to the trend of device miniaturization brought about by the GaN-based vertical channel and obtains the convenience of manufacturing the vertical GaN HEMT semiconductor device, because there is no need to pattern a current blocking layer to make a channel pattern.

The third main purpose of the present invention is to provide a method for manufacturing a vertical GaN HEMT semiconductor device, so as to achieve material commonality without the need for epitaxial patterns in the manufacture of the vertical GaN HEMT semiconductor device, thereby eliminating the need for the production of a channel pattern of a patterned current blocking layer on a GaN-based substrate, i.e., omitting the patterned photolithography process for forming the channel pattern.

The main purpose of the present invention is achieved through the following technical solutions:

A vertical GaN HEMT semiconductor device is proposed, comprising:

A stacked structure epitaxially grown on a substrate and a surface drift layer on the stacked structure, wherein the stacked structure includes an inner drift layer, a current balancing layer, and an inner barrier layer interposed therein; wherein the surface drift layer and the stacked structure are etched to form a deep trench with a non-flat sidewall, the deep trench penetrates the surface drift layer and the stacked structure, the inner barrier layer has a protruding portion protruding from the sidewall of the deep trench; the conductivity type of the protruding portion of the inner barrier layer is modified;

a surface barrier layer continuously formed on the surface drift layer and on the non-flat sidewall of the deep trench;

A first gate structure is disposed in the deep trench;

A source structure, disposed on the surface drift layer and located on both sides of the first gate structure;

The drain structure is arranged at the bottom of the device in the opposite direction to the epitaxial growth direction of the stacked structure.

By adopting the above-mentioned structural technical solution, the inner barrier layer has a protruding portion protruding inwardly from the side wall of the deep trench; the conductivity type of the protruding portion of the inner barrier layer is modified, so that longitudinal passages can be established on both sides of the first gate structure; combined with the surface barrier layer continuously extending into the non-flat side wall of the deep trench, intermittent and interruptible longitudinal carrier gas channels located at the end side of the inner drift layer are established in the longitudinal passages on both sides of the first gate structure. While the chip area size is miniaturized, the length of the carrier gas channel will not be reduced synchronously, and there is no need to make a channel pattern of the inner barrier layer.

In a preferred example, the present invention may be further configured as follows: the inner drift layer and the surface drift layer are over-etched so that the non-flat sidewall of the deep trench has an S-shaped cross-sectional shape.

By adopting the above preferred technical features and utilizing the S-shaped cross-sectional shape of the non-flat sidewall of the deep trench, the conductivity type of the protruding portion of the inner barrier layer can be more easily modified.

In a preferred example, the present invention may be further configured as follows: the device further includes a gate dielectric layer formed on the outer surface of the surface barrier layer.

By adopting the above preferred technical features, the first gate structure and the surface blocking layer are isolated by the gate dielectric layer, thereby preventing the silicon element of the first gate structure from diffusing into the lattice of the surface blocking layer.

In a preferred example, the present invention may be further configured as follows: the inner barrier layer conducts electricity between the inner drift layer and the current balancing layer only at the protruding portion.

By adopting the above-mentioned preferred technical features, using the protruding portion as the only longitudinal conductive portion of the inner barrier layer, the inner barrier layer can block the longitudinal movement of carriers outside the two sides of the first gate structure over a large area, which is beneficial to control the longitudinal conductive path from the surface drift layer to the substrate on both sides of the first gate structure.

In a preferred example, the present invention can be further configured as follows: the inner barrier layer is a multi-layer structure, and is also formed between the surface drift layer and the current balancing layer, and between the inner drift layer and the epitaxial bottom layer located below the inner drift layer.

By adopting the above-mentioned preferred technical features and utilizing the inner barrier layer of the multi-layer structure, except for the protruding parts, the inner barrier layer isolates the abnormal conduction between the surface drift layer and the current balancing layer, thereby improving the characteristics of preventing vertical breakdown and better exerting the longitudinal current blocking effect.

In a preferred example, the present invention can be further configured as follows: the surface drift layer forms a truncated lateral carrier gas channel on the side close to the surface blocking layer, and the inner drift layer forms an intermittent truncated longitudinal carrier gas channel on the side edge close to the side wall of the deep trench; based on the connection of the current equalizing layer, the longitudinal carrier gas channel is located in the matrix circuit, and the lateral carrier gas channel is located on one side of the matrix circuit.

By adopting the above-mentioned preferred technical features, the combination of the lateral carrier gas channel and the longitudinal carrier gas channel is utilized to reduce the area occupied by the total channel length on the device surface, which is beneficial to the miniaturization of the chip size; and based on the connection of the current equalizing layer to the longitudinal carrier gas channel, in the conduction stage of the transistor, a matrix circuit is formed between the source and the drain, the longitudinal carrier gas channel is located in the matrix circuit, and the lateral carrier gas channel is located on one side of the matrix circuit, so as to better exert the effect of uniform carrier flow distribution, and the plurality of longitudinal carrier gas channels have the integrity of mutual protection, and a single individual longitudinal carrier gas channel is not easy to burn out.

In a preferred example, the present invention can be further configured as follows: the device also includes a second gate structure, which is arranged on the surface blocking layer and located between the first gate structure and the source structure; preferably, a shallow groove that does not penetrate the surface drift layer is formed on the upper surface of the surface drift layer, so that the bottom surface of the second gate structure is uneven and the lateral carrier gas channel is discontinuous.

By adopting the above-mentioned preferred technical features and utilizing the setting of the second gate structure, in the transistor-off stage, the lateral carrier gas channel can be cut off in multiple sections; in a more preferred feature, utilizing the shallow groove, the second gate structure obtains good non-planar fixation, and the lateral carrier gas channel can be cut off in sections and can be further refined to have multiple sub-conduction sections and sub-cut-off sections between the sub-conduction sections, so that the lateral carrier gas channel is discontinuous, thereby achieving a better cut-off effect.

The second main purpose of the present invention is achieved through the following technical solution: a semiconductor chip device is proposed, including a vertical GaN HEMT semiconductor device that can implement the feature combination as described above.

The third main purpose of the present invention is achieved through the following technical solutions:

A method for manufacturing a vertical GaN HEMT semiconductor device is proposed, comprising:

Step S1, providing a substrate, on which a stacked structure and a surface drift layer on the stacked structure are epitaxially grown, wherein the stacked structure includes an inner drift layer, a current balancing layer, and an inner barrier layer interposed therebetween;

Step S2, etching the surface drift layer and the stacked structure to form a deep trench with a non-flat sidewall on the substrate, wherein the deep trench penetrates the surface drift layer and the stacked structure, and the inner barrier layer has a protruding portion protruding from the sidewall of the deep trench;

Step S3, modifying the protruding parts of the inner barrier layer;

Step S4, continuously forming a surface barrier layer on the surface drift layer and on the non-flat sidewall of the deep trench;

Step S5, disposing a first gate structure in the deep trench;

Step S6, disposing a source structure on the surface drift layer, wherein the source structure is located on both sides of the first gate structure;

Step S7: setting a drain structure as the bottom of the device in the direction opposite to the epitaxial growth direction of the stacked structure; specifically, the drain structure may be set on the back side of the substrate.

By adopting the above method and technical solution, a GaN HEMT semiconductor device having both a lateral carrier gas channel and a longitudinal carrier gas channel can be manufactured.

The present invention can be further configured as follows in a preferred example:

In step S1, the stacked structure and the surface drift layer are patternless blank film layers epitaxially grown on the substrate in a fully covering manner;

Step S2 includes selectively etching the deep trench so that the inner drift layer and the surface drift layer are over-etched, so that the non-flat sidewall of the deep trench has an S-shaped cross-sectional shape;

Step S3 includes oblique angle ion implantation, and the implantation mask layer used is the same as the etching mask layer used in step S2, so as to change the conductivity type of the protruding part of the inner barrier layer to be consistent with the current balancing layer;

Preferably, after step S1 and before step S4, the method further comprises: step S31, forming a shallow trench in the surface drift layer, wherein the shallow trench does not penetrate the surface drift layer, so that the bottom surface of the second gate structure provided in step S5 is non-flat, and the lateral carrier gas channel is discontinuous;

After forming the surface barrier layer in step S4, the following steps are further included: step S41, forming a gate dielectric layer on the outer surface of the surface barrier layer;

In step S5, a second gate structure is further arranged on the surface barrier layer, and the second gate structure is located between the first gate structure and the source structure; in step S5, the first gate structure and the second gate structure are conductive polysilicon;

In step S6, the source structure is conductive polysilicon; after step S6, it also includes: step S61, forming an interlayer film on the surface barrier layer, the interlayer film substantially covers the first gate structure in the device area, and the interlayer film does not cover the upper end surface of the source structure; step S62, setting a source metal on the interlayer film.

In summary, the present invention includes at least one of the following technical effects that contribute to the prior art:

1. Eliminate the difficulty of manufacturing a patterned current blocking layer in the existing vertical GaN HEMT semiconductor device, and solve the technical defects that the epitaxial wafer cannot be shared or/and the process stability is poor due to the existence of the patterned current blocking layer;

2. Adding additional functions to the gate trench can eliminate the patterning process of the current blocking layer;

3. Under the same channel length specification, based on the vertical carrier gas channel, the occupied area on the chip surface can be reduced;

4. Based on the second gate structure, the impedance of the transistor can be adjusted in different areas, so that the GaN HEMT semiconductor device has better product stability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional view of a vertical GaN HEMT semiconductor device according to some preferred embodiments of the present invention;

FIG. 2 is a block diagram showing a method for manufacturing a vertical GaN HEMT semiconductor device according to some preferred embodiments of the present invention;

FIG3 is a schematic cross-sectional view of components corresponding to step S1 of FIG2 in some preferred embodiments of the present invention;

FIG. 4 is a schematic cross-sectional view of components corresponding to step S2 of FIG. 2 in some preferred embodiments of the present invention;

FIG5 is a schematic cross-sectional view of components corresponding to step S3 of FIG2 in some preferred embodiments of the present invention;

FIG6 is a schematic cross-sectional view of components corresponding to step S4 of FIG2 in some preferred embodiments of the present invention;

FIG. 7 is a schematic cross-sectional view of components corresponding to step S5 of FIG. 2 in some preferred embodiments of the present invention;

FIG8 is a schematic cross-sectional view of components corresponding to step S6 of FIG2 in some preferred embodiments of the present invention;

FIG. 9 is a schematic cross-sectional view of components corresponding to step S7 of FIG. 2 in some preferred embodiments of the present invention;

FIG. 10 is a schematic cross-sectional view of a vertical GaN HEMT semiconductor device in a gate operating state according to some preferred embodiments of the present invention;

FIG. 11 is a schematic cross-sectional view of vertical GaN HEMT semiconductor devices according to some other preferred embodiments of the present invention;

FIG. 12 is a schematic cross-sectional view of a vertical GaN HEMT semiconductor device in a gate operating state according to some other preferred embodiments of the present invention;

FIG. 13 is a schematic cross-sectional view of forming shallow trenches in the manufacture of vertical GaN HEMT semiconductor devices according to some other preferred embodiments of the present invention.

Figure numerals: 10, substrate; 101, transfer plate; 11, deep trench; 20, stacked structure; 21, inner drift layer; 21a, longitudinal carrier gas channel; 22, current equalizing layer; 23, inner barrier layer; 23a, protruding portion; 24, epitaxial bottom layer; 25, isolation junction; 30, surface drift layer; 30a, lateral carrier gas channel; 31, shallow trench; 40, surface barrier layer; 50, first gate structure; 51, gate dielectric layer; 60, source structure; 61, source metal; 70, drain structure; 80, second gate structure; 90, interlayer film; 110, hard mask layer.

Detailed ways

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments for understanding the inventive concept of the present invention, and cannot represent all the embodiments, nor are they interpreted as the only embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field on the premise of understanding the inventive concept of the present invention are within the scope of protection of the present invention.

It should be noted that if there are directional indications (such as up, down, left, right, front, back, etc.) involved in the embodiments of the present invention, the directional indications are only used to explain the relative position relationship, movement, etc. between the components in a certain posture. If the specific posture changes, the directional indications will also change accordingly. In order to facilitate the understanding of the technical solution of the present invention, the vertical GaN HEMT semiconductor device and the manufacturing method thereof of the present invention are further described and explained in detail below, but they are not limited to the protection scope of the present invention.

FIG1 is a schematic cross-sectional view of a vertical GaN HEMT semiconductor device in some preferred embodiments of the present invention. The drawings only show the common parts of multiple embodiments, and the parts with differences or distinctions are described in text or presented in comparison with the drawings. Therefore, based on the industrial characteristics and technical essence, technicians familiar with the field should correctly and reasonably understand and judge whether the individual technical features described below or any combination of them can be characterized in the same embodiment, or whether multiple technical features with mutually exclusive technical essences can only be characterized in different variant embodiments. The embodiments with too similar drawings will not be drawn repeatedly.

Referring to FIG. 1 , some embodiments of the present invention disclose a vertical GaN HEMT semiconductor device, including a substrate 10 for arranging a drain and having a stacked structure 20 and a surface drift layer 30 thereon, a surface barrier layer 40 located on the substrate 10 for isolating a gate and a source, a first gate structure 50 penetrating the surface drift layer 30 and embedded in the stacked structure 20, a source structure 60 arranged on the surface drift layer 30, and a drain structure 70 arranged on the back of the substrate 10. Among them, the substrate 10, the stacked structure 20, the surface drift layer 30 and the surface barrier layer 40 are all made of semiconductor single crystal materials, and the basic material can be but not limited to GaN (gallium nitride), or a group IV semiconductor, a group III-V semiconductor or a group II-VI semiconductor with the same function, such as SiC, which is also another choice of basic material, and if necessary, each layer can be doped with the required chemical elements to adjust its electrical characteristics. In the aforementioned semiconductor structure, carriers can conduct the source structure 60 and the drain structure 70. The surface blocking layer 40 can also be called a surface blocking layer or a surface barrier layer. Based on the influence of the surface blocking layer 40 on the surface drift layer 30, it is relatively easy to form a carrier flow path on the surface of the surface drift layer 30. For example, the material of the surface drift layer 30 is intrinsic GaN, which is electrically N-type, and the material of the surface blocking layer 40 is AlGaN, which is electrically P-type. The surface of the surface drift layer 30 adjacent to the surface blocking layer 40 is N-type. The carrier flow path includes a lateral carrier gas channel 30a and a longitudinal carrier gas channel 21a as shown in FIG. 1. Based on the electric field effect of the first gate structure 50, the lateral carrier gas channel 30a and the longitudinal carrier gas channel 21a can be shut off by the first gate structure 50, as shown in FIG. 1 and FIG. 10. In the example, the carriers are specifically electrons. When the first gate structure 50 is in a negative electric field, the surface drift layer 30 adjacent to the first gate structure 50 is transformed into a positive electric tendency, and the surface N-type increase characteristic of the surface drift layer 30 is eliminated by the gate electric field, and the lateral carrier gas channel 30a and the longitudinal carrier gas channel 21a are in the off state (the changes between Figures 1 and 10 can be compared).

The stacked structure 20 and the surface drift layer 30 located on the stacked structure 20 are epitaxially grown in sequence on the substrate 10. The substrate 10 is a semiconductor single crystal structure. Based on the semiconductor epitaxial growth process, the stacked structure 20 and the surface drift layer 30 are also semiconductor single crystal structures. In this example, the material of the substrate 10 is specifically N+ type GaN material, the material of the surface drift layer 30 is specifically GaN intrinsic material or N-type semiconductor material, and the basic material of the stacked structure 20 is GaN. The stacked structure 20 includes an inner drift layer 21, a current equalizing layer 22, and an inner barrier layer 23 interposed therein. The inner barrier layer 23 has more than two layers and is mainly used to separate the surface drift layer 30 from the inner drift layer 21 and to separate the inner drift layer 21 from the conductive layer at the bottom of the device (specifically, the substrate 10 or the epitaxial bottom layer 24). The material of the inner drift layer 21 is specifically GaN intrinsic material or N-type semiconductor material, the material of the current equalizing layer 22 is specifically N+ type GaN material, and the material of the inner barrier layer 23 is specifically P type GaN material, specifically AlGaN. More specifically, the bottom layer of the stacked structure 20 is the epitaxial bottom layer 24. As the bottom drift layer, the material of the epitaxial bottom layer 24 is specifically N-type GaN material. The epitaxial bottom layer 24 has a lower doping concentration than the current equalizing layer 22, and the doping component can be silicon, germanium or other N-type materials.

Furthermore, a deep trench 11 with non-flat sidewalls is formed by etching the surface drift layer 30 and the stacked structure 20 on the substrate 10. The deep trench 11 penetrates the surface drift layer 30 and the stacked structure 20, and specifically stops at the epitaxial bottom layer 24. The inner barrier layer 23 has a protruding portion 23a protruding from the sidewall of the deep trench 11. The protruding portion 23a protrudes from both the same side edge of the inner drift layer 21 and the same side edge of the current balancing layer 22. The conductivity type of the protruding portion 23a of the inner barrier layer 23 is modified so that the conductivity type of the protruding portion 23a is the same as that of the inner drift layer 21 or the current balancing layer 22. Based on the protruding portion 23a, the sidewalls of the deep trench 11 are non-flat and straight sidewalls, and the deep trench 11 is a multi-link structure. In addition, in the working area of the semiconductor device (i.e., the main area excluding the external contact welding area), no doping well is required except for the area of the deep trench 11. In the example, the epitaxial bottom layer 24 forms an isolation junction 25 below the deep trench 11. The well area of the isolation junction 25 is defined by the notch shape of the deep trench 11, and no additional photolithography development step is required. The conductivity type of the isolation junction 25 is opposite to the conductivity type of the epitaxial bottom layer 24. For example, the isolation junction 25 is P-type, and the doping component can be a chemical element of group III or group II. There is unidirectional non-conduction between PN types, and bidirectional non-conduction between PNP types or NPN types. The aforementioned doping components, except for the isolation junction 25, and the doping components that may be required for other layers are formed together using in-situ doping technology during epitaxial growth.

The surface barrier layer 40 is continuously formed on the surface drift layer 30 and the non-flat sidewall of the deep trench 11. The surface barrier layer 40 can be specifically prepared by a secondary epitaxial process after the deep trench 11 is formed by etching. In the example, the material of the surface barrier layer 40 is specifically a P-type GaN material, specifically AlGaN. The surface barrier layer 40 has a band gap different from that of the surface drift layer 30, so that a lateral carrier gas channel 30a and a longitudinal carrier gas channel 21a appear near the interface between the surface drift layer 30 and the longitudinal carrier gas channel 21a, and the longitudinal carrier gas channel 21a is also formed on the side edge of the inner drift layer 21. The first gate structure 50 is arranged in the deep trench 11 to shut off the lateral carrier gas channel 30a and the longitudinal carrier gas channel 21a. The common material of the first gate structure 50 is heavily doped conductive polysilicon, and it can also be other conductive materials. In addition, before the first gate structure 50 is set, a gate dielectric layer 51 can be first formed on the surface of the surface blocking layer 40, and the material of the gate dielectric layer 51 is a dielectric insulating material of metal nitride or metal oxide. The gate dielectric layer 51 isolates the conduction between the surface blocking layer 40 and the first gate structure 50. The thickness of the gate dielectric layer 51 and the surface blocking layer 40 is thin enough. The potential of the first gate structure 50 can affect the surface conductivity type of the surface drift layer 30 and the inner drift layer 21 to shut off the lateral carrier gas channel 30a and the longitudinal carrier gas channel 21a.

The source structure 60 is disposed on the surface drift layer 30 and is located on both sides of the first gate structure 50. The source structure 60 is electrically connected to the surface drift layer 30. The material of the source structure 60 can be conductive polysilicon, copper, aluminum, titanium or other suitable alloys. In order to prevent the components of the source structure 60 from diffusing into the surface drift layer 30, a barrier layer (not shown) can be formed at the contact interface between the two.

The drain structure 70 is arranged at the bottom of the device in the opposite direction to the epitaxial growth direction of the stacked structure 20. Specifically, the drain structure 70 is arranged on the back side of the substrate 10. In different examples, the substrate 10 can be peeled off or removed, and the drain structure 70 can be directly arranged on the lower surface of the stacked structure 20, or the drain structure 70 can be arranged on the bottom surface of the transfer substrate 101 that is separately mounted after the semiconductor process (as shown in Figures 11 and 12). The transfer substrate can be any conductive material, which should play an interface buffering role and a longitudinal electrical conduction role in joining the stacked structure 20 and the drain structure 70, but is no longer limited to semiconductor materials.

In an embodiment of the basic structure, the inner barrier layer 23 has a protruding portion 23a protruding inwardly from the side wall of the deep trench 11. The conductivity type of the protruding portion 23a of the inner barrier layer 23 can be modified without the need for an additional photolithography and development process, and longitudinal passages can be established on both sides of the first gate structure 50; combined with the surface barrier layer 40 continuously extending into the non-flat side wall of the deep trench 11, intermittent and interruptible longitudinal carrier gas channels 21a located at the end side of the inner drift layer 21 are established in the longitudinal passages on both sides of the first gate structure 50. While the chip area size is miniaturized, the length of the carrier gas channel will not be reduced synchronously, and there is no need to make a channel pattern of the inner barrier layer 23.

In a preferred example, regarding the sidewall shape of the deep trench 11, the inner drift layer 21 and the surface drift layer 30 can be over-etched laterally in an isotropic selective etching manner, so that the non-flat sidewall of the deep trench 11 has an S-shaped wavy cross-sectional shape. With this S-shaped cross-sectional shape, the conductivity type of the protruding portion 23a of the inner barrier layer 23 is more easily modified.

In a preferred example, regarding the internal structure of the stacked structure 20, the inner barrier layer 23 conducts the inner drift layer 21 and the current equalizing layer 22 only at the protruding portion 23a. By utilizing the fact that the inner barrier layer 23 is only connected at the protruding portion 23a in the longitudinal direction, the inner barrier layer 23 can block the longitudinal movement of carriers outside the two sides of the first gate structure 50 over a large area, which is beneficial to control the longitudinal conduction path from the surface drift layer 30 to the substrate 10 at the two sides of the first gate structure 50.

In a preferred example, regarding the specific structure of the inner barrier layer 23, the inner barrier layer 23 is a multi-layer structure, and is also formed between the surface drift layer 30 and the current balancing layer 22, and between the inner drift layer 21 and the epitaxial bottom layer 24 located below the inner drift layer 21. By using the multi-layer structure of the inner barrier layer 23, except for the protruding portion 23a, the inner barrier layer 23 isolates the abnormal conduction between the surface drift layer 30 and the current balancing layer 22, improves the characteristic of preventing vertical breakdown, and better exerts the longitudinal current blocking effect.

In a preferred example, regarding the specific structure of the first gate structure 50, the device further includes a gate dielectric layer 51, which can be formed on the outer surface of the surface barrier layer 40. The gate dielectric layer 51 is used to isolate the first gate structure 50 from the surface barrier layer 40 to prevent the silicon element of the first gate structure 50 from diffusing into the lattice of the surface barrier layer 40. The first gate structure 50 can be protruding higher than the gate dielectric layer 51 to increase the off-length of the channel; in different examples, the first gate structure 50 can also be flush with the gate dielectric layer 51 to reduce the coverage thickness of the interlayer film 90. In a further specific example, the interlayer film 90 is electrically insulating and covers the gate dielectric layer 51 or the surface barrier layer 40. The interlayer film 90 and the source structure 60 are in the same layer structure to protect the source structure 60. A layer of source metal 61 can be formed on the interlayer film 90 to connect the source structure 60.

It can be seen that the surface drift layer 30 forms a truncated lateral carrier gas channel 30a on one side close to the surface barrier layer 40, and the inner drift layer 21 forms a discontinuous truncated longitudinal carrier gas channel 21a on the side edge close to the side wall of the deep trench 11, which is an N-type channel in this example. Based on the connection of the current equalizing layer 22, the longitudinal carrier gas channel 21a is located in the matrix circuit, and the lateral carrier gas channel 30a is located on one side of the matrix circuit. The combination of the lateral carrier gas channel 30a and the longitudinal carrier gas channel 21a is utilized to reduce the area occupied by the total channel length on the device surface, which is beneficial to the miniaturization of the chip size; and based on the connection of the current equalizing layer 22 to the longitudinal carrier gas channel 21a, in the conduction stage of the transistor, a matrix circuit is formed between the source structure 60 and the drain structure 70, the longitudinal carrier gas channel 21a is located in the matrix circuit, and the lateral carrier gas channel 30a is located on one side of the matrix circuit, so as to better exert the effect of uniform carrier flow distribution, and the plurality of longitudinal carrier gas channels 21a have a mutually protective integrity, and a single individual longitudinal carrier gas channel 21a is not easily burned.

2 and in conjunction with FIGS. 3 to 10 , some embodiments of the present invention further disclose a vertical GaN HEMT semiconductor device, including steps S1 to S7 as described below.

Step S1 can refer to FIG. 3, and provide a substrate 10, on which a stacked structure 20 and a surface drift layer 30 on the stacked structure 20 are epitaxially grown, and the stacked structure 20 includes an inner drift layer 21, a current balancing layer 22, and an inner barrier layer 23 disposed therein. In step S1, the substrate 10 is in the form of a wafer. In this example, the epitaxial growth sequence of the stacked structure 20 is an epitaxial bottom layer 24, an inner barrier layer 23, an inner drift layer 21, an inner barrier layer 23, a current balancing layer 22, and an inner barrier layer 23, and the surface drift layer 30 is epitaxially grown on the uppermost inner barrier layer 23. Among them, when the inner barrier layer 23 is of the first conductive type, the inner drift layer 21 and the current balancing layer 22 have the same second conductive type, and the inner barrier layer 23 of the first conductive type is arranged between two adjacent layers of the second conductive type, and the number of layers of the inner drift layer 21 and the current balancing layer 22 is not limited to one layer, and multiple layers can be used. In a preferred example, in step S1 , the stacked structure 20 and the surface drift layer 30 are patternless blank film layers epitaxially grown on the substrate 10 to fully cover the entire surface, and can be used as a public wafer.

Step S2 can refer to FIG. 4 , based on the post-lithography pattern of the hard mask layer 110, the surface drift layer 30 and the stacked structure 20 are etched to form a deep trench 11 with a non-flat sidewall on the substrate 10, the deep trench 11 penetrates the surface drift layer 30 and the stacked structure 20, and the inner barrier layer 23 has a protruding portion 23a protruding from the sidewall of the deep trench 11. The specific sub-step is to firstly etch the deep trench 11 longitudinally to a preset depth by anisotropic etching, and then use isotropic over-selective etching, the etching gas used has a slower etching efficiency for the inner barrier layer 23 than other layers, so that the non-flat sidewall of the deep trench 11 has an S-shaped cross-sectional shape. Therefore, the protruding portion 23a of the inner barrier layer 23 can be formed.

Step S3 can refer to FIG. 5 to modify the protruding portion 23a of the inner barrier layer 23. The modification method is ion implantation, in which a material component having a second conductivity type is injected into the protruding portion 23a of the inner barrier layer 23 of the first conductivity type in an implantation direction at an oblique angle, and the protruding portion 23a is converted into the second conductivity type, in order to be consistent with the conductivity type of the inner drift layer 21 and the current balancing layer 22. In a preferred example, under the shielding of the hard mask layer 110, anisotropic longitudinal ion implantation method is used to inject a material component having a first conductivity type into the epitaxial bottom layer 24 of the second conductivity type corresponding to the bottom of the deep trench 11 to form an isolation junction 25. The hard mask layer 110 can be used as a formation pattern of the deep trench 11, as a modification shield of the protruding portion 23a, and as a formation pattern of the isolation junction 25, so only one photolithography development of the hard mask layer 110 is required.

Step S4 can refer to Figure 6 to continuously form a surface barrier layer 40 on the surface drift layer 30 and on the non-flat sidewalls of the deep trench 11. The specific operation is to first remove the hard mask layer 110, clean the deep trench 11, and then epitaxially grow the surface barrier layer 40 on the outer surface of the surface drift layer 30, and also epitaxially grow it on the non-flat sidewalls of the deep trench 11. The aforementioned isolation junction 25 can relatively increase the thickness of the first conductive type well region of the surface barrier layer 40 under the bottom of the deep trench 11. In a preferred example, after forming the surface barrier layer 40 in step S4, it also includes: step S41, forming a gate dielectric layer 51 on the outer surface of the surface barrier layer 40. One method for forming the gate dielectric layer 51 is a thin film deposition technology of CVD or ALD.

Step S5 can refer to Fig. 7, and a first gate structure 50 is disposed in the deep trench 11. The first gate structure 50 is disposed by polysilicon filling.

Step S6 can refer to FIG. 8 , and a source structure 60 is provided on the surface drift layer 30 , and the source structure 60 is located on both sides of the first gate structure 50 . The source structure 60 can be bonded to the surface drift layer 30 , or directly bonded to the surface barrier layer 40 . When the source structure 60 is bonded to the surface drift layer 30 , a well layer (not shown) of the first conductivity type in the reverse direction can be preferably provided at the bottom layer of the integration layer including the epitaxial bottom layer 24 and the substrate 10 , so as to form a unidirectional conduction protection measure. When the source structure 60 is bonded to the surface barrier layer 40 , a unidirectional conduction protection measure will be formed between the surface barrier layer 40 and the surface drift layer 30 at the bottom of the source structure 60 . In this embodiment, the first conductivity type is P type, and the second conductivity type is N type; in the variation example, the first conductivity type is N type, and the second conductivity type is P type.

In a preferred example, in step S6, the source structure 60 is conductive polysilicon; after step S6, it also includes: step S61, forming an interlayer film 90 on the surface blocking layer 40, the interlayer film 90 substantially covers the first gate structure 50 in the device area, and the interlayer film 90 does not cover the upper end surface of the source structure 60; step S62, setting the source metal 61 on the interlayer film 90.

Step S7 can refer to FIG9 , in which a drain structure 70 is provided as the bottom of the device in the direction opposite to the epitaxial growth direction of the stacked structure 20 . In a specific example, the drain structure 70 is provided on the back side of the substrate 10 .

Therefore, based on the above manufacturing method, a GaN HEMT semiconductor device having both the lateral carrier gas channel 30 a and the vertical carrier gas channel 21 a can be manufactured.

Referring to FIG. 11 and FIG. 12, a vertical GaN HEMT semiconductor device disclosed in some other embodiments of the present invention includes the main basic components as described above, FIG. 11 shows the transistor-on state of the semiconductor device, and FIG. 12 shows the transistor-off state of the semiconductor device. In this preferred example, the device further includes a second gate structure 80, which is disposed on the surface barrier layer 40 and is located between the first gate structure 50 and the source structure 60; in a preferred example, a shallow groove 31 that does not penetrate the surface drift layer 30 is formed on the upper surface of the surface drift layer 30, so that the bottom surface of the second gate structure 80 is non-flat and the lateral carrier gas channel 30a is non-continuous. By using the second gate structure 80, in the transistor off stage, the lateral carrier gas channel 30a is multi-section and can be cut off; in a more preferred feature, by using the shallow groove 31, the second gate structure 80 is well fixed to a non-planar surface, and the lateral carrier gas channel 30a is a cut-off section that can be further refined to have multiple sub-conducting sections and sub-cut-off sections between the sub-conducting sections, so that the lateral carrier gas channel 30a is discontinuous, achieving a better cut-off effect. The manufacturing method of the vertical GaN HEMT semiconductor device includes the main steps S1 to S7 as described in FIG. 2 of the first embodiment.

FIG13 illustrates a method for manufacturing the shallow trench 31. In a preferred example, after step S1 of providing the substrate 10 and before step S4 of forming the surface barrier layer 40, the method further includes: step S31, forming a shallow trench 31 in the surface drift layer 30, wherein the shallow trench 31 does not penetrate the surface drift layer 30, so that the bottom surface of the second gate structure 80 provided in step S5 is non-flat, and the lateral carrier gas channel 30a is non-continuous, that is, not a continuous section. The main difference between the deep trench 11 and the shallow trench 31 is that the deep trench 11 penetrates the surface drift layer 30 and the remaining layers of the stacked structure 20 except the epitaxial bottom layer 24, and the depth of the shallow trench 31 specifically does not exceed one-half of the thickness of the surface drift layer 30.

In a preferred example, in step S5, a second gate structure 80 is further provided on the surface barrier layer 40, and the second gate structure 80 is located between the first gate structure 50 and the source structure 60; in step S5, the first gate structure 50 and the second gate structure 80 are conductive polysilicon. After the source structure 60 is provided in step S6, based on the existence of the source metal 61, the semiconductor device itself has sufficient supporting strength, and the substrate 10 can be removed, or the substrate 10 can be replaced with a transfer plate 101, and then the drain structure 70 is provided on the transfer plate 101 in step S7 (as shown in FIGS. 11 and 12).

The embodiments of this specific implementation method are all preferred embodiments for facilitating understanding or implementing the technical solutions of the present invention, and are not intended to limit the protection scope of the present invention. All equivalent changes made based on the structure, shape, and principle of the present invention should be included in the protection scope of the present invention.

Claims (12)

1. A vertical GaN HEMT semiconductor device comprising:

a stacked structure epitaxially grown on a substrate and a surface drift layer on the stacked structure, wherein the stacked structure comprises an inner drift layer, a uniform current layer and an inner resistance layer arranged therebetween; a deep trench with a non-flat side wall is etched on the surface drift layer and the laminated structure, the deep trench penetrates through the surface drift layer and the laminated structure, and the inner barrier layer is provided with a protruding part protruding inwards on the side wall of the deep trench; the conductivity type of the protruding part of the inner blocking layer is modified, and the inner blocking layer conducts the inner drift layer and the current equalizing layer only at the protruding part;

a surface blocking layer continuously formed on the surface drift layer and on the non-planar sidewalls of the deep trenches;

a first gate structure disposed in the deep trench;

A source electrode structure arranged on the surface drift layer and positioned at two sides of the first gate electrode structure;

a drain structure arranged at the bottom of the device opposite to the epitaxial growth direction of the laminated structure;

the surface drift layer is provided with a lateral carrier gas channel which can be interrupted at one side close to the surface blocking layer, and the inner drift layer is provided with a longitudinal carrier gas channel which can be interrupted at the side edge close to the side wall of the deep groove.

2. The vertical GaN HEMT semiconductor device of claim 1, wherein said inner drift layer and said face drift layer are over etched such that non-planar sidewalls of said deep trench have an S-shaped cross-sectional shape.

3. The vertical GaN HEMT semiconductor device of claim 1, further comprising a gate dielectric layer formed on an outer surface of said face barrier layer.

4. The vertical GaN HEMT semiconductor device of claim 1, wherein said inner resistance layer is a multilayer structure further formed between said face drift layer and said current sharing layer and between said inner drift layer and an epitaxial underlayer below said inner drift layer.

5. The vertical GaN HEMT semiconductor device of claim 1, further comprising a second gate structure disposed on said plane blocking layer and between said first gate structure and said source structure;

A shallow trench is formed from the upper surface of the face drift layer that does not penetrate the face drift layer so that the bottom surface of the second gate structure is non-planar and the lateral carrier gas channel is discontinuous.

6. A semiconductor chip device comprising a vertical GaN HEMT semiconductor device according to any one of claims 1-5.

7. A method of manufacturing a vertical GaN HEMT semiconductor device, comprising:

s1, providing a substrate, wherein a laminated structure and a surface drift layer on the laminated structure are epitaxially grown on the substrate, and the laminated structure comprises an inner drift layer, a uniform flow layer and an inner resistance layer arranged therebetween;

s2, etching the surface drift layer and the laminated structure to form a deep trench with a non-flat side wall on the substrate, wherein the deep trench penetrates through the surface drift layer and the laminated structure, and the inner barrier layer is provided with a protruding part protruding inwards at the side wall of the deep trench;

s3, modifying protruding parts of the inner resistance layer, wherein the inner resistance layer conducts the inner drift layer and the current sharing layer only at the protruding parts;

s4, continuously forming a surface blocking layer on the surface drift layer and on the non-flat side wall of the deep trench;

S5, setting a first grid structure in the deep trench;

s6, arranging a source electrode structure on the surface drift layer, wherein the source electrode structure is positioned on two sides of the first grid electrode structure;

s7, setting a drain electrode structure as the bottom of the device in the direction opposite to the epitaxial growth direction of the laminated structure; the surface drift layer is provided with a lateral carrier gas channel which can be interrupted at one side close to the surface blocking layer, and the inner drift layer is provided with a longitudinal carrier gas channel which can be interrupted at the side edge close to the side wall of the deep groove.

8. The method for manufacturing the vertical GaN HEMT semiconductor device according to claim 7, wherein:

in step S1, the stacked structure and the surface drift layer are a non-pattern blank film layer epitaxially grown on the substrate in a full coverage manner;

step S2, etching the deep groove selectively to enable the inner drift layer and the surface drift layer to be excessively etched, so that the non-flat side wall of the deep groove has an S-shaped cross section;

step S3 includes bevel ion implantation, and the implantation mask layer used in step S2 is followed by etching the mask layer to change the conductivity type of the protruding portion of the inner barrier layer to be consistent with the current equalizing layer.

9. The method for manufacturing the vertical GaN HEMT semiconductor device according to claim 8, wherein: after forming the surface blocking layer in step S4, the method further comprises: s41, forming a gate dielectric layer on the outer surface of the surface barrier layer.

10. The method for manufacturing the vertical GaN HEMT semiconductor device according to claim 8, wherein: step S5 further includes disposing a second gate structure on the surface blocking layer, where the second gate structure is located between the first gate structure and the source structure; in step S5, the first gate structure and the second gate structure are conductive polysilicon.

11. The method for manufacturing the vertical GaN HEMT semiconductor device according to claim 10, wherein: the method further comprises the following steps after the step S1 and before the step S4: s31, forming shallow trenches in the surface drift layer, wherein the shallow trenches do not penetrate through the surface drift layer, so that the bottom surface of the second gate structure arranged in the step S5 is non-flat, and the transverse carrier gas channel is discontinuous.

12. The method for manufacturing the vertical GaN HEMT semiconductor device according to claim 7, wherein: in step S6, the source electrode structure is conductive polysilicon; after step S6, the method further comprises: s61, forming an interlayer film on the surface blocking layer, wherein the interlayer film substantially covers the first gate structure of the device region, and the interlayer film does not cover the upper end surface of the source structure; s62, disposing source metal on the interlayer film.