CN117630981A - Signal simulation source device for satellite navigation chip verification and test - Google Patents
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Abstract
The application relates to the technical field of satellite navigation signal simulation and test, and discloses a signal simulation source device for satellite navigation chip verification and test, which comprises a carrier wave generator, a code generator, a noise generator, an interference generator, a signal generation module and a register read-write module; the signal generating module receives output signals of the carrier generator, the code generator, the noise generator and the interference generator, and generates a target intermediate frequency signal by combining register configuration of the register read-write module; the register read-write module is electrically connected with the CPU subsystem through the APB bus. The method has the advantages that the method simulates the generation of all-frequency points of the single-channel satellite navigation whole system and the low-orbit navigation enhanced intermediate frequency signals so as to effectively support the functional performance verification of the chip baseband signal processing module and facilitate the design of the investigation module, the verification and test environment is simpler and more convenient to build, the verification and test efficiency is improved, and the acquisition cost and the labor cost of verification and test equipment are reduced.
Description
Technical Field
The application relates to the technical field of satellite navigation signal simulation and test, in particular to a signal simulation source device for satellite navigation chip verification and test.
Background
The satellite navigation chip can be used for receiving and processing radio frequency signals or intermediate frequency signals of satellites, sequentially completing the functions of radio frequency receiving, analog-to-digital conversion, interference detection and suppression, data preprocessing, capturing, tracking, observational quantity generation, text demodulation, position speed time resolving and the like, and finally providing positioning, speed measuring and time service for users. The verification and test of the traditional satellite navigation chip are not separated from the assistance of special equipment such as a satellite navigation signal simulation source, an interference source and the like.
The satellite navigation signal simulation source device can generate satellite navigation radio frequency signals of different frequency points of different systems, supports the configuration of satellite types and quantity, user dynamics and signal carrier-to-noise ratio, and can test the functional performance indexes such as signal receiving, anti-interference, starting time, capturing tracking sensitivity, positioning speed measurement time service precision and the like of a satellite navigation chip by matching with an interference signal source and related hardware.
When the satellite navigation signal analog source device is used for verification or test, the output power of the combined signal of the satellite navigation signal analog source and the interference source is usually required to be divided into multiple paths to be transmitted to each chip test platform, and the key function performance test of one batch of chips is finished according to the test flow set in advance, and the next batch of chips is replaced after the test is finished. In the verification and test process, equipment such as a satellite navigation signal simulation source, an interference source, an intermediate frequency data acquisition and playback device, a radio frequency front end board card and the like, and a power divider, a combiner, a low-noise amplifier and other radio frequency connectors are required to be connected in advance, so that the verification and test environment is complex to build, and verification and test efficiency are affected.
Disclosure of Invention
In order to reduce the environment construction complexity of verification test and improve verification and test efficiency, the application provides a signal simulation source device for verification and test of a satellite navigation chip.
The application is realized by the following technical scheme:
a signal simulation source device for satellite navigation chip verification and test comprises a carrier wave generator, a code generator, a noise generator, an interference generator, a signal generation module and a register read-write module;
the signal generating module receives output signals of the carrier wave generator, the code generator, the noise generator and the interference generator, and generates a target intermediate frequency signal by combining register configuration of the register read-write module;
the register read-write module is electrically connected with the CPU subsystem through the APB bus.
The present application may be further configured in a preferred example to: in the signal generation module, the I/Q channel telegraph text and the I/Q channel pseudo code are subjected to pseudo code modulation, added with I/Q channel noise, interfered by the I/Q channel, and input into the carrier generator to output an I/Q channel intermediate frequency signal.
The present application may be further configured in a preferred example to: the I/Q channel noise is generated by a gaussian white noise generator.
The present application may be further configured in a preferred example to: the gaussian white noise generator generates a gaussian white noise sequence comprising,
the even distribution sequence generator is caused to generate an even distribution sequence;
the uniformly distributed sequence is converted into a gaussian distribution sequence by using an inverse cumulative distribution function.
The present application may be further configured in a preferred example to: when the uniformly distributed sequence generator is caused to generate a uniformly distributed sequence, including,
a pseudo-random sequence is generated using a linear feedback shift register, the structure of which includes,
wherein k represents the operation time; k. q, s are positive integers, and k > =s; a and C are 64-bit integers; the high k bit of C is 1, and the low (64-k) bit is 0;
modulo-2 accumulating the pseudo-random sequence to obtain the 64-bit uniformly distributed sequence, wherein the accumulating formula comprises,
wherein A is i,k Representing a pseudo-random sequence; u (U) k Representing a uniformly distributed sequence; n represents N pseudo-random sequences.
The present application may be further configured in a preferred example to: the uniformly distributed sequence is converted into a gaussian distribution sequence using an inverse cumulative distribution function, including,
converting the uniform distribution sequence into a Gaussian distribution sequence by adopting an inverse cumulative distribution function, wherein the expression of the inverse cumulative distribution function comprises,
wherein x is the input [0,1 ]]Uniformly distributed sequences, y is the output Gaussian distribution sequence, erf -1 () Is an inverse error function;
performing piecewise second-order polynomial interpolation fitting on the ICDF function value, and storing polynomial coefficients in a lookup table form in the register read-write module;
the lookup table is divided into 62 sections according to the power step of 2, and each section is uniformly divided into 4 sections;
obtaining each coefficient of the second-order polynomial from the lookup table according to the segment address of the uniform distribution sequence;
and calculating by adopting the inverse cumulative distribution function to obtain a corresponding 16-bit Gaussian distribution sequence.
The present application may be further configured in a preferred example to: the I/Q channel interference is generated by an interference generator except for spoofing interference.
The present application may be further configured in a preferred example to: the carrier generator carries out BPSK or double BPSK carrier modulation on the signals subjected to pseudo code modulation, noise addition and interference addition, and cuts bits of the modulation result and outputs the cut bits.
The present application may be further configured in a preferred example to: when the carrier generator carries out BPSK carrier modulation on the signal subjected to pseudo code modulation, noise addition and interference addition, a BPSK modulation signal model is adopted, and the expression of the BPSK modulation signal model comprises,
s(n)＝A s D I (n)C I (n)exp(j2πf c /f s n)+A n N(n)+A j J(n)
wherein n is the sampling point moment, I represents an I channel, A s 、A n 、A j Respectively a signal amplitude factor, a noise amplitude factor and an interference amplitude factor, f c Is the carrier frequency of the intermediate frequency signal, f s For the sampling rate, D (N) is telegraph text, C (N) is pseudocode, N (N) is noise, J (N) is the interfering signal sequence.
The present application may be further configured in a preferred example to: when the carrier generator carries out double BPSK carrier modulation on the signal subjected to pseudo code modulation, noise addition and interference addition, a double BPSK modulation signal model is adopted, the expression of the double BPSK modulation signal model comprises,
wherein n is the sampling point moment, I represents an I channel or a data channel, Q represents a Q channel or a pilot channel, A s 、A n 、A j Respectively a signal amplitude factor, a noise amplitude factor and an interference amplitude factor, f c Is the carrier frequency of the intermediate frequency signal, f s For the sampling rate, D (N) is the telegram, C (N) is the pseudocode, N (N) is the noise, J (N) is the interfering signal sequence, SC (N) is the subcarrier sequence.
To sum up, compared with the prior art, the beneficial effects brought by the technical scheme provided by the application at least include:
the signal generation module of the signal simulation source device receives output signals of the carrier generator, the code generator, the noise generator and the interference generator, and combines with register configuration of the register read-write module to generate a target intermediate frequency signal, so that the signal simulation source device can be integrated into a satellite navigation baseband chip or a radio frequency baseband integrated SoC chip, and simulate and generate a single-channel satellite navigation whole-system full-frequency point and a low-rail navigation enhanced intermediate frequency signal, can support flexible configuration of pseudo code types, modulation modes, doppler frequencies, text symbols, signal to noise ratios and various types of interference, can effectively support functional performance verification of a chip baseband signal processing module, and can check the design problem of the module, and can be used as a test screening means during chip mass production; the equipment such as purchase interference sources, medium-frequency data acquisition and playback, radio frequency front end board cards, power splitters, combiners, low-noise radio frequency connectors and the like are not needed, the environment establishment of verification test is simpler and more convenient, the verification and test efficiency is improved, and the acquisition cost and the test environment establishment cost of verification and test equipment are also reduced.
Drawings
Fig. 1 is a schematic diagram of an internal structure of a signal simulation source device for verifying and testing a satellite navigation chip according to an exemplary embodiment of the present application.
Fig. 2 is a schematic diagram of the working principle of a signal generating module of a signal simulation source device for verifying and testing a satellite navigation chip according to another exemplary embodiment of the present application.
Fig. 3 is a schematic diagram of the working principle of a noise generator of a signal simulation source device for verifying and testing a satellite navigation chip according to another exemplary embodiment of the present application.
Fig. 4 is a functional block diagram of a Gold code generator of a signal analog source device for satellite navigation chip verification and testing according to an exemplary embodiment of the present application.
Fig. 5 is a functional block diagram of an m-sequence code generator of a signal simulation source device for satellite navigation chip verification and testing according to an exemplary embodiment of the present application.
Fig. 6 is a block diagram of an overall structure of a signal simulation source device integrated into a satellite navigation chip for satellite navigation chip verification and testing according to an exemplary embodiment of the present application.
Fig. 7 is a verification test flow chart of a signal simulation source device for verifying and testing a satellite navigation chip according to an exemplary embodiment of the present application.
Detailed Description
The present embodiment is merely illustrative of the present application and is not intended to be limiting, and those skilled in the art, after having read the present specification, may make modifications to the present embodiment without creative contribution as required, but is protected by patent laws within the scope of the claims of the present application.
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In addition, the term "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In this context, unless otherwise specified, the term "/" generally indicates that the associated object is an "or" relationship.
The current international satellite navigation system mainly includes global satellite navigation systems such as BDS (BeiDou Navigation Satellite System, beidou satellite navigation system), GPS (Global Position System, global positioning system) in the united states, galileo in europe, GLONASS (Global Navigation Satellite System, global satellite navigation system) in russia, and regional satellite navigation systems such as QZSS (Quasi-Zenith Satellite System, quasi zenith satellite system) in japan, IRNSS (Indian Regional Navigational Satellite System, indian regional navigation satellite system) in india. The high-performance high-precision satellite navigation chip generally supports full-system full-frequency point signal receiving and is used for high-precision positioning, orientation, gesture determination, time service and other scenes such as automatic driving, unmanned aerial vehicle, electric power telecommunication time service, surveying and mapping and the like. In recent years, the low-orbit satellite system is in competitive construction, the defects that satellite navigation signals are easy to be blocked and interfered can be overcome by virtue of the characteristics of large satellite quantity, strong signal landing power, quick geometric configuration change and the like, and the availability and positioning performance of the satellite navigation system are improved, so that the receiving and processing functions of the low-orbit navigation enhancement signals are also important requirements of a high-performance satellite navigation chip.
In the design stage of the satellite navigation chip, two chip verification and test means, namely UVM (Universal Verification Methodology ) simulation verification and FPGA (Field Programmable Gate Array, programmable gate array) prototype verification, are usually adopted, and the two modes both require the assistance of a signal simulation source.
For UVM simulation verification, recording and converting a combined radio frequency signal of a satellite navigation signal simulator and an interference source into an intermediate frequency digital signal file by using intermediate frequency signal acquisition equipment, and providing the intermediate frequency digital signal file for an algorithm model and digital logic to perform functional simulation and comparison verification; for FPGA prototype verification, a radio frequency front end board needs to be designed, radio frequency signals of a processing signal analog source and an interference source are received in real time, and digital intermediate frequency signals are provided for the FPGA to verify chip baseband processing logic. However, the environment construction work of the UVM verification scheme is complex, a plurality of devices need to be purchased or developed for cooperation, attenuation of each signal link hardware needs to be calibrated when index tests such as sensitivity and anti-interference of a satellite navigation chip are performed, so that the cost of hardware devices and manual operation is high, and in order to traverse the chip function and touch the chip performance when UVM simulation verification is performed, a signal source test scene needs to be replaced or signal configuration needs to be changed, recording signals are repeatedly acquired and intermediate frequency files are derived, and the workload is extremely high and the flexibility is poor; and the reproducibility of signals is poor when the FPGA is verified, so that the problems of grasping the design details of the problem and checking the design details are not facilitated, the boundary test conditions are difficult to traverse, and the like are solved.
In addition, in the chip batch test stage, the traditional scheme generally needs to divide the combined signals of the satellite navigation signal analog source and the interference source into multiple paths to be output to each chip test platform, the key function performance test of one batch of chips is completed according to the test flow set in advance, the next batch of chips are replaced after the test is completed, the automatic test flow efficiency of the signal analog source, the fault-free running time of the test system, the number of the signal sources and the like limit the test efficiency, and the system is limited by the non-ideal physical characteristics of a signal link, so that the test results of each chip are difficult to uniformly and accurately measure. The existing signal analog source devices are mostly independent of satellite navigation chips or receivers.
Therefore, the signal simulation source device for verifying and testing the satellite navigation Chip can be integrated into a satellite navigation baseband Chip or a radio frequency baseband integrated System on Chip (SoC) Chip, replaces equipment such as a satellite navigation signal simulation source, an interference source, intermediate frequency data acquisition and playback, a radio frequency front end board card and the like required in the traditional Chip verification and testing process, and a power divider, a combiner, a low-noise amplifier and other radio frequency connectors, so as to simulate and generate a single-channel satellite navigation full-System full-frequency point and a low-rail navigation enhanced intermediate frequency signal, support flexible configuration of pseudo code types, modulation modes, doppler frequencies, text symbols, signal to noise ratios and various types of interference, effectively support functional performance verification of a Chip baseband signal processing module, solve the problem of module design, can be used as a test screening means in Chip mass production, greatly improve the efficiency of Chip design verification and mass production test, reduce the purchase cost of special equipment and verification test environment, reduce the purchase cost of equipment and maintenance cost, and labor hour cost, simplify the signal parameter, simplify the verification test flow, high verification and test efficiency, and high consistency, and high reproducibility.
Embodiments of the present application are described in further detail below with reference to the drawings attached hereto.
Referring to fig. 1, an embodiment of the present application provides a signal analog source device for satellite navigation chip verification and test, which includes a carrier generator, a code generator, a noise generator, an interference generator, a signal generating module, and a register read-write module. The signal generating module receives output signals of the carrier generator, the code generator, the noise generator and the interference generator, and generates a target intermediate frequency signal by combining register configuration of the register read-write module.
The signal generating module is a top-level module of the signal analog source device (also called signal analog source IP), acquires register configuration and telegraph text, pseudo code, noise, interference generated by each module, completes operations such as time counting, pseudo code modulation of telegraph text symbols, carrier modulation, noise adding, interference adding and the like, and finally generates a required target intermediate frequency signal.
The register read-write module is electrically connected with the CPU subsystem through an APB (Advanced Peripheral Bus ) bus to the outside and is responsible for register configuration and read operation of each sub-module.
Referring to fig. 2, in the signal generating module, the I/Q channel text and the I/Q channel pseudo code are subjected to pseudo code modulation, added with I/Q channel noise, and input into the carrier generator after I/Q channel interference, and output an I/Q channel intermediate frequency signal.
Specifically, the signal generation module updates the carrier amplitude and pseudo-code chips with a carrier NCO (Numerically Controlled Oscillator ) and a code NCO, wherein the code NCO overflow count is used to provide a standard time count, such as a half-chip count, a millisecond count, a symbol count, etc.
The I/Q channel telegraph text is configured through a register, takes a value according to the symbol count, and modulates the pseudo code on the basis of the telegraph text symbol. The pseudo code is generated by a universal code generator, and supports m sequences (such as GPS L2C signals and GLONASS G1/G2 signals), gold codes (such as BDS B11 and GPS L1CA signals), weil codes (such as BDS B1C and GPS L1C signals) and storage codes (such as Galileo E1OS signals). For BOC pseudo code modulation (such as BDS B1C, GPS L1C and Galileo E1OS signals) signals, half-chip subcarrier modulation is carried out on the pseudo code; for time division multiplexing pseudo code modulation (such as GPS L2C and low-orbit MCSK signals), generating two groups of code sequences of I/Q channel pseudo codes for time division multiplexing; for BPSK carrier modulated signals (e.g., BDS B1I and GPS L1C/A signals), only I-channel pseudocode needs to be generated; for dual BPSK carrier modulated signals (e.g., BDS B2a and GPS L5 signals), I/Q channel pseudocode is generated for the data/pilot channel.
The I/Q channel noise is generated by a noise generator and the enabling mode is selected according to the carrier modulation mode.
The I/Q channel interference is generated by an interference generator except deception interference, and comprises interference such as narrow band, broadband, sweep frequency, pulse and the like, and the interference bandwidth is controlled by an interference code rate and an FIR (Finite Impulse Response ) filter; the forwarding deception jamming is formed by adding delay of control signals of the top signal generation module.
Referring to FIG. 3, in one embodiment, the I/Q channel noise is generated by a Gaussian white noise generator. A Gaussian white noise sequence is generated by means of a Gaussian white noise generator and is used for simulating additive Gaussian white noise introduced in the real signal transmission process, and the carrier-to-noise ratio of the signal is controlled by configuring amplitude factors of the signal and the noise.
When the gaussian white noise generator generates a gaussian white noise sequence, comprising,
the even distribution sequence generator is caused to generate an even distribution sequence;
the uniformly distributed sequence is converted into a gaussian distribution sequence by using an inverse cumulative distribution function.
In one embodiment, the method includes, when the uniformly distributed sequence generator is caused to generate a uniformly distributed sequence, including,
a pseudo-random sequence is generated using a linear feedback shift register, the structure of which includes,
wherein k represents the operation time; k. q, s are positive integers, and k > =s; a and C are 64-bit integers; the high k bit of C is 1, and the low (64-k) bit is 0;
modulo-2 accumulating the pseudo-random sequence to obtain the 64-bit uniformly distributed sequence, wherein the accumulating formula comprises,
wherein A is i,k Representing a pseudo-random sequence; u (U) k Representing a uniformly distributed sequence; n represents N pseudo-random sequences.
In one embodiment, the uniform distribution sequence is converted to a gaussian distribution sequence using an inverse cumulative distribution function, including,
converting the uniform distribution sequence into a Gaussian distribution sequence by adopting an inverse cumulative distribution function, wherein the expression of the inverse cumulative distribution function comprises,
wherein x is the input [0,1 ]]Uniformly distributed sequences, y is the output Gaussian distribution sequence, erf -1 () Is an inverse error function;
performing piecewise second-order polynomial interpolation fitting on the ICDF function value, and storing polynomial coefficients in a lookup table form in the register read-write module;
the lookup table is divided into 62 sections according to the power step of 2, and each section is uniformly divided into 4 sections;
obtaining each coefficient of the second-order polynomial from the lookup table according to the segment address of the uniform distribution sequence;
and calculating by adopting the inverse cumulative distribution function to obtain a corresponding 16-bit Gaussian distribution sequence.
The sequence U is uniformly distributed from 64 bits according to the following method k Obtaining ICDF function input x k ：
x k ＝{U k [0],U k [3:17]}
The ICDF function lookup table address is calculated as follows:
Addr k ＝{LZD(U k [63:3]),U k [2:1]}
calculating a second order polynomial interpolation output y of the ICDF function according to the following formula k I.e. the desired gaussian white noise sequence.
The period of the noise random sequence generated by the Gaussian white noise generator is long, and the random performance distribution is excellent; and the ICDF algorithm is adopted to ensure that the normal distribution characteristic of the noise random sequence is good, and the lookup table is designed to replace complex operation, so that the logic resource occupation of the system is small, and the carrier-to-noise ratio can be matched.
In one embodiment, the code generator supports three types of Weil codes, store codes, and generate codes (m-sequences, gold codes).
For Weil codes, legendre sequences are generated in advance and stored in a memory to serve as a lookup table, and the Legendre sequences are shifted and added according to the Weil code generation method of Beidou B1C and GPS L1C signals, and fixed sequences are circularly intercepted or inserted.
For the storage code, a 1KB SRAM space is reserved, and a single-star Galileo E1OS signal and other extension signals can be supported.
For the generated codes, a Gold universal code generator and an m-sequence universal code generator are respectively adopted to generate the needed pseudo code sequences, so that Gold codes with any shift register not exceeding 16 bits and m-sequences with any shift register not exceeding 32 bits can be supported.
Referring to fig. 4, in the gold code mode, G1 and G2 generating polynomials of the code generator and the shift register state are 16 bits, the pseudo code of the designated satellite can be generated by configuring the generating polynomial coefficient and the initial state of the register, and for the signal (such as BDS B3I and GPS L5) requiring shortening of the G1 sequence, the shift register state reset can be triggered by the chip count or the current state of the register. Taking BDS B3I signal pseudo code as an example, the generator polynomials of G1 and G2 are:
the initial phase of the G1 shift register is "1111111111111", the initial phase of the G2 shift register is formed by performing different shifting times on "1111111111111", and different initial phases correspond to different satellites. The G1/G2 polynomials may be different for different frequency point signals.
The code sequence generated by G1 is truncated by 1 chip to become G1 sequence with period of 8190 chips, or the initial phase of the shift register is set when the phase of the G1 shift register is judged to be '1111111111100'.
Referring to fig. 5, in the m-sequence mode, the code generator has a generator polynomial with a shift register state of 32 bits, which can support m-sequence generation of a 32-bit shift register (a GPS L2C signal pseudocode requires a 27-bit shift register). Taking the GPS L2C signal as an example, the generator polynomial is:
G(X)＝1+X 3 +X 4 +X 5 +X 6 +X 9 +X 11 +X 13 +X 16 +X 19 +X 21 +X 24 +X 27
the initial phase of the 27 bit shift register is determined by the satellite number.
The code generator can support the generation of all satellite navigation signals and low-orbit navigation enhancement signal pseudo codes in the current market, and the generated code has flexible and configurable generating polynomial and register phase, so that the applicability is stronger.
In one embodiment, the interference generator uses the intermediate frequency signal modulated with the Gold code pseudo-random sequence as the satellite interference signal, which is used for simulating signal interference of different bandwidths such as single frequency, narrow band, broadband and the like in the real environment, and the interference signal ratio can be controlled by configuring the amplitude factors of the signal and the interference so as to verify the anti-interference function and performance of the satellite navigation chip.
The interference Gold code is selected to avoid sequences being used by the satellites in the sky, such as sequences corresponding to the GPS L1C/A PRN 33.
The bandwidth of the interference signal is controlled by configuring a frequency control word of an interference Gold code NCO, the bandwidth of the interference signal is set according to 1/10 of the bandwidth of the useful signal, the bandwidth of the interference signal is 2 times of the code rate, the bandwidth is used for verifying the narrow-band anti-interference function of the satellite navigation chip, the interference Gold code rate is configured through a register, and an FIR filter is connected to the output end of the interference signal so as to optimize bandwidth control. For single-frequency interference, the Gold code sequence does not need to be modulated, and pure carrier waves can be directly generated.
For pulse interference and sweep frequency interference, the interference generator is only responsible for generating an interference sequence with a specified bandwidth, and the signal generating module controls the duty ratio and the intermediate frequency of an interference signal during carrier modulation.
For the forwarding of spoofing interference, the interference generator does not need to generate an interference sequence, and the signal generating module performs delay addition of multiple real signals.
The interference generator supports multiple interference types, wherein the interference types comprise narrow bands, broadband, pulses, frequency sweeping and deception interference, and the interference-to-noise ratio is configurable and flexible to use.
In one embodiment, the carrier generator performs BPSK or double BPSK carrier modulation on the pseudo-code modulated, noise-added, and interference-added signals, and truncates the modulation result and outputs the truncated modulation result.
Specifically, when the carrier wave generator carries out BPSK carrier wave modulation on the signal subjected to pseudo code modulation, noise addition and interference addition, a BPSK modulation signal model is adopted, and the expression of the BPSK modulation signal model comprises,
s(n)＝A s D I (n)C I (n)exp(j2πf c /f s n)+A n N(n)+A j J(n)
wherein n is the sampling point moment, I represents an I channel, A s 、A n 、A j Respectively a signal amplitude factor, a noise amplitude factor and an interference amplitude factor, f c Is the carrier frequency of the intermediate frequency signal, f s For the sampling rate, D (N) is telegraph text, C (N) is pseudocode, N (N) is noise, J (N) is the interfering signal sequence.
When the carrier generator carries out double BPSK carrier modulation on the signal subjected to pseudo code modulation, noise addition and interference addition, a double BPSK modulation signal model is adopted, and the expression of the double BPSK modulation signal model comprises,
wherein n is the sampling point moment, I represents an I channel or a data channel, Q represents a Q channel or a pilot channel, A s 、A n 、A j Respectively a signal amplitude factor, a noise amplitude factor and an interference amplitude factor, f c Is the carrier frequency of the intermediate frequency signal, f s For the sampling rate, D (N) is the telegram, C (N) is the pseudocode, N (N) is the noise, J (N) is the interfering signal sequence, SC (N) is the subcarrier sequence.
The carrier generator supports BOC and MCSK pseudo code modulation, supports BPSK and double-path BPSK carrier modulation, can generate satellite navigation whole-system whole-frequency point signals, low-orbit navigation enhancement signals and other more new signal system expansion, and is flexible in configuration.
Referring to fig. 6, the satellite navigation chip architecture includes a radio frequency subsystem, a signal analog source IP, a baseband subsystem, a CPU subsystem (Central Processing Unit ), a storage subsystem, a peripheral subsystem, and a bus unit, etc. The signal analog source IP and the radio frequency subsystem both output intermediate frequency digital signals to the baseband subsystem for selection by the baseband signal processing module. The signal simulation source IP is generated by a signal simulation source device for satellite navigation chip verification and test.
The signal simulation source device with powerful functions and less occupied resources can be integrated in a satellite navigation chip, replaces special equipment such as a traditional satellite signal simulator and an interference source, and is used as an efficient on-chip verification and test means.
Referring to fig. 7, a verification test procedure of a signal simulation source device for satellite navigation chip verification and test includes,
(1) Storing reference operation results of key nodes
In the UVM simulation verification stage, a signal simulation and baseband signal processing flow is operated through an algorithm model of a chip, and operation results of key nodes are stored as files, such as intermediate frequency sampling data output of a signal simulation source and node data on a satellite navigation chip baseband signal processing link, including but not limited to output of an interference detection and suppression module, output of a data preprocessing module, acquisition results, tracking results and the like;
in the stage of FPGA prototype verification and chip batch test, the CPU firmware initializes the reference operation result generated in the simulation verification stage into the on-chip memory such as SRAM or DDR of the chip.
(2) Configuring baseband signal processing module
The CPU firmware configures registers of the baseband signal processing modules such as capturing, tracking, data preprocessing, anti-interference and the like through a bus, and selects an intermediate frequency signal data source as the output of a signal simulation source IP.
(3) Configuring signal analog source IP
And finally, the CPU firmware configures a register of the signal simulation source IP and enables data output, so that the consistency of the starting operation time is ensured.
(4) Reading and comparing operation results
And (3) reading the real-time operation result of the key node in the step (1) at a specific moment, such as in a timer interrupt, capturing interrupt and tracking interrupt service subprogram, comparing with a stored reference operation result, counting the comparison result in a certain time, and judging whether the verification or test is passed.
In an embodiment, a mode of storing intermediate frequency sampling signals in a chip can be used for replacing a real-time signal analog source, namely intermediate frequency sampling points of one code period are stored in SRAM (Static Random Access Memory ) in the chip at a lower sampling rate, and a baseband signal processing module circularly reads the intermediate frequency sampling signals for processing, so that the method has the advantages of saving purchase cost of a large number of special equipment, verifying the construction cost of a test environment and having strong data reproducibility.
Through verification, the satellite navigation signal and the low-orbit navigation enhancement signal system mainly cover the aspects of pseudo code type, pseudo code modulation mode, carrier debugging mode and the like at the signal level, and the system types corresponding to the signal frequency points are shown in the following table 1.
TABLE 1
The signal simulation source device can support all the signal systems and has strong universality.
The signal simulation source generated by the method can traverse various code patterns and modulation modes of satellite navigation and low-orbit satellite signals, supports noise and interference, and is convenient for verification and test of a baseband signal processing module, and the main characteristics are as follows:
supporting single-frequency point intermediate frequency signal simulation of a single satellite;
the intermediate frequency signal is in a complex form, and the data bit width and the format are matched;
the I/Q channel message can be configured through a register;
intermediate frequency and Doppler can be matched;
the pseudo code supports three types of generating codes (m sequence, gold code), weil code and storage code, wherein the generating codes are matched with an I/Q channel generating polynomial;
supporting BPSK (Binary Phase Shift Keying, binary frequency shift keying), two-way BPSK carrier modulation,
supporting BOC (Binary Offset Carrier ), MCSK (Multiplex CodeShift Keying, complex code shift keying) pseudo code modulation;
the support signal is added with Gaussian white noise, and the carrier-to-noise ratio is configurable;
signal plus interference is supported, and the interference types comprise narrow band, pulse and wide band, and the interference-to-noise ratio is configurable.
In summary, the signal generating module of the signal simulation source device for verifying and testing the satellite navigation chip receives the output signals of the carrier wave generator, the code generator, the noise generator and the interference generator, and combines the register configuration of the register read-write module to generate the target intermediate frequency signal, so that the signal simulation source device can be integrated into the satellite navigation baseband chip or the radio frequency baseband integrated SoC chip to simulate and generate the single-channel satellite navigation whole system full-frequency point and the low-orbit navigation enhanced intermediate frequency signal, can support flexible configuration of pseudo code types, modulation modes, doppler frequencies, text symbols, signal to noise ratios and various types of interference, can effectively support functional performance verification of the chip baseband signal processing module, and is used as a test screening means in chip batch production; the equipment such as purchase interference sources, medium-frequency data acquisition and playback, radio frequency front end board cards, power splitters, combiners, low-noise radio frequency connectors and the like are not needed, the environment establishment of verification test is simpler and more convenient, the verification and test efficiency is improved, and the acquisition cost and the test environment establishment cost of verification and test equipment are also reduced.
The signal simulation source IP is directly integrated into the chip, and the verification and the test of the satellite navigation chip can bring the following advantages:
(1) The verification test process does not need the support of special equipment such as a satellite navigation signal analog source, an interference source, an intermediate frequency signal acquisition device, a radio frequency front end board card, a radio frequency connector and the like, so that a large amount of equipment acquisition and maintenance cost and verification test environment construction cost can be saved;
(2) The system has the advantages that the system is flexible and configurable in user dynamics, signal to noise ratio, interference type and interference signal ratio, can conveniently traverse verification test scenes, can easily test baseband functional performance indexes such as signal receiving, capturing and tracking time consumption, capturing and tracking sensitivity, interference type detection, compression interference resistance, deception interference resistance and the like, has complete capability of replacing a special satellite navigation signal simulator and an interference source in the verification and test process of a satellite navigation chip, and is quicker and simpler in test case establishment and test result evaluation;
(3) The signal pseudo code and the modulation mode are flexible and configurable, and the low-rail navigation enhancement or the support of other new signal systems can be conveniently configured and realized, and the signal expansion and upgrading of the traditional signal analog source are high in cost;
(4) The method is easy to generate ideal signals without noise, interference and Doppler, and is more beneficial to the design and problem investigation of an auxiliary baseband module compared with the traditional signal analog source;
(5) The generated intermediate frequency signal data has no randomness, can be stably reproduced, and the running results of each baseband processing module can be stably reproduced, so that the running results can be completely compared with the priori results one by one on an FPGA prototype platform and a chip test platform, which cannot be achieved by the traditional signal simulation source;
(6) The automatic test flow can be flexibly customized by designing the processor firmware, the operation results can be accurately compared, the sieve sheet standard is unified and quantifiable, the sieve sheet accuracy is high, and compared with the traditional scheme, unmanned participation can be achieved, and the time consumption is shorter.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the system is divided into different functional units or modules to perform all or part of the above-described functions.
Claims (10)
1. The signal simulation source device for the verification and the test of the satellite navigation chip is characterized by comprising a carrier wave generator, a code generator, a noise generator, an interference generator, a signal generation module and a register read-write module;
the signal generating module receives output signals of the carrier wave generator, the code generator, the noise generator and the interference generator, and generates a target intermediate frequency signal by combining register configuration of the register read-write module;
the register read-write module is electrically connected with the CPU subsystem through the APB bus.
2. The signal simulation source device for satellite navigation chip verification and test according to claim 1, wherein in the signal generation module, the I/Q channel message and the I/Q channel pseudo code are subjected to pseudo code modulation, added with I/Q channel noise, interfered by the I/Q channel, and input into the carrier generator to output an I/Q channel intermediate frequency signal.
3. The signal simulation source device for satellite navigation chip verification and testing of claim 2, wherein the I/Q channel noise is generated by a gaussian white noise generator.
4. A signal simulation source device for satellite navigation chip verification and test according to claim 3, wherein the Gaussian white noise generator generates a Gaussian white noise sequence comprising,
the even distribution sequence generator is caused to generate an even distribution sequence;
the uniformly distributed sequence is converted into a gaussian distribution sequence by using an inverse cumulative distribution function.
5. The signal simulation source device for satellite navigation chip verification and test of claim 4, wherein the uniformly distributed sequence generator is configured to generate the uniformly distributed sequence, comprising,
a pseudo-random sequence is generated using a linear feedback shift register, the structure of which includes,
wherein k represents the operation time; k. q, s are positive integers, and k > =s; a and C are 64-bit integers; the high k bit of C is 1, and the low (64-k) bit is 0;
modulo-2 accumulating the pseudo-random sequence to obtain the 64-bit uniformly distributed sequence, wherein the accumulating formula comprises,
wherein A is i,k Representing a pseudo-random sequence; u (U) k Representing a uniformly distributed sequence; n represents N pseudo-random sequences.
6. The signal simulation source device for satellite navigation chip verification and test of claim 4, wherein the uniformly distributed sequence is converted to a gaussian distribution sequence using an inverse cumulative distribution function comprising,
converting the uniform distribution sequence into a Gaussian distribution sequence by adopting an inverse cumulative distribution function, wherein the expression of the inverse cumulative distribution function comprises,
wherein x is the input [0,1 ]]Uniformly distributed sequences, y is the output Gaussian distribution sequence, erf -1 () Is an inverse error function;
performing piecewise second-order polynomial interpolation fitting on the ICDF function value, and storing polynomial coefficients in a lookup table form in the register read-write module;
the lookup table is divided into 62 sections according to the power step of 2, and each section is uniformly divided into 4 sections;
obtaining each coefficient of the second-order polynomial from the lookup table according to the segment address of the uniform distribution sequence;
and calculating by adopting the inverse cumulative distribution function to obtain a corresponding 16-bit Gaussian distribution sequence.
7. The signal simulation source device for satellite navigation chip verification and testing of claim 2, wherein the I/Q channel interference is generated by an interference generator except for spoofing interference.
8. The signal simulation source device for satellite navigation chip verification and test according to claim 1, wherein the carrier generator performs BPSK or double BPSK carrier modulation on the signal after pseudo code modulation, noise addition and interference addition, and truncates and outputs the modulation result.
9. The signal simulation source device for satellite navigation chip verification and test according to claim 8, wherein the carrier generator applies a BPSK modulation signal model when performing BPSK carrier modulation on the signal subjected to pseudo code modulation, noise addition and interference addition, and the expression of the BPSK modulation signal model includes,
s(n)＝A s D I (n)C I (n)exp(j2πf c /f s n)+A n N(n)+A j J(n)
wherein n is the sampling point moment, I represents an I channel, A s 、A n 、A j Respectively a signal amplitude factor, a noise amplitude factor and an interference amplitude factor, f c Is the carrier frequency of the intermediate frequency signal, f s For the sampling rate, D (N) is telegraph text, C (N) is pseudocode, N (N) is noise, J (N) is the interfering signal sequence.
10. The signal simulation source device for satellite navigation chip verification and test according to claim 8, wherein the carrier generator performs double BPSK carrier modulation on the signal subjected to pseudo code modulation, noise addition and interference addition, a double BPSK modulation signal model is adopted, and the expression of the double BPSK modulation signal model includes,
wherein n is the sampling point moment, I represents an I channel or a data channel, Q represents a Q channel or a pilot channel, A s 、A n 、A j Respectively a signal amplitude factor, a noise amplitude factor and an interference amplitude factor, f c Is the carrier frequency of the intermediate frequency signal, f s For the sampling rate, D (N) is the telegram, C (N) is the pseudocode, N (N) is the noise, J (N) is the interfering signal sequence, SC (N) is the subcarrier sequence.
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