CN117613048A - Method and system for constructing interconnection information of wafer substrate of system on chip - Google Patents

Abstract

The present invention relates to the technical field of on-chip system design, and in particular to a method and system for constructing interconnection information of an on-chip system wafer substrate. The connection points are divided into corresponding connection point types; the EDA tool is used to comprehensively process the required chip connection points to obtain the chip interconnection information file; the top-level input and output ports of the interconnection information are automatically set through scripts so that the connection point types Each connection point in the first corresponds to the micro-bump on the top layer of the wafer substrate or the C4 bump on the bottom layer; based on the chip interconnection information file and the top-level input and output ports, the required mounting chips are automatically instantiated through scripts to obtain on-wafer System wafer substrate interconnect information. The invention automatically sorts out the classification of bump map information of each core particle connection through a script, simplifies the complexity of the design of the interconnection information file of the wafer substrate of the on-wafer system, improves its generation efficiency and accuracy, and can be suitable for large-scale integration and high density. Interconnected on-wafer system wafer substrate design.

Description

On-chip system wafer substrate interconnection information construction method and system

Technical field

The present invention relates to the technical field of on-wafer systems, and in particular to a method and system for constructing interconnection information on a wafer substrate of an on-wafer system.

Background technique

System on a Chip (SoC) is an embeddable, full-featured computer that integrates basic hardware facilities such as processor, memory, storage, and peripheral interfaces. Its core is a chip. The chip includes the following core components: Processor core , high-speed bus, on-chip memory, peripheral interface, interrupt controller, clock system, power management system, debugging interface, etc. On-wafer systems are based on integrated circuit technology (ASIC). Functions that originally required interconnection of several chips on multiple printed circuit boards are interconnected on one or more wafers through high-density integration, making it possible The equipment is more compact and integrated, and also more effectively optimizes system performance and power consumption, and can be widely used in supercomputing, digital signal processing and other fields.

2.5D interposer integration technology mainly integrates ASIC or other control processing chips plus HBM memory chips. The steps for generating the substrate interconnection information file (Verilog format or CSV format) required for the substrate physical design are as follows: 1 . Directly interconnect the HBM controller interface signals and HBM core chip corresponding signals in the substrate interconnection information file. 2. The power supply and other IO signals of the core chips are defined through the port signals in the substrate top-level interconnection information file, so as to The substrate is designed as micro bump or C4 bump. It can be applied to the physical design of 2.5D interposer substrates with a single interface (HBM interface) and small integration scale (usually one ASIC plus two HBMs). The large integration scale of on-chip systems (hundreds of chips), many types of chips, and diverse chip interconnect interfaces (high-speed interfaces, storage interfaces) make it difficult to generate the substrate interconnect information files required for the current 2.5Dinterposer substrate design. The method is no longer applicable to the design of wafer substrate interconnection information file generation for systems on wafers.

Contents of the invention

To this end, the present invention provides a method and system for constructing interconnection information of on-chip system wafer substrates to solve the problem that the generation of substrate interconnection information files required for existing 2.5Dinterposer substrate design is not suitable for on-wafer system wafer substrate design. questions that can guide the physical design of silicon interposers in wafer substrates or advanced packaging.

According to the design scheme provided by the present invention, on the one hand, a method for constructing interconnection information on a system-on-chip wafer substrate is provided, including:

Obtain the connection point list of the on-wafer system core particles, and divide the connection points of each core particle in the connection point list into corresponding connection point types. Among them, the connection point types include: connection point types that lead signals out of the wafer substrate 1. Connection point type two and other types of connection point type three for signal interconnection on the wafer substrate;

Use EDA tools to process the required mounting chip connection points to obtain the chip interconnection information file; set the top-level input and output ports of the interconnection information based on each connection point of connection point type one, so that each connection point in connection point type one Corresponding to the micro bumps on the top layer of the wafer substrate or the C4 bumps on the bottom layer;

Instantiate the required mounting die based on the die interconnection information file and the top-level input and output ports to obtain the on-wafer system wafer substrate interconnection information.

As the method for constructing the interconnection information of the on-chip system wafer substrate of the present invention, further, a list of connection points of the on-chip system core particles is obtained, including:

List of connection points for all types of die mounted on Jingyuan substrate.

As the on-wafer system wafer substrate interconnection information construction method of the present invention, further, the second connection point type includes at least a chip power connection point, a ground connection point and an IO connection point.

As the method for constructing interconnection information of the wafer substrate of the on-chip system of the present invention, further, dividing each core particle connection point in the connection point list into the corresponding connection point type also includes:

Set the core particle connection point naming and/or the connection point connection naming according to the preset mapping rules, and use the naming to represent the connection mapping relationship of each connection point of the core particle.

As the method for constructing the interconnection information of the wafer substrate of the on-chip system of the present invention, further, the EDA tool is used to process the required mounting die connection points, and the die interconnection information file is obtained, which also includes:

The correctness of the wafer substrate chip connection relationship is checked based on the chip interconnection relationship. The correctness check includes DRC inspection using EDA tools and manual inspection using the visual schematic window.

Further, the present invention also provides an on-chip system wafer substrate interconnection information construction system, including: an information acquisition module, an information processing module and an instantiation module, wherein,

The information acquisition module is used to obtain the connection point list of the on-wafer system core particles, and divide the connection points of each core particle in the connection point list into corresponding connection point types. Among them, the connection point types include: leading the signal out of the wafer substrate Connection point type one, connection point type two for signal interconnection on the wafer substrate and other types of connection point type three;

The information processing module is used to use EDA tools to process the required mounting chip connection points and obtain the chip interconnection information file; set the top-level input and output ports of the interconnection information based on each connection point of connection point type 1 to enable the connection Each connection point in point type one corresponds to the micro-bumps on the top layer of the wafer substrate or the C4 bumps on the bottom layer;

The instantiation module is used to instantiate the required mounting die based on the die interconnection information file and the top-level input and output ports to obtain the on-wafer system wafer substrate interconnection information.

Beneficial effects of the present invention:

This invention simplifies the complexity of the interconnection information file design of the wafer substrate of the on-chip system by classifying and combing the bump map information of each core chip connection, and combines EDA tools to realize the generation of interconnection information between large-scale mounting core chips, and Use the DRC of the EDA tool and the visualized schematic diagram to check the interconnection between the die, which facilitates the inspection and maintenance of the interconnection between the die, ensures the correctness of the final wafer substrate interconnection information file design, and provides the basis for the wafer substrate interconnection It provides a basis for design sign-off of connection information files and can be applied to the design of wafer substrates for large-scale integration and high-density interconnection on-wafer systems.

Picture description:

Figure 1 is a schematic diagram of the process of constructing interconnection information on the wafer substrate of the on-wafer system in the embodiment.

Detailed ways:

In order to make the purpose, technical solutions and advantages of the present invention clearer and clearer, the present invention will be described in further detail below in conjunction with the accompanying drawings and technical solutions.

The physical design of the traditional 2.5D silicon substrate requires the import of the connection information file of the silicon substrate. However, the traditional connection information file generation method cannot effectively support the design and inspection of interconnection relationships at the interconnection scale of hundreds of chips for on-wafer systems. To this end, embodiments of the present invention provide a method for constructing interconnection information on a system-on-chip wafer substrate, as shown in Figure 1, which includes the following content:

S101. Obtain the connection point list of the on-wafer system core particles, and divide the connection points of each core particle in the connection point list into corresponding connection point types. The connection point types include: connection point types that lead signals out of the wafer substrate. 1. Connection point type 2 for signal interconnection on the wafer substrate and other types of connection point type 3.

Among them, a list of connection points of all types of core chips mounted on the wafer substrate of the on-wafer system is obtained. The second type of connection point includes at least a core power connection point, a ground connection point and an IO connection point.

Based on the bump map (BumpMap) information of each chip in the DSP, DDR, and switching chip of the on-chip system, the bump list of the chip mounted on the chip is automatically sorted through a script according to the interface and IO function of the mounted chip, and the bump list is obtained. The die needs to lead out signals outside the wafer substrate, signals for interconnection on the wafer substrate, and other signals.

According to the preset mapping rules, the core particle connection point naming and/or the connection point connection naming can be automatically set through the script, and the naming can be used to represent the connection mapping relationship of each connection point of the core particle. Among them, the mapping rules can be combined with the type of core particles, the number of core particles and the connection relationship between core particles for mapping. For example, DSPn (nth DSP) is mounted on the wafer substrate and the corresponding bump name is prefixed with DSPn_. Similarly, DDR and switching chips can be processed in the same way. The network name of the interconnection line between cores can be set according to the mapping rules. For example, the network name of the line connecting DSPn_DD to DDRn_TT can be set to DSPn_DD_DDRn_TT. This network name can clearly represent the interconnection device and its corresponding network. name.

S102. Use the EDA tool to process the required mounting chip connection points and obtain the chip interconnection information file; each connection point based on connection point type one is automatically set as the top-level input and output port of the interconnection information through the script, so that the connection points Each connection point in Type 1 corresponds to the micro-bumps on the top layer of the wafer substrate or the C4 bumps on the bottom layer.

The EDA tool supports multiple styles of interconnection information output. The EDA tool can automatically generate the schematic symbols of the chip according to the signals that the chip needs to interconnect on the wafer substrate. By establishing the principles of each chip placement The diagram symbols call the core particles, and complete the interconnection according to the design requirements and based on the naming of the core particles and the core particle connections, so that the interconnection signals are clear, convenient for the core particle interconnection, and at the same time, it is convenient to check the core particle interconnection relationship; the generation principle After drawing, compare it with the bump information of the required die interconnection on the wafer substrate at the carding place. Software can be used to export the pin information of the die schematic symbols in CSV format, and then use scripts and die The bump information can be automatically compared, or the sorted signal classification can be used for automatic comparison to ensure that the symbols of the core particles produced do not miss bumps or add extra bumps. Check the interconnection of the schematic diagram, and check the correctness of the wafer substrate die connection relationship based on the die interconnection relationship to ensure that the interconnection design is correct. The correctness check includes automated DRC check using EDA comprehensive tools and manual inspection utilizing the visual schematic window. Export inter-die interconnection information from EDA tools. The input and output ports on the top layer of the wafer substrate interconnection information file are set according to the type of signal connection points that need to be led out to the outside of the wafer substrate, so that the signals that the on-wafer system wafer substrate needs to be led out to the outside (including power, ground, IO, etc.), this part of the signal is directly set as a port signal in the top module of the substrate interconnection information file, so that during physical design, this part corresponds to the micro bump on the top layer of the wafer substrate and the C4 bump on the bottom layer.

S103. Based on the chip interconnection information file and the top-level input and output ports, the required mounting chips are automatically instantiated through script mapping to obtain the on-wafer system wafer substrate interconnection information.

Instantiate each mounted device in the wafer substrate interconnection information file, and instantiate the exported inter-die interconnection information and top-level input and output port information to the corresponding pins of the mounted die device, thereby completing the entire Creation of wafer substrate interconnect information files.

For on-chip systems with large integration scale (hundreds of cores), many types of cores (computing cores, storage cores, interconnect cores, etc.), and diverse interconnect interfaces (Pcie, RapidIO, FC, storage interfaces) Under the characteristics, the embodiment of this case automatically creates the core chip schematic symbols, uses the schematic diagram to obtain the required mounting core chips, and completes the interconnection between the core chips according to the design requirements, and then derives the interconnection between the core chips. Information, combined with the definition of power, ground and IO externally derived from the wafer substrate, the interconnection information file design of the on-wafer system wafer substrate is simplified through the script, and the interconnection information file of the on-wafer system wafer substrate can be automatically generated to improve the on-chip system wafer substrate interconnection information file. The generation efficiency of system wafer substrate interconnection design information reduces the complexity of the system wafer substrate interconnection information file design. At the same time, the visualized schematic diagram facilitates the inspection of interconnection relationships between cores and improves interconnection information files. Generate accuracy to easily guide the physical design of silicon interposers on wafer substrates or advanced packaging.

Further, based on the above method, embodiments of the present invention also provide an on-chip system wafer substrate interconnection information construction system, including: an information acquisition module, an information processing module and an instantiation module, wherein,

The information acquisition module is used to obtain the connection point list of the on-wafer system core particles, and divide the connection points of each core particle in the connection point list into corresponding connection point types. Among them, the connection point types include: leading the signal out of the wafer substrate Connection point type one, connection point type two for signal interconnection on the wafer substrate and other types of connection point type three;

The information processing module is used to use EDA tools to comprehensively process the required mounting chip connection points and obtain the chip interconnection information files; set the top-level input and output ports of the interconnection information based on each connection point of connection point type 1 to enable connection Each connection point in point type one corresponds to the micro-bumps on the top layer of the wafer substrate or the C4 bumps on the bottom layer;

The instantiation module is used to instantiate the required mounting die based on the die interconnection information file and the top-level input and output ports to obtain the on-wafer system wafer substrate interconnection information.

Unless otherwise specifically stated, the relative order of components and steps, numerical expressions, and numerical values set forth in these examples do not limit the scope of the invention.

Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on its differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. As for the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple. For relevant details, please refer to the description in the method section.

The units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, in the above description The composition and steps of each example have been generally described in terms of function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Persons of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementations are not considered to be beyond the scope of the present invention.

Those of ordinary skill in the art can understand that all or part of the steps in the above method can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk or an optical disk. Optionally, all or part of the steps of the above embodiments can also be implemented using one or more integrated circuits. Correspondingly, each module/unit in the above embodiments can be implemented in the form of hardware, or can also be implemented in the form of software function modules. Form realization. The invention is not limited to any particular form of combination of hardware and software.

Finally, it should be noted that the above-mentioned embodiments are only specific implementations of the present invention and are used to illustrate the technical solutions of the present invention rather than to limit them. The protection scope of the present invention is not limited thereto. Although refer to the foregoing The embodiments illustrate the present invention in detail. Those of ordinary skill in the art should understand that any person familiar with the technical field can still modify the technical solutions recorded in the foregoing embodiments within the technical scope disclosed by the present invention. It may be easy to think of changes, or equivalent substitutions of some of the technical features; and these modifications, changes or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and they should all be included in the present invention. within the scope of protection. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (8)

1. The method for constructing the interconnection information of the wafer substrate of the system on chip is characterized by comprising the following steps of:

obtaining a connection point list of system-on-chip core grains, and dividing each core grain connection point in the connection point list into corresponding connection point types, wherein the connection point types comprise: leading signals out of a first connection point type outside the wafer substrate, a second connection point type for signal interconnection on the wafer substrate and a third connection point type of other types;

comprehensively processing the required mounting core particle connection points by using an EDA tool to obtain a core particle interconnection information file; setting an interconnection information top layer input/output port based on each connection point of the connection point type I, so that each connection point of the connection point type I corresponds to a micro bump on the top layer or a C4 bump on the bottom layer of the wafer substrate;

and instantiating the required mounting core particles based on the core particle interconnection information file and the top-layer input/output port so as to acquire the interconnection information of the wafer substrate of the system on chip.

2. The method for constructing interconnection information of a wafer substrate of a system on a chip according to claim 1, wherein obtaining a connection point list of a system on a chip includes:

list of connection points for all mounted types of die.

3. The method of claim 1, wherein the second connection point type at least comprises a die power connection point, a ground connection point, and an IO connection point.

4. The method for constructing interconnection information of a wafer substrate of a system on a chip according to claim 1, wherein each core connection point in the connection point list is divided into a corresponding connection point type, further comprising:

setting the connection point names and/or connection point connection line names of the core particles according to a preset mapping rule, and representing the connection mapping relation of each connection point of the core particles by using the names.

5. The method for constructing interconnection information of a wafer substrate of a system on a chip according to claim 1, wherein the processing of the required die attach points by using an EDA tool to obtain a die interconnection information file, further comprises:

and performing correctness checking on the wafer substrate core connection relation based on the core interconnection relation, wherein the correctness checking comprises automatic DRC checking by using an EDA tool and manual checking by using a visual schematic diagram window.

6. A system-on-chip wafer substrate interconnect information construction system, comprising: an information acquisition module, an information processing module and an instantiation module, wherein,

the information acquisition module is used for acquiring a connection point list of the system-on-chip core grains and dividing connection points of the core grains in the connection point list into corresponding connection point types, wherein the connection point types comprise: leading signals out of a first connection point type outside the wafer substrate, a second connection point type for signal interconnection on the wafer substrate and a third connection point type of other types;

the information processing module is used for comprehensively processing the required mounting core particle connection points by using an EDA tool to obtain a core particle interconnection information file; setting an interconnection information top layer input/output port based on each connection point of the connection point type I, so that each connection point of the connection point type I corresponds to a micro bump on the top layer or a C4 bump on the bottom layer of the wafer substrate;

and the instantiation module is used for instantiating the required mounted core particles based on the core particle interconnection information file and the top-layer input/output port so as to acquire the interconnection information of the wafer substrate of the system on chip.

7. An electronic device, comprising:

at least one processor, and a memory coupled to the at least one processor;

wherein the memory stores a computer program executable by the at least one processor to implement the method of any one of claims 1-5.

8. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein a computer program which, when executed, is capable of realizing the method according to any of claims 1-5.