CN117592405A - Automatic searching and optimizing connection method, device, product and medium for gate control power supply unit - Google Patents

Abstract

The invention discloses an automatic search and optimization connection algorithm, a device, an electronic device and a computer-readable storage medium for a gated power supply unit. The invention includes dividing the gated power supply unit array, grouping the gated power supply unit array, determining the gated power supply unit array cascade connection port and connecting the gated power supply unit loop based on the grouping. By grouping arrays of gated power supply units in the same power domain in pairs in sequence for loop connection, the present invention can quickly and automatically connect the gated power supply units, effectively find the shortest connection path, and at the same time reduce redundant connections and Reduce transition problems caused by long-term connections.

Description

Gated power supply units automatically search for optimized connection methods, devices, products and media

Technical field

The invention belongs to the field of low-power consumption automated design of integrated circuits. Specifically, it relates to a gated power supply unit automatically searching for optimized connection algorithms, devices, electronic equipment and computer-readable storage media.

Background technique

When designing low-power integrated circuit power supplies, the chip is generally divided into multiple power domains. The power supply of each power domain can be independently switched on and off when working and turned off when not working, which can effectively reduce chip power consumption. The key device to realize the above functions is the gated power supply unit (Power Switch cell, PSW). The gated power supply unit realizes the connection and disconnection of the circuit through the CMOS circuit structure. When one or more power domains need to be turned off, it is necessary to Larger current value. The current that a MOS tube can pass is extremely limited. Therefore, during the use phase, a large number of gated power supply units are required to work together.

As shown in Figure 1, the currently commonly used method of connecting gated power supply units is to use a daisy chain structure. All switches are connected in series to form a one-way link. When the previous power switch is turned on, an output signal is generated. After the signal is driven, a power switch is turned on. In Figure 1, the EDA tool does not optimize the connection of the gated power supply unit. In some special scenarios, such as the presence of a macro module unit near the gated power supply unit, the gated power supply unit array may not be connected. rules. In addition, there may be a gated power supply unit in the gap between two macro module units. In these cases, when the EDA tool connects the gated power supply units in series, it will automatically connect them sequentially based on the proximity principle. The EDA tool automatically connects the results. There may be situations where the front and rear units are far apart and have to be connected by long wires, resulting in uncontrollable connection wiring between gated power supply units, occupying more wiring resources, causing wiring congestion, and long wires can easily cause transition problems. (transition) needs to be repaired, which will increase the complexity of the design.

Contents of the invention

In view of this, the purpose of the present invention is to avoid the use of long wires for connecting gated power supply units and reduce design complexity, so as to solve the problems existing in the above background technology.

In order to achieve the above object, in the first aspect, the present invention provides a method for automatically searching and optimizing the connection of a gated power supply unit, including:

The step of dividing the gated power supply unit array. In this step, the gated power supply units in the chip power domain are divided into N-level gated power supply unit arrays according to their positions. The number of units in the i-th level gated power supply unit array is M _i , where, 1≤i≤N, M _i ≥2;

The step of grouping the gated power supply unit arrays. In this step, for each array in the plurality of gated power supply unit arrays, adjacent gated power supply units are grouped in two-by-two combinations in order. Even-numbered unit combinations are Two gate control units have two pairs of input terminals and output terminals, and an odd-numbered unit combination has one gate control unit that has a pair of input terminals and output terminals;

The step of determining the gated power supply unit array cascade connection port; in this step, for the plurality of gated power supply unit arrays, select the input end of the gated power supply unit as the input end of the uplink cascade connection and/or the downlink cascade connection. , select the output terminal of the gated power supply unit as the output terminal of the upstream cascade connection and/or the downstream cascade connection respectively;

The step of connecting gated power supply unit loops based on grouping; in this step, the plurality of gated power supply unit arrays are arranged based on grouping, and the input terminals and output terminals of the gated power supply units of the array are connected to form a A closed loop, in which the output end of the uplink cascade is regarded as connected to the input end of the uplink cascade, and the output end of the downlink cascade is regarded as connected to the input end of the downlink cascade. Even-numbered units have one in and one out. times, the odd-numbered unit enters and exits once.

In a second aspect, the present invention provides an automatic search and optimization connection device for a gated power supply unit, including:

Array division unit, which is used to divide the gated power supply units in the chip power domain into N-level gated power supply unit arrays according to their positions. The number of units in the i-th level gated power supply unit array is M_i, where 1≤ i≤N, M_i≥2;

An array grouping unit, the unit is used for, for each array in the plurality of gated power supply unit arrays, sequentially grouping adjacent gated power supply units in pairwise combinations. Even-numbered unit combinations have two gated units. , there are two pairs of input terminals and output terminals, and the odd unit combination has a gate control unit, which has a pair of input terminals and output terminals;

Array cascade connection port determination unit, the unit is used for selecting the input terminals of the gated power supply units as the input terminals of the upstream cascade connection and/or the downstream cascade connection for the plurality of gated power supply unit arrays, and selecting gates therefrom. The output terminals of the power supply unit are respectively used as the output terminals of the upstream cascade connection and/or the downstream cascade connection;

A loop connection unit, which is used to arrange the plurality of gated power supply unit arrays based on grouping, and connect the input terminals and output terminals of the gated power supply units of the array to form a closed loop, wherein, The output end of the uplink cascade is regarded as connected to the input end of the uplink cascade, and the output end of the downlink cascade is regarded as connected to the input end of the downlink cascade. Even-numbered units enter and exit twice, and odd-numbered units enter once. Once out.

In a third aspect, the present invention provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores information that can be executed by the at least one processor. The instructions are executed by the at least one processor, so that the at least one processor can execute the gated power supply unit automatically searching for optimized connection method.

In a fourth aspect, the present invention provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the gated power supply unit automatically searches for and optimizes the connection method.

beneficial effects

By grouping arrays of gated power supply units in the same power domain in pairs in sequence for loop connection, the present invention can quickly and automatically connect the gated power supply units, and can effectively find the shortest connection path while reducing redundant connections and reducing costs. Transition problems caused by long-term connections.

Description of drawings

Figure 1 is a schematic diagram of the principle of daisy chain connection of gated power supply units in the prior art.

FIG. 2 is a flow chart of a method for automatically searching and optimizing connections for a gated power supply unit in an embodiment of the present invention.

Figure 3 is a schematic diagram of the method of the present invention applied in an embodiment.

Figure 4 is a schematic diagram of four situations of dual array uplink cascading in some embodiments of the method of the present invention.

Figure 5 is a schematic diagram of three situations of odd array uplink cascading in some embodiments of the method of the present invention.

Figure 6 is a schematic diagram of two situations in which the uplink and downlink cascade ports are adjacent in some embodiments of the method of the present invention.

Figure 7 is a schematic diagram of five situations in which the uplink and downlink cascade ports are not adjacent in some embodiments of the method of the present invention.

Figure 8 is a schematic diagram of three situations in which the uplink and downlink cascade input ports are adjacent and the output ports are not adjacent in some embodiments of the method of the present invention.

Figure 9 is a schematic diagram of two situations in which the uplink and downlink cascade input ports are not adjacent and the output ports are adjacent in some embodiments of the method of the present invention.

Figure 10 is a schematic diagram of two situations in which the odd-numbered array unit is located in the middle in some embodiments of the method of the present invention.

Figure 11 is a schematic diagram of the automatic search and optimization connection device of the gated power supply unit in the embodiment of the present invention.

Figure 12 is a schematic diagram of the composition of an electronic device according to an embodiment of the present invention.

Reference signs

a power domain input, b power domain output, c macro module unit, d gated power unit

Detailed ways

The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, as long as there is no conflict, the following embodiments and the features in the embodiments can be combined with each other.

It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the drawings only show the components related to the present invention and do not follow the number, shape and number of components during actual implementation. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be arbitrarily changed, and the component layout type may also be more complex.

As shown in FIG. 2 , the method for automatically searching and optimizing the connection of gated power supply units in one embodiment of the present invention includes the steps of dividing the gated power supply unit array and the steps of grouping the gated power supply unit array.

In the step of dividing the gated power supply unit array, the gated power supply units in the chip power domain are divided into N-level gated power supply unit arrays according to their positions. The number of units in the i-th level gated power supply unit array is _Mi , where, 1≤i≤N, M _i ≥2.

In some embodiments of the present invention, dividing the array according to the position of the gated power supply unit specifically involves obtaining multiple gated power supply units whose Manhattan distance from the input signal from the starting point is less than a preset threshold as the first-level gated power supply unit array; Obtain a plurality of gated power supply units whose Manhattan distance from the first gated power supply unit array is smaller than a preset threshold from the remaining gated power supply units as a second gated power supply unit array; repeat the above steps to obtain the second gated power supply unit array from the remaining gated power supply unit arrays. Multiple gated power supply units whose Manhattan distances from the precursor array are smaller than a preset threshold are sequentially obtained from the gated power supply unit as the Nth gated power supply unit array.

In some embodiments of the present invention, for arranging the gated power supply units according to the grid, the gated power supply units with consistent abscissas and continuous ordinates can also be listed in the same column according to the coordinate information, and the enable terminals can be arranged according to the power domain. The distance to the response end (ack) is divided into N-level gated power supply unit arrays in ascending order.

In the step of grouping the gated power supply unit arrays, for each array in the plurality of gated power supply unit arrays, adjacent gated power supply units are grouped in pairs. If there is one gated power supply unit left in the group, , the gated power supply unit is a separate group; the even-numbered unit combination has two gated units with two pairs of input terminals and output terminals, and the odd-numbered unit combination has one gated unit with a pair of input terminals and output terminals.

In some embodiments of the present invention, the order is in end-to-end order of the array. Preferably, each gated power supply unit array has at most one odd-numbered unit, and optimally, the odd-numbered unit is located at one end of the array; in some other embodiments , or in order from the middle to both ends of the array. Preferably, each end of each gated power supply unit array has at most one odd-numbered unit. Optimally, the odd-numbered unit is located at one end of the array.

In the step of determining the upstream and downstream cascade connection ports of the gated power supply unit array, for the plurality of gated power supply unit arrays, the input end of the gated power supply unit is selected as the input end of the upstream cascade connection and/or the downlink cascade connection. The output terminal of the gated power supply unit serves as the output terminal of the upstream cascade connection and/or the downstream cascade connection.

In some embodiments of the present invention, the gated power supply unit array may have only one level, or only two levels, or may have more than three levels. Specifically, for the first-level array, the input end of the gated power supply unit needs to be selected as the input end of the upstream cascade connection, and the output end of the gated power supply unit needs to be selected as the output end of the upstream cascade connection, and connected to the use end of the power domain respectively. The energy end and the response end are the input end and output end of the power domain. Generally, if it is a multi-level array, the first level array also needs to be connected to the second level array, and the input end of the gated power supply unit is selected as the downstream level connection. The input end of the gated power supply unit is selected as the output end of the downstream cascade connection; for the Nth level array, only the input end of the gated power supply unit is selected as the input end of the upstream cascade connection, and the gated power supply unit input end is selected as the input end of the upstream cascade connection. The output end of the power supply unit is used as the output end of the uplink cascade connection; for the intermediate array, it is necessary to connect the upper and lower adjacent levels, select the input end of the gated power supply unit as the input end of the uplink cascade connection and the downlink cascade connection, select the gate The output terminal of the controlled power supply unit serves as the output terminal of the upstream cascade connection and the downstream cascade connection. The gated power supply unit array has only 1 level, which is selected according to the above-mentioned 1st level array selection rules. The gated power supply unit array has 2 levels, which are selected according to the above-mentioned selection rules for the 1st level array and the Nth level array. The gated power supply unit array has more than 3 levels, which are selected according to the above-mentioned selection rules for the 1st level array, the intermediate array and the Nth level array.

In some embodiments of the present invention, the input end and the output end of the uplink cascade are adjacent, and the input end and the output end of the downlink cascade are adjacent. In some embodiments of the present invention, the input end and the output end of the uplink cascade may not be adjacent, and the input end and the output end of the downlink cascade may not be adjacent.

Furthermore, in other embodiments of the present invention, for the intermediate array when the number of units Mi _is ≥ 4, the input terminal of the uplink cascade, the output terminal of the uplink cascade, the input terminal of the downlink cascade, and the output terminal of the downlink cascade are Connect different gated power supply units respectively.

In some embodiments of the present invention, specifically, for the first-level array, the Manhattan distance between each gate control unit and the power domain enable end (enable) and the response end (ack) is calculated, and the distance from the power domain enable end (ack) is selected. enable) The gated power supply unit with the smallest Manhattan distance and which is not blocked is connected to the power domain enable end (enable), and the gated power supply unit with the smallest Manhattan distance and which is not blocked from the power domain responder (ack) is selected from the power domain. The response end (ack) is connected; in the array of adjacent gated power supply units, calculate the Manhattan distance between each gated power supply unit in the upper-level array and each gated power supply unit in the lower-level array, and select the one with the smallest Manhattan distance. Two pairs of gated power supply units serve as the downstream connection and the uplink connection of the two-level cascade respectively. The output end of the upper-level gated power supply unit in the downlink connection is connected to the input end of the lower-level gated power supply unit, and the uplink connection is connected to the lower-level gated power supply unit. The output terminal of the power supply unit is connected to the input terminal of the upper-level gated power supply unit, and the upstream and downstream connections are not blocked and are the closest ones.

In the step of connecting gated power supply unit loops based on grouping, the plurality of gated power supply unit arrays are arranged based on grouping, and the input terminals and output terminals of the gated power supply units of the array are connected to form a closed loop. path, in which the output end of the uplink cascade is regarded as connected to the input end of the uplink cascade, and the output end of the downlink cascade is regarded as connected to the input end of the downlink cascade.

In some embodiments of the present invention, for each array in the plurality of gated power supply unit arrays, the step of determining the upstream and downstream cascade connection ports of the gated power supply unit array may be performed first, and then the gated power supply units may be connected based on grouping. The steps of the loop.

In other embodiments of the present invention, the step of determining the upstream and downstream cascade connection ports of the multiple gated power supply unit arrays can be performed on the entire array of gated power supply units, and then for each of the multiple gated power supply unit arrays The arrays individually perform the steps of gated power unit loops based on group connections.

In some embodiments of the present invention, for each array in the plurality of gated power supply unit arrays, the gates in the group are connected in sequence starting from the input end of the upstream cascade in a clockwise or counterclockwise direction around the array. The input terminal and output terminal of the control power supply unit are finally connected to the output terminal of the upstream cascade.

FIG. 3 is a schematic diagram of the application of the automatic search and optimization connection method of the gated power supply unit in one embodiment of the present invention. The method in this embodiment includes:

1. Since the gated power supply unit PSW can be added in an array when the EDA tool is added, then according to the coordinate information, the gated power supply unit PSW with consistent abscissas and continuous ordinates are listed in the same column, as shown in Figure 3. For three columns.

2. Sort the gated power supply units in the same column from small to large according to the vertical coordinate. Combine the sorted gated power supply units in this column into two groups in order to form one unit. As shown in Figure 3, the gates in column 1 are sorted. The gated power supply units 1 and 2 form a combination as column 1-1, and the gated power supply units 3 and 4 form a combination as column 1-2. We call this combination of two units an even number combination, and they are sorted in order. When an odd number appears in this array, the last combination has only one unit. We call this an odd combination. The final arrangement and combination form is shown in Figure 3.

3. After the gated power supply units PSW are classified as above, the even number combination has two input terminals and two output terminals, and the odd number combination has only one input terminal and one output terminal. Then these gated power supply unit PSWs are connected together according to certain requirements. Forming a closed loop is equivalent to a mathematical arrangement problem. By analogy with the connections of these gated power units, we can conclude that in this mathematical arrangement, an even number combination unit will appear twice and an odd number combination unit will appear once.

4. Specifically, the combination of the nearest gated power supply unit from the enable signal (enable) and the response signal (ack) can be obtained based on the Manhattan distance. In Figure 3, it is columns 1-6, then we consider the combination of columns 1-6. One of the unit's input terminals closest to the enable signal (enable) is connected to the enable signal (enable), and at the same time, the latest output terminal to the response signal (ack) is connected to the response signal (ack). Then the mathematical arrangement corresponding to the closed loop connection of this gated power supply unit is as follows: enable signal (enable), columns 1-6, columns 1-6, response signal (ack). With this step we have determined the beginning and end of an arrangement.

5. Taking columns 1-6 as the starting point, as shown in Figure 2, we can agree to search upward, from the unit closest to columns 1-6 until reaching the last unit of column 1, so that the arrangement is: enable signal (enable ), Column 1-6, Column 1-7, Column 1-8, Column 1-9, Column 1-10, Column 1-11, Column 1-12, Column 1-12, Column 1-11, Column 1- 10, columns 1-9, columns 1-8, columns 1-7, columns 1-6, response signal (ack). In this way, a closed loop of gated power supply unit connections composed of multiple units has been formed in column 1, but there are still several units in column 1 that have not entered the connection. Then find the unit closest to the connection in column 1, as shown in Figure 2 The units in the middle column 1-6 are closest to the units 1-5 in the middle column that have not entered the connection. Then add columns 1-5 to the connection and rank them before columns 1-6 to form a new arrangement: enable signal (enable), column 1- 6. Column 1-7, Column 1-8, Column 1-9, Column 1-10, Column 1-11, Column 1-12, Column 1-12, Column 1-11, Column 1-10, Column 1- 9, columns 1-8, columns 1-7, columns 1-5, columns 1-5, columns 1-6, response signal (ack). And so on, until all units in column 1 have joined the connection, forming the final arrangement of column 1: enable signal (enable), columns 1-6, columns 1-7, columns 1-8, columns 1-9, columns 1-10, Column 1-11, Column 1-12, Column 1-12, Column 1-11, Column 1-10, Column 1-9, Column 1-8, Column 1-7, Column 1-5, Column 1-4, Column 1-3, Column 1-2, Column 1-1, Column 1-1, Column 1-2, Column 1-3, Column 1-4, Column 1-5, Column 1-6, Response Signal(ack). In this way, all the gated power supply units in column 1 are finally connected, and a closed loop of signals back and forth is formed.

6. After completing the arrangement of column 1, we enter the arrangement of the next column, such as column 2 in Figure 3. The selection of the starting point of the next column can be obtained by using the Manhattan distance. Traverse all the points in column 2 and calculate the group with the shortest Manhattan distance from column 1 in column 2 to determine the starting point of the new column, such as In Figure 3, there are multiple combinations of distances to the nearest Manhattan from column 1, such as column 1-1 and column 2-1, column 1-2 and column 2-2, column 1-9 and column 2-9, etc. Their Manhattan distances are the same. When this situation exists, except for the group of signal input units in columns 1-6 in the previous column, we can arbitrarily select one as the starting point of column 2, such as column 1-1 corresponds to Column 2-1, then the starting point of the new column can be selected as column 2-1.

7. According to the connection method of column 1, we know that column 2-1 is the starting point and end point of column 2. Since columns 2-9 in column 2 are odd combinations, then in the mathematical arrangement of column 2, column 2- 9 will appear once, and finally the connection arrangement of column 2 can be successfully deduced as: column 2-1, column 2-2, column 2-3, column 2-4, column 2-5, column 2-6, column 2 -7, Column 2-8, Column 2-9, Column 2-8, Column 2-7, Column 2-6, Column 2-5, Column 2-4, Column 2-3, Column 2-2, Column 2 -1.

8. According to the previous connection sequence of column 1 and column 2, it can be concluded that in the connection closed loop of column 1, the connection sequence of column 2 will be added at column 1-1, eventually forming a connection closed loop of all units in column 1 and column 2 : Enable signal (enable), columns 1-6, columns 1-7, columns 1-8, columns 1-9, columns 1-10, columns 1-11, columns 1-12, columns 1-12, columns 1 -11, Column 1-10, Column 1-9, Column 1-8, Column 1-7, Column 1-5, Column 1-4, Column 1-3, Column 1-2, Column 1-1, Column 2 -1, Column 2-2, Column 2-3, Column 2-4, Column 2-5, Column 2-6, Column 2-7, Column 2-8, Column 2-9, Column 2-8, Column 2 -7, Column 2-6, Column 2-5, Column 2-4, Column 2-3, Column 2-2, Column 2-1, Column 1-1, Column 1-2, Column 1-3, Column 1 -4, columns 1-5, columns 1-6, response signal (ack).

9. According to this connection method, we can connect column 3, as shown in Figure 3. By analogy, when the gated power supply unit PSW has multiple columns, they can be connected according to this method to form the final closed loop.

The application of the automatic search and optimization connection method of the gated power supply unit of the present invention in one embodiment will be described below using a single row connection situation.

Figure 4 is a schematic diagram of four situations of dual array uplink cascading in some embodiments of the method of the present invention. In Figure 4, the number of gated power supply unit array units is an even number, and they are grouped in pairs in an end-to-end order. The input terminals and output terminals of the array's upstream cascade are assigned to the same group (1 and 2 in Figure 4). Different Adjacent groups (3 in Figure 4), and non-adjacent groups (4 in Figure 4). It can be seen from the figure that closed loops can be well formed in various situations.

Figure 5 is a schematic diagram of three situations of dual array uplink cascading in some embodiments of the method of the present invention. In Figure 5, the number of gated power supply unit array units is an odd number, and they are grouped in pairs in an end-to-end order. The odd-numbered units are located at the upper end (1 and 2 in Figure 4) or at the lower end (3 in Figure 4). The input of the upstream cascade of the array terminals and output terminals are allocated in the same group (1 in Figure 4), different adjacent groups (2 in Figure 4), and non-adjacent groups (3 in Figure 4), it can be seen that the three types shown in Figure 5 situation. It can be seen from the figure that closed loops can be well formed in various situations.

Figure 6 is a schematic diagram of two situations in which the uplink and downlink cascade ports are adjacent in some embodiments of the method of the present invention. In Figure 6, the number of gated power supply unit array units is an even number, and they are grouped in pairs in an end-to-end order. The input terminals and output terminals of the array's upstream and downstream cascades are allocated in the same group (1 in Figure 4) and in different phases. Neighboring group (2 in Figure 4). It can be seen from the figure that closed loops can be well formed in various situations.

Figure 7 is a schematic diagram of five situations in which the uplink and downlink cascade ports are not adjacent in some embodiments of the method of the present invention. In Figure 7, the number of gated power supply unit array units is an even number, and they are grouped in pairs in an end-to-end order. The input terminals and output terminals of the array's upstream and downstream cascades are not adjacent. It can be seen from the figure that closed loops can be well formed in various situations. In Figure 7, there is a crossover situation in the closed loops 3, 4, and 5, and some restrictions are required when routing relative to 1 and 2.

Figure 8 is a schematic diagram of three situations in which the uplink and downlink cascade input ports are adjacent and the output ports are not adjacent in some embodiments of the method of the present invention. In Figure 8, the number of gated power supply unit array units is an even number, and they are grouped in pairs in an end-to-end order. The input ports of the array's upstream and downstream cascades are adjacent, but the output ports are not adjacent. It can be seen from the figure that closed loops can be well formed in various situations.

Figure 9 is a schematic diagram of two situations in which the uplink and downlink cascade input ports are not adjacent and the output ports are adjacent in some embodiments of the method of the present invention. In Figure 9, the number of gated power supply unit array units is an even number, and they are grouped in pairs in an end-to-end order. The input ports of the array's upstream and downstream cascades are not adjacent, but the output ports are adjacent. It can be seen from the figure that closed loops can be well formed in various situations.

Figure 10 is a schematic diagram of two situations in which the odd-numbered array unit is located in the middle in some embodiments of the method of the present invention. In Figure 9, the number of gated power supply unit array units is an odd number, and they are grouped in pairs in an end-to-end order. The odd-numbered units are set in the middle of the array, and the upstream cascade ports of the array are adjacent. It can be seen from the figure that closed loops can be well formed in various situations.

It can be seen from the embodiments in Figures 4 to 10 that the method of the present invention can quickly and automatically connect the gated power supply unit, and can effectively find the shortest connection path. At the same time, it can reduce redundant connections and reduce transition problems caused by long-term connections. .

As shown in Figure 11, the automatic search and optimization connection device of the gated power supply unit in one embodiment of the present invention includes:

Array division unit, which is used to divide the gated power supply units in the chip power domain into N-level gated power supply unit arrays according to their positions. The number of units in the i-th level gated power supply unit array is _Mi , where, 1 ≤i≤N, M _i ≥2;

Array grouping unit, this unit is used for grouping adjacent gated power supply unit combinations in order for the plurality of gated power supply unit arrays. Even-numbered unit combinations have two gated units, and there are two pairs. Input terminals and output terminals, the odd-numbered unit combination has a gate control unit, which has a pair of input terminals and output terminals;

Array cascade connection port determination unit, the unit is used for selecting the input terminals of the gated power supply units as the input terminals of the upstream cascade connection and/or the downstream cascade connection for the plurality of gated power supply unit arrays, and selecting gates therefrom. The output terminals of the power supply unit are respectively used as the output terminals of the upstream cascade connection and/or the downstream cascade connection;

A loop connection unit, which is used to arrange each array in the plurality of gated power supply unit arrays based on grouping, and connect the input terminals and output terminals of the gated power supply units of the array to form a closed loop. Loop, in which the output end of the uplink cascade is regarded as connected to the input end of the uplink cascade, the output end of the downlink cascade is regarded as connected to the input end of the downlink cascade, and the even-numbered units enter and exit twice. , the odd-numbered unit enters and exits once. In one embodiment, the present invention provides an electronic device. As shown in Figure 12, the electronic device includes at least one processor and a memory communicatively connected to the at least one processor; wherein the memory stores information that can be processed by at least one processor. Instructions executed by the processor are executed by at least one processor, so that at least one processor can execute the above-mentioned automatic search and optimized connection method of the gated power supply unit.

Among them, the memory and the processor are connected using a bus. The bus can include any number of interconnected buses and bridges. The bus connects one or more processors and various circuits of the memory together. The bus can also connect various other circuits together through interfaces such as peripherals, voltage regulators, and power management circuits, all of which are well known in the art. The interface provides an interface between the bus and the transceiver, such as a communication interface and a user interface. A transceiver may be one element or may be multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. The data processed by the processor is transmitted over the wireless medium through the antenna. Further, the antenna also receives the data and transmits the data to the processor.

The processor is responsible for managing the bus and general processing, and can also provide a variety of functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory can be used to store data used by the processor when performing operations.

In one embodiment, the present invention provides a computer-readable storage medium that stores a computer program. When the computer program is executed by a processor, the above-mentioned embodiment of the gated power supply unit automatically searches for and optimizes the connection method.

Those skilled in the art can understand from the above description that all or part of the steps in the methods of the above embodiments can be completed by instructing relevant hardware through a program. The program is stored in a storage medium and includes several instructions to make a device ( It may be a microcontroller, a chip, etc.) or a processor (processor) that executes all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage media include, but are not limited to, various media that can store program codes, such as USB flash drives, mobile hard disks, magnetic memories, and optical memories.

In the several embodiments provided in this application, it should be understood that the disclosed system, device or method can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of modules/units is only a logical function division. In actual implementation, there may be other division methods, for example, multiple modules or units may be combined or can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be indirect coupling or communication connection through some interfaces, devices or modules or units, which may be in electrical, mechanical or other forms.

Modules/units described as separate components may or may not be physically separate. Components shown as modules/units may or may not be physical modules, that is, they may be located in one place, or they may be distributed to multiple network units. superior. Some or all of the modules/units may be selected according to actual needs to achieve the purpose of the embodiments of the present application. For example, each functional module/unit in various embodiments of the present application can be integrated into a processing module, or each module/unit can exist physically alone, or two or more modules/units can be integrated into one module/unit. in the unit.

Those of ordinary skill in the art should further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of both. In order to clearly illustrate the hardware and software interchangeability. In the above description, the composition and steps of each example have been generally described according to functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each specific application, but such implementations should not be considered beyond the scope of this application.

The descriptions of the processes or structures corresponding to each of the above drawings have different emphasis. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

The above embodiments only illustrate the principles and effects of the present application, but are not used to limit the present application. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in this application shall still be covered by the claims of this application.

Claims (10)

1. The automatic searching and optimizing connection method for the gate control power supply unit is characterized by comprising the following steps of:

dividing the gate control power supply unit array into N-level gate control power supply unit arrays according to the positions of the gate control power supply units in the chip power supply domain, wherein the number of units of the ith-level gate control power supply unit array is M _i Wherein i is more than or equal to 1 and less than or equal to N, M _i ≥2；

Grouping the gating power supply unit arrays, wherein for each of the plurality of gating power supply unit arrays, adjacent gating power supply units are grouped in sequence in pairs, each gating power supply unit is combined with two gating units, each gating unit is provided with two pairs of input ends and output ends, each gating unit is combined with a single gating unit, and each gating unit is provided with a pair of input ends and output ends;

determining a gate control power supply unit array cascade port; in the step, for the multiple gating power supply unit arrays, the input ends of the gating power supply units are selected as the input ends of uplink and/or downlink cascade respectively, and the output ends of the gating power supply units are selected as the output ends of uplink and/or downlink cascade respectively;

gating the power supply unit loop based on the packet connection; in this step, for the multiple gating power supply unit arrays, the input ends and the output ends of the gating power supply units of the arrays are connected to form a closed loop based on grouping arrangement, wherein the output end of the uplink cascade is regarded as being connected to the input end of the uplink cascade, the output end of the downlink cascade is regarded as being connected to the input end of the downlink cascade, the even number of units are input and output twice, and the odd number of units are input and output once.

2. The automatic search optimizing connection method of the gate power supply unit according to claim 1, wherein in the step of dividing the gate power supply unit array, gate power supply units with consistent abscissa and continuous ordinate are classified into the same column according to the coordinate information, and are divided into N-level gate power supply unit arrays according to the distances between the gate power supply array and the power domain enabling end and the response end in order from small to large.

3. The automatic search and optimization connection method of the gate control power supply unit according to claim 1, wherein in the step of grouping the gate control power supply unit arrays, specifically, the order is in an array end-to-end order; alternatively, the order is from the middle of the array to both ends, respectively.

4. The automatic search and optimization connection method of the gating power supply unit according to claim 3, wherein in the step of grouping the gating power supply unit arrays, specifically, the sequence is that according to the end-to-end sequence of the arrays, at most one singular unit exists in each gating power supply unit array; alternatively, the sequence is from the middle of the array to the two ends, and each gating power cell array has at most two singular units.

5. The method for automatically searching and optimizing connection of a gate-controlled power supply unit according to claim 4, wherein in the step of determining the cascade ports of the gate-controlled power supply unit array, the input end and the output end of the upstream cascade are adjacent, and the input end and the output end of the downstream cascade are adjacent.

6. The method for automatically searching and optimizing connection of gate-controlled power supply units according to claim 5, wherein in the step of determining the gate-controlled power supply unit array cascade port, for the number of units M _i An intermediate array of equal to or greater than 4, wherein the input end of the uplink cascade, the output end of the uplink cascade, the input end of the downlink cascade and the output end of the downlink cascade are respectively connectedDifferent gating power supply units are connected.

7. The automatic search optimizing connection method of a gate power supply unit according to claim 6, wherein in the step of connecting the gate power supply unit loops based on the group, for each of the plurality of gate power supply unit arrays, the input terminal and the output terminal of the gate power supply unit in the group are sequentially connected from the input terminal of the upstream cascade in a clockwise direction or a counterclockwise direction around the array, and finally connected to the output terminal of the upstream cascade.

8. An automatic search optimizing connection device for a gate control power supply unit, comprising:

an array dividing unit for dividing the gate power supply units in the chip power supply domain into N-stage gate power supply unit arrays according to the positions of the gate power supply units, wherein the number of the ith-stage gate power supply unit array is M _i Wherein i is more than or equal to 1 and less than or equal to N, M _i ≥2；

The array grouping unit is used for grouping adjacent gating power supply units into groups according to the sequence, wherein two gating units are combined into a double-number unit, two pairs of input ends and output ends are arranged on the double-number unit, one gating unit is combined into a single-number unit, and a pair of input ends and output ends are arranged on the single-number unit;

the array cascade port determining unit is used for selecting the input ends of the gating power supply units from the multiple gating power supply unit arrays as the input ends of the uplink cascade and/or the downlink cascade respectively, and selecting the output ends of the gating power supply units from the multiple gating power supply unit arrays as the output ends of the uplink cascade and/or the downlink cascade respectively;

a loop connection unit for, for each of the plurality of arrays of gating power supply units, arranging based on a packet, connecting input terminals and output terminals of the gating power supply units of the array to form a closed loop, the output end of the uplink cascade is regarded as being connected to the input end of the uplink cascade, the output end of the downlink cascade is regarded as being connected to the input end of the downlink cascade, the double units enter one by one and exit two times, and the singular units enter one by one and exit one by one.

9. An electronic device, comprising:

at least one processor; the method comprises the steps of,

a memory communicatively coupled to the at least one processor; wherein,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the gated supply unit auto-seek optimization method as claimed in any one of claims 1 to 7.

10. A computer readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the gated supply unit auto search optimizing connection method of any of claims 1 to 7.