CN117559988A - Level conversion circuit - Google Patents

Abstract

The embodiment of the disclosure discloses a level shift circuit, comprising: the first switch is connected with the first high-level end, and the second end is connected with the signal output end of the level conversion circuit; the first end of the second switch is connected with the first low-level end, and the second end of the second switch is connected with the signal output end of the level conversion circuit; the input end of the first conversion circuit is respectively connected with the second high-level end and the second low-level end, and the output end of the first conversion circuit is connected with the control end of the first switch; the first end of the first capacitor is connected with the control end of the second switch; a blocking circuit connected to the first end of the first capacitor to block charge leakage of the first capacitor in a charged state of the first capacitor; and the output end of the second conversion circuit is connected with the second end of the first capacitor, and the input end of the second conversion circuit is connected with the second high-level end or the second low-level end so as to provide the first voltage or the second voltage for the first capacitor. The level conversion circuit in the embodiment of the disclosure can reduce the occurrence of signal output errors or delays.

Description

Level conversion circuit

Technical Field

Embodiments of the present disclosure relate to the field of circuit design, and relate to, but are not limited to, a level shifter circuit.

Background

Level Shift circuits (Level Shift) are widely used, and the voltage domain of the Level Shift circuit of the conventional Level Shift circuit is changed from 0 to VDDL to 0 to VDDH, and VDDL and VDDH are both positive voltages, whereas the conventional Level Shift circuit cannot realize the Level Shift function when the local is not 0 but is a negative voltage. If the driving capability of the on-chip charge pump for generating negative voltage is limited, the negative voltage is lifted when the level conversion circuit works, so that the level conversion is overturned slowly or not, and the problems of no output signal or delayed output signal and the like are caused.

Disclosure of Invention

In view of this, an embodiment of the present disclosure provides a level shifter circuit, including:

the first end of the first switch is connected with the first high-level end, and the second end of the first switch is connected with the signal output end of the level conversion circuit; the first end of the second switch is connected with the first low-level end, and the second end of the second switch is connected with the signal output end of the level conversion circuit;

the input end of the first conversion circuit is respectively connected with the second high-level end and the second low-level end, and the output end of the first conversion circuit is connected with the control end of the first switch;

the first end of the first capacitor is connected with the control end of the second switch;

a blocking circuit connected to a first end of the first capacitor to block leakage of charge of the first capacitor in a charged state of the first capacitor;

And the output end of the second conversion circuit is connected with the second end of the first capacitor, and the input end of the second conversion circuit is connected with the second high-level end or the second low-level end so as to provide a first voltage or a second voltage for the first capacitor.

In some embodiments, the blocking circuit comprises:

the first end of the third switch is connected with the first end of the first capacitor, and the second end of the third switch is connected with the second low-level end; the control end of the third switch is used for receiving a changed first input level signal so as to control the third switch to release the charge of the first capacitor when being conducted, so that the second switch is turned off; or when the third switch is controlled to be turned off, the charge leakage of the first capacitor is blocked.

In some embodiments, the blocking circuit further comprises:

and the control circuit is connected with the control end of the third switch to provide the first input level signal to switch the on or off state of the third switch.

In some embodiments, the control circuit comprises:

a second capacitor having a first end for receiving a varying second input level signal;

a fourth switch, the first end of which is connected with the first end of the second capacitor, and the second end of which is connected with the control end of the third switch, so that the voltage of the control end of the third switch is the same as the first end of the second capacitor;

And the first end of the fifth switch is connected with the second end of the second capacitor, and the second end of the fifth switch is connected to the control end of the third switch so that the voltage of the control end of the third switch is the same as that of the second end of the second capacitor.

In some embodiments, the control circuit further comprises: and the first end of the sixth switch is connected with the second end of the second capacitor, the second end of the sixth switch is connected with a second low level, and the second end of the second capacitor is connected with the second low level through the sixth switch.

In some embodiments, the first end of the sixth switch is connected to the second low-level end, the second end is connected to the second end of the second capacitor, and the control end is connected to the second end of the fourth switch and the second end of the fifth switch; when the fourth switch is turned on, the sixth switch is turned off, so that electric leakage of the second capacitor is reduced; when the fifth switch is turned on, the sixth switch is turned on to release the charge on the second capacitor.

In some embodiments, the control circuit further comprises: and the first end of the first resistor is connected with the second end of the second capacitor, and the second end of the first resistor is connected with the first end of the sixth switch.

In some embodiments, the control circuit further comprises: and the input end of the first inverter is used for receiving the second input level signal, and the output end of the first inverter is connected with the first end of the second capacitor.

In some embodiments, the second input level signal received by the input terminal of the control circuit is the enable signal, and the enable signal is used for indicating an operating state or a non-operating state of the level conversion circuit;

and the control circuit controls the third switch to be turned off when the enabling signal indicates the working state, and controls the third switch to be turned on when the enabling signal indicates the non-working state.

In some embodiments, the level shifting circuit further comprises:

an input signal terminal for receiving an input signal;

and the enabling signal end is used for receiving the enabling signal, wherein the enabling signal indicates the level conversion circuit to control the conduction of the first switch and the second switch together with the input signal when in the working state.

Through the level conversion circuit of the embodiment of the disclosure, the first switch for outputting the first high-level signal and the second switch for outputting the first low-level signal are respectively controlled through the first conversion circuit and the second conversion circuit. And a first capacitor is also connected between the second switch and the first conversion circuit, and the second switch is turned on by a discharge signal of the first capacitor. And the blocking circuit is connected to the first end of the first capacitor, so that the charge leakage of the first capacitor in a charged state is blocked, the on and off states of the second switch are switched by using the charged charge of the first capacitor, the on and off of the second switch are not influenced by the voltage of the first low-level end, and the level conversion error or delay is reduced.

Drawings

Fig. 1 is a schematic diagram of a level shifter circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a level shifter circuit according to a second embodiment of the present disclosure;

fig. 3 is a schematic diagram III of a level shifter circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a level shifter circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a level shifter circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a level shifter circuit according to an embodiment of the present disclosure;

fig. 7 is a block diagram of a signal processing apparatus according to an embodiment of the present disclosure.

Detailed Description

In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1, an embodiment of the present disclosure provides a level shift circuit 100 including:

a first switch K1 having a first end connected to a first high-level end and a second end connected to the signal output end OUT of the level shifter circuit 100;

a second switch K2 having a first terminal connected to the first low-level terminal and a second terminal connected to the signal output terminal OUT of the level shifter circuit 100;

the input end of the first conversion circuit 110 is respectively connected with the second high-level end and the second low-level end, and the output end of the first conversion circuit is connected with the control end (node A) of the first switch K1;

a first end (node B) of the first capacitor C1 is connected to the control end of the second switch K2;

the output end of the second conversion circuit 120 is connected with the second end (node C) of the first capacitor C1, and the input end of the second conversion circuit is connected with the second high-level end or the second low-level end to provide the first voltage or the second voltage for the first capacitor C1;

and a blocking circuit 130 connected to the first end of the first capacitor C1 to block leakage of charges of the first capacitor C1 in a charged state of the first capacitor C1.

In some embodiments, the first high level terminal and the second high level terminal are independent of each other and are configured to provide different high level signals; the first low level end and the second low level end are mutually independent and are used for providing different low level signals.

Illustratively, the first high-level terminal is used for providing the first high-level signal VDDH, the second high-level terminal is used for providing the second high-level signal VDDL, the first low-level terminal is used for providing the first low-level signal VSSL, and the second low-level terminal is used for providing the second low-level signal VSS.

The first switch K1 and the second switch K2 may be three-terminal devices such as a triode and a field effect transistor, and here, the transistors are taken as examples, the first switch K1 may be a P-type transistor, and the second switch K2 may be an N-type transistor.

For convenience of description, a node to which the control terminal of the first switch is connected is referred to as a node a, a node to which the control terminal of the second switch is connected is referred to as a node B, and a node to which the first capacitor C1 is connected to the second conversion circuit 120 is referred to as a node C.

The output voltage VDDH of the first high-level end is a back-stage power supply voltage, and the output voltage VDDL of the second high-level end is a front-stage power supply voltage; the voltage VSS at the second low-level terminal may be a ground voltage or a preset low-level voltage, for example, a negative voltage; the voltage VSSL at the first low-level terminal is a negative voltage, and the voltage value thereof may be equal to the negative value (-VDDL) of the voltage at the second high-level terminal, but may be other preset low-voltage values.

The level shifter 100 in the embodiment of the present disclosure switches the output level by switching on and off the first switch K1 and the second switch K2. When the first switch K1 is turned on, the second switch K2 is turned off, and the first high-level terminal connected to the first terminal of the first switch K1 provides a voltage to the signal output terminal OUT, so that the output voltage is VDDH.

When the second switch K2 is turned on, the first switch K1 is turned off, and the first low-level terminal connected to the first terminal of the second switch K2 provides a voltage to the signal output terminal OUT, so that the output voltage is VSSL.

The first switch K1 is controlled by the first conversion circuit 110, and the second switch K2 is controlled by the second conversion circuit 130 and the first capacitor C1. Since the second switching circuit 120 is configured to charge the first capacitor C1 and control the on/off of the second switch K2 according to the charged charge, the on/off of the second switch K2 is not associated with the first low level terminal, so that VSSL is not raised and cannot be turned on. In contrast, conventional cross-coupled structures, the gate of the output switch is associated with the VSSL, and thus has an effect on the switching speed and whether the switch can be turned on when VSSL changes. Even if the VSSL is raised, the circuit in the embodiment of the present disclosure can directly output the raised VSSL, and no output delay or output error caused by the opening delay or the opening failure of the second switch K2 will occur.

In the embodiment of the present disclosure, the first end of the first capacitor C1 is further connected to the blocking circuit 130. The charge state of the first capacitor C1 stores charge, and the positive voltage or the negative voltage of the second switch K2 can be switched by using the charge polarity of the first capacitor C1, so as to switch the on and off states of the second switch. The first capacitor C1 is required to have the capability of maintaining the charge, because if the charge leaks, it may cause the voltage provided to the second switch K2 to be insufficient to control the second switch K2 to be turned on or off, thereby affecting the effect of the second switch K2. The blocking circuit 130 may form a larger impedance at the first end of the first capacitor C1 so that the charge of the first capacitor C1 is maintained, i.e. the leakage of the charge of the first capacitor C1 is blocked.

In some embodiments, as shown in fig. 2, the blocking circuit 130 includes:

a third switch K3, a first end of which is connected to the first end of the first capacitor C1, and a second end of which is connected to the second low-level end; the control end of the third switch K3 is configured to receive a changed first input level signal S1, so as to control the third switch K3 to release the charge of the first capacitor C1 when turned on, so that the second switch K2 is turned off; or when the third switch K3 is controlled to be turned off, the leakage of the charge of the first capacitor is blocked, and the second switch K2 is turned on.

Here, the blocking circuit is composed of a third switch K3. The third switch K3 is turned on to connect the first end of the first capacitor C1 to the second low-level end, so that the potential of the third switch is consistent with the potential of the second low-level signal, for example, the ground. This means that the control terminal of the second switch K2 is grounded, and the second switch K2 is turned off.

When the third switch K3 is turned off, a large impedance may be formed at the first end of the first capacitor C1, and the charge in the first capacitor C1 leaks from the first end.

The first input level signal S1 received by the control terminal of the third switch K3 is used for switching the two states. It can be understood that when the second switch needs to be turned on, the first input level signal S1 is a signal for turning off the third switch K3; when the second switch does not need to be turned on, the first input level signal S1 is a signal for turning on the third switch K3.

In some embodiments, as shown in fig. 3, the blocking circuit 130 further includes:

the control circuit 131 is connected to the control end of the third switch K3, so as to provide the first input level signal S1 to switch the on or off state of the third switch K3.

The output signal of the control circuit 131 is the first input level signal S1

In some embodiments, as shown in fig. 4, the control circuit 131 includes:

a second capacitor C2 having a first terminal for receiving a varying second input level signal S2;

a fourth switch K4, a first end of which is connected to the first end of the second capacitor C2, and a second end of which is connected to the control end of the third switch K3, so that the voltage of the control end of the third switch K3 is the same as the first end of the second capacitor C2;

and a fifth switch K5, wherein a first end of the fifth switch K5 is connected to the second end of the second capacitor C2, and a second end of the fifth switch K3 is connected to the control end of the third switch K3, so that the voltage of the control end of the third switch K3 is the same as the voltage of the second end of the second capacitor C2.

The second input level signal S2 is an input signal to the control circuit 131, and the first input level signal S1 is an output signal from the control circuit 131. That is, the first input level signal S1 is changed with the change of the second input level signal S2.

The control circuit 131 uses the second capacitor C2 to receive the second input level signal S2, so that the second capacitor charges or discharges with the second input level signal S2. After the second capacitor C2 is charged, the voltage of the first terminal is different from the voltage of the second terminal.

Two ends of the fourth switch K4 are respectively connected with the first end of the second capacitor C2 and the control end of the third switch K3. Therefore, when the fourth switch K4 is turned on, the control terminal voltage of the third switch K3 is the same as the first terminal voltage of the second capacitor C2. At this time, the first end voltage of the charged second capacitor C2 may be used to control the on/off of the third switch K3.

Two ends of the fifth switch K5 are respectively connected with the second end of the second capacitor C2 and the control end of the third switch K3. Therefore, when the fifth switch K5 is turned on, the voltage of the control terminal of the third switch K3 is the same as the voltage of the second terminal of the second capacitor C2. At this time, the second terminal voltage of the charged second capacitor C2 may be used to control the on/off of the third switch.

It will be appreciated that the voltage across the second capacitor C2 will remain for a period of time after charging, and that the voltage across is relatively high and low. Therefore, the on and off states of the third switch K3 can be switched by switching the on and off states of the fourth switch K4 and the fifth switch K5 in this process.

In some embodiments, as shown in fig. 5, the control circuit 130 further includes: a sixth switch K6, a first end of which is connected to the second end of the second capacitor C2, a second end of which is connected to a second low level, and a second end of the second capacitor connected to the second low level through the sixth switch.

Here, the second low level may be ground or another low level. The second low level signal VSS may be provided, for example, to the second low level terminal.

The second terminal of the second capacitor C2 may be pulled low when the sixth switch K6 is turned on, thereby adjusting the voltage across the second capacitor C2.

In some embodiments, the first terminal of the sixth switch K6 is connected to the second low-level terminal, the second terminal is connected to the second terminal of the second capacitor C2, and the control terminal is connected to the second terminal of the fourth switch K4 and the second terminal of the fifth switch K5; when the fourth switch K4 is turned on, the sixth switch K6 is turned off, so as to reduce the leakage of the second capacitor C2; when the fifth switch K5 is turned on, the sixth switch K6 is turned on to release the charge on the second capacitor C2.

When the fourth switch K4 is turned on, the third switch K3 is turned off insufficiently to leak the charge of the second capacitor C2, which results in leakage of the charge of the first capacitor C1, where the sixth switch may use a MOS transistor with a larger resistance, for example, an inverted ratio transistor, i.e., a MOS transistor with a channel length L greater than the channel threshold W.

In another embodiment, when the fourth switch K4 is turned on, the sixth switch K6 is turned on to release the charge on the second capacitor C2; when the fifth switch K5 is turned on, the sixth switch K6 is turned off to reduce the leakage current of the second capacitor C2.

It can be understood that the case where the sixth switch K6 is turned off is a case where the third switch K3 is required to be turned off, so that when the sixth switch K6 is turned on, the on and off states of the fourth switch K4 and the fifth switch K5 are required to be corresponding to each other so that the third switch K3 is turned on; when the sixth switch K6 is turned off, the on and off states of the fourth switch K4 and the fifth switch K5 are required to be corresponding to each other, so that the third switch K3 is turned off. In practical applications, the types of the fourth switch K4 and the fifth switch K5 may be configured according to the requirements, so as to configure the corresponding relationship between the fourth switch K4 and the sixth switch K6.

In some embodiments, as shown in fig. 5, the control circuit 131 further includes: the first end of the first resistor R1 is connected with the second end of the second capacitor C2, and the second end of the first resistor R1 is connected with the first end of the sixth switch K6.

The resistance of the first resistor R1 may also be larger, thereby further reducing the leakage current on the second capacitor C2.

In some embodiments, as shown in fig. 5 above, the control circuit 131 further includes: the input end of the first inverter INV1 is used for receiving the second input level signal S2, and the output end of the first inverter INV1 is connected to the first end of the second capacitor C2.

Here, the first inverter INV1 functions to match the second input level signal S2 with the on states of the respective switches in the corresponding control circuit 131. Therefore, whether the first inverter INV1 is required may be determined according to the type of the actual second input level signal S2.

In some embodiments, the second input level signal S2 received at the input terminal of the control circuit is an enable signal EN, where the enable signal is used to indicate an operating state or a non-operating state of the level shifter circuit 100;

the control circuit 131 controls the third switch K3 to be turned off when the enable signal EN indicates the operating state, and controls the third switch K3 to be turned on when the enable signal indicates the non-operating state. Therefore, the level shifter 100 reduces the leakage of the first capacitor C1 by using the turned-off third switch K3 in the operating state, and further controls the on/off of the second switch K2 by using the charge on the first capacitor C1. In the non-working state, the third switch K3 is used to release the charge of the first capacitor C1 and simultaneously make the control terminal of the second switch K2 terminate the second low-level signal, so as to maintain a stable conducting state.

Here, the function of the control circuit 131 will be specifically described with reference to the control circuit 131 shown in fig. 5:

in the initial state, the enable signal EN outputs a low level "0" (i.e., indicates that the level shift circuit is inactive), and at this time, the first inverter INV1 outputs a high level "1", i.e., the voltage VDDL charges the capacitor C2. At this time, the fourth switch K4 is turned on to transmit the high level voltage VDDL to the control end of the third switch K3, and at this time, both the sixth switch K6 and the third switch K3 are turned on to release the charge of the first capacitor C1 through the third switch K3, and at the same time, the voltages at two sides of the second capacitor C2 are VDDL and 0, respectively, and the fifth switch K5 is turned off.

When the enable signal end EN outputs a high level "1" (i.e. indicates that the level shift circuit is active), the first inverter INV1 outputs a low level VSS (e.g. the voltage is 0), and the voltages at both sides of the second capacitor C2 become 0 and-VDDL, so that the fifth switch K5 is turned on and transfers the low level signal VSS to the control end of the sixth switch K6, and the sixth switch K6 is turned off. At the same time, the third switch K3 is turned off, thereby forming a large impedance, preventing the charge leakage of the first capacitor C1.

In some embodiments, as shown in fig. 6, the level shifter circuit 100 further includes:

an input signal terminal for receiving an input signal IN;

and the enabling signal end is used for receiving the enabling signal EN, wherein the enabling signal indicates the level conversion circuit to control the conduction of the first switch and the second switch together with the input signal when in the working state.

In some embodiments, with continued reference to fig. 6, the first switch circuit 110 has a first terminal connected to the first high-level terminal and a second terminal connected to the second low-level terminal; the first switching circuit 110 is configured to control on or off of the first switch according to a second high level signal VDDL provided by the second high level terminal or according to a second low level signal VSS provided by the second low level terminal.

The first conversion circuit 110 connects the second high-level terminal and the second low-level terminal as the inputs of the previous stage, and confirms whether to output the second high-level signal VDDL provided by the above-described second high-level terminal or the second low-level signal VSS provided by the second low-level terminal based on some input signals. Illustratively, if outputting the second high level signal VDDL may turn on the first switch K1, outputting the second low level signal VSS may turn off the first switch K1; alternatively, if the first switch K1 is turned off by outputting the second high level signal VDDL, the first switch K1 is turned on by outputting the second low level signal VSS. It will be appreciated that if the first switch K1 uses a field effect transistor, a PMOS transistor may be used in connection with a high level, so as to achieve better turn-on and turn-off performance.

Since the first switch K1 is connected to the first high-level terminal, the first high-level signal VDDH provided from the first high-level terminal can be transmitted to the signal output terminal OUT of the level shift circuit through the first switch K1 when the first switch K1 is turned on, and thus, level shift from the second high-level signal VDDL to the first high-level signal VDDH is achieved.

In some embodiments, as shown in fig. 6, the first conversion circuit 110 is further connected to an input signal terminal, and the first conversion circuit 110 includes: the first pull-up switch P1, the second pull-up switch P2, the first pull-down switch N1 and the second pull-down switch N2;

the first end of the first pull-up switch P1 is connected with the first high-level end, the second end of the first pull-up switch P1 is connected with the first end of the first pull-down switch N1, and the control end of the first pull-up switch P1 is connected with the second end of the second pull-up switch P2;

the first end of the second pull-up switch P2 is connected to the first high-level end, the second end is connected to the first end of the second pull-down switch P2, and is connected to the output end of the first conversion circuit, namely the node a, and the control end is connected to the second end of the first pull-up switch;

the control end of the first pull-down switch N1 is configured to receive the second high level signal VDDL or the second low level signal VSS according to an inverted signal of the input signal IN, and the second end is connected to the second low level end VSS; the first pull-down switch N1 is configured to be turned on when receiving the second high level signal VDDL to pull down the voltage of the control terminal of the second pull-up switch P2, turn on the second pull-up switch P2 and pull up the output voltage of the first conversion circuit 110 to turn off the first switch K1;

The control end of the second pull-down switch N2 is configured to receive the second high level signal VDDL or the second low level signal VSS according to the input signal IN, and the second end is connected to the second low level end VSS; the second pull-down switch N2 is configured to be turned on when receiving the second high level signal VDDL, so as to pull down the voltage of the control terminal of the first pull-up switch, turn on the first pull-up switch, and pull down the output signal of the first conversion circuit, so that the first switch K1 is turned on.

The input signal IN is used to determine whether the level shift circuit 100 is to shift the second high level signal VDDL to the first high level signal VDDH or the second low level signal VSS to the first low level signal VSSL. The first conversion circuit 110 is configured to determine whether to convert the second high level signal VDDL into the first high level signal VDDH according to the data signal IN. For example, if the input signal IN is "1", it is determined to convert the second high level signal VDDL into the first high level signal VDDH, and the first converting circuit 110 performs the conversion function. If the input signal IN is "0", the level shift circuit does not shift the high level signal but is used to shift the second low level signal VSS to the first low level signal VSSL, so at this time, the first shift circuit 110 only functions to turn off the first switch K1, and the level shift circuit does not output the first high level signal VDDH. Is arranged to output the first low level signal VSSL, and is implemented by the second conversion circuit.

For example, the first pull-up switch P1 and the second pull-up switch P2 in the first converting circuit 110 may be two PMOS transistors connected in a cross-connection manner, and in an operating state, they are in a one-on-one-off state. Correspondingly, the first pull-down switch N1 and the second pull-down switch N2 may adopt two NMOS transistors, the control ends of which are controlled by the input signal IN and the inverted signal of the input signal IN respectively, as shown IN fig. 6, the input signal IN may be used as the input signal of the control end of the first pull-down switch N1 through the first input signal INA of the NAND gate NAND1 after one inversion; the second input signal INB, which is inverted twice by the second inverter INV2, can be used as the input signal of the control terminal of the second pull-down switch N2. When the first input signal INA is the second high level signal VDDL, the second input signal INB is the second low level signal VSS; when the first input signal INA is the second low-level signal VSS, the second input signal INB is the second low-high-level signal VDDL. Thus, the two switches also remain in an on-off state in the operating state. In an embodiment, the control terminals of the first pull-down switch N1 and the second pull-down switch N2 may be connected to a signal selection circuit. The signal selection circuit selects whether to output the second high level signal VDDL or the second low level signal VSS to the control terminals of the first pull-down switch N1 and the second pull-down switch N2 according to the received input signal IN.

That is, if the first switch K1 is turned off by the first converting circuit 110 outputting the high level signal, the first pull-up switch P1 is turned off, the second pull-up switch P2 is turned on, the first pull-down switch N1 is turned on, and the second pull-down switch N2 is turned off. Therefore, the inverse signal of the input signal IN received by the control terminal of the first pull-down switch N1 is at a high level, and the input signal IN received by the control terminal of the second pull-down switch N2 is at a low level.

Accordingly, if the first switch K2 is turned on by the first converting circuit 110 outputting the low level signal, the first pull-up switch P1 is turned on, the second pull-up switch P2 is turned off, and the first pull-down switch N1 is turned off, and the second pull-down switch N2 is turned on. Therefore, the inverse signal of the input signal IN received by the first pull-down switch N1 control terminal is at a low level, and the input signal IN received by the second pull-down switch N2 control terminal is at a high level. At this time, the level conversion of the second high level signal VDDL provided at the input second high level terminal to the first high level signal VDDH provided at the first high level terminal is realized.

In some embodiments, as shown in fig. 6, the second conversion circuit 120 is further connected to an input signal terminal; the second conversion circuit 120 includes: a seventh switch K7 and/or an eighth switch K8;

The first ends of the seventh switch K7 and the eighth switch K8 are connected to the second end of the first capacitor C1, and the second end is connected to the second high level end or the second low level end according to the inverted signal of the input signal IN; wherein the seventh switch K7 and the eighth switch K8 are turned on in an operating state of the level shifter circuit 100 and turned off in a non-operating state based on an enable signal EN.

Similar to the function of the first conversion circuit 120, the second conversion circuit 120 is connected to the input signal terminal and the enable signal terminal, and determines whether to turn on the second switch K2 based on the input signal IN.

For example, if the input signal IN is "1", it is determined to convert the second high level signal VDDL into the first high level signal VDDH, and the first converting circuit 110 performs the conversion function. If the input signal IN is "0", the level shifter 100 is configured to shift the second low level signal VSS into the first low level signal VSSL, and at this time, the second shifter 120 and the first capacitor C1 together function to turn on the second switch K2, so that the level shifter outputs the first low level signal VSSL.

Specifically, the second conversion circuit 120 may include only one switch (the seventh switch K7 or the eighth switch K8), or may include the two switches in parallel. If two switches are used, the conduction performance is better, and the first capacitor C1 can be charged faster. Taking two switches as an example, the control ends of the seventh switch and the eighth switch are connected with the enabling signal end and controlled by the enabling signal EN. The enable signal EN is used to switch the operating state and the non-operating state of the entire level shifter circuit 100. As shown in fig. 6, if the seventh switch K7 and the eighth switch K8 are an NMOS transistor and a PMOS transistor, respectively, the control terminal of the seventh switch K7 may be controlled by the enable signal EN (or the second enable signal ENB after the enable signal is inverted twice), and the control terminal of the eighth switch K8 may be controlled by the first enable signal ENA after the enable signal is inverted once. The second ends of the seventh switch K7 and the eighth switch K8 are connected to the inverted signal of the input signal, i.e. the first input signal INA. The first input signal INA is actually the second high level signal VDDL or the second low level signal VSS obtained based on the input signal IN.

In the operating state, the seventh switch K7 and the eighth switch K8 are turned on, and the second high level signal VDDL or the second low level signal VSS connected to the first terminal thereof may be transmitted to the first capacitor C1, so that the second switch K2 is controlled to be turned on or not by the voltage state of the other terminal (i.e. the node B) of the first capacitor C1, for example, the second switch K2 may be an NMOS transistor, where the control terminal is turned on when the control terminal is at a high level, and the control terminal is turned off when the control terminal is at a low level. It will be appreciated that the second high level signal VDDL or the second low level signal VSS is provided according to the input signal IN, and the position may provide the second high level signal VDDL if the input signal is "0" and the position may provide the second low level signal VSS if the input signal is "1".

When the input signal is "0", the second high level signal VDDL charges the first capacitor C1 (node C) through the seventh switch K7 and the eighth switch K8 to make the voltage VDDL, and at this time, the voltage at the other end (node B) of the first capacitor C1 is 0. Since the source terminal of the second switch K2 is connected to the first low level terminal, the voltage VSSL thereof is negative, and thus the second switch K2 may be in a conductive state at this time, so that the signal output terminal OUT outputs the first low level signal VSSL.

When the input signal is "1", the second low level signal VSS pulls down the voltage of the node C through the seventh switch K7 and the eighth switch K8, so that the voltage of the node C is 0. Since the first capacitor C1 is already charged, the voltage of the node B at the other end of the first capacitor C1 is relatively changed to-VDDL, so that the voltage of the control terminal of the second switch K2 is reduced, and the switch is turned to the off state.

In some embodiments, after the level shifter circuit 100 enters the operation state based on the enable signal EN, the seventh switch K7 and the eighth switch K8 are turned on after a predetermined delay time.

IN addition, a Delay unit t_delay may be connected between the control terminals of the seventh switch K7 and the eighth switch K8 and the enable signal terminal for delaying the enable signal by a predetermined time. Thus, after the level shifter 100 enters the operation state under the control of the enable signal EN, the seventh switch K7 and the eighth switch K8 are turned on after a predetermined delay time. As shown in fig. 6, the delay unit t_delay may be connected to an input terminal of the third inverter INV3 such that the output signal enable signal EN of the third inverter is the signal ENA inverted once and delayed, the fourth inverter INV4 is connected to the rear, and the output signal thereof is the signal ENB inverted twice and delayed.

In this way, when the signal output terminal OUT is required to output the first low level signal VSSL, the first switch K1 is turned off and then pulled down to the first level signal VSSL, so as to prevent the output negative voltage from being pulled up by the voltage VDDH of the first high level terminal.

In some embodiments, the second conversion circuit 120 further comprises: a ninth switch K9; a first end of the ninth switch K9 is connected to the second end of the first capacitor C1, and a second end of the ninth switch K9 is connected to the second high-level end; the ninth switch K9 is turned off in the operating state and turned on in the non-operating state based on the enable signal EN. Illustratively, the control terminal of the ninth switch K9 is coupled to the first enable signal ENA.

In this way, in the non-working state, the ninth switch K9 can pull the voltage of the node C up to VDDL, so that the first capacitor C1 is charged, so that the voltage of the node C at two ends of the first capacitor is VDDL, the voltage of the node B is 0, and the second switch K2 is kept in the conducting state.

After the switch is turned to the on state, the ninth switch K9 is turned off, and the voltage across the first capacitor C1 is determined by the states of the seventh switch K7 and the eighth switch K8 and the input signal, so as to determine whether the second switch K2 is kept on or turned off.

Embodiments of the present disclosure also provide examples of:

referring to the level shifter 100 shown IN fig. 6, en is an enable terminal, IN is an input signal, OUT is an output signal, VDDL is a front stage power supply voltage, VDDH is a rear stage power supply voltage, VSS is 0 potential, VSSL is negative voltage, and t_delay is a delay unit.

The level shift circuit 200 switches the output level between VDDH and VSSL (negative voltage generated by the negative voltage module) through the switches MP3 and MN3, wherein the output switch MN3 controlling the VSSL is opened and closed independently of the VSSL, and cannot be opened because the VSSL is raised, and in the conventional cross-coupling mode, the gate of the output switch is associated with the VSSL, so that the opening speed of the switch and whether the switch can be opened are affected when the VSSL is changed. In the present application, even if vssl is raised, the raised voltage is output.

The first module 210 is configured to output a point a voltage, thereby controlling MP3 on or off. The switch MN3 is controlled by the output voltage of C1, while the charge change of C1 is controlled by EN, IN together. The second module 220 is configured to output the voltage at the point E through the capacitor C2, so as to control the switch MN8 to be turned on or off, which is independent of the input signal IN and is only related to the enable signal EN. The MN8 is used to avoid the loss of C1 charges, and may be replaced by other structures, such as other structures with large impedance. The third module 230 is a digital control module.

The following describes the operation principle of the level shift circuit 200:

first, initial stage (no signal input IN):

case one: when EN input is 0, MP3 is turned off, MN3 is turned on, and MN8 is turned on.

1. MP3: en=0, ina=1, inb=0, MN2 off, MN1 on, MP2 gate grounded, MP2 on, a VDDH, MP3 off;

2. MN8: en= 0,F =vddl, MP4 is turned on, MN4 is turned off, the gates of point E and MN7 are VDDL, MN8 and MN7 are turned on, point B and point D are grounded to 0 (vss), and at this time, the left and right sides of C2 are VDDL and 0 respectively;

3. MN3: en=0, ena=1, enb=0, i.e. ENA is VDDH, MN6 is turned on, point C is VDDL, MN5, MP5 is turned off, since b=0, MN3 is turned on, the output terminal OUT outputs VSSL, and at this time, both sides of C1 are VDDL, 0, respectively.

And a second case: when EN input is 1, MN8 is off, MP3 and MN3 remain unchanged when no signal IN is input.

1. MP3: commonly determined by the input signal IN, ina=1, inb=0, mp3 states are unchanged when there is no input signal IN;

2. MN8: en=1, f=0, mp4 off, VDDL on the left side of C2 to 0, VDDL on the right side, VDDL-at point D, MN4 on, E-at point E, MN7 gate-VDDL, MN7 off, MN8 off;

3. MN3: en=1, ena=0, enb=1, MN6 is turned off, MN5 and MP5 are turned on, VDDL changes to INA on the lower side of C1, and INA is determined by the input signals IN and EN together, and when no input signal IN is present, ina=1, that is, VDDL, C1 state is unchanged, and switch MN3 state is unchanged.

That is, in the initial stage, C1 is charged, and C1 is in the initial state.

A second, level-shift phase (enable signal "1"):

case one: when in=0 is held, the initial state is held, and the OUT terminal outputs VSSL.

1. MP3: in=0, ina=1, inb=0, mp3 state is unchanged, stay off;

2. MN3: in=0, ina=1, the C1 state is unchanged, MN3 remains on.

And a second case: in=1, MP3 is turned on, MN3 is turned off, and the OUT terminal outputs VDDH.

1. MP3: in=1, ina=0, inb=1, MN1 open, MN2 closed, point a 0, mp3 open;

2. MN3: in=1, ina=0, C1 changes from VDDL to 0 on the lower side, from 0 to-VDDL on the upper side, and MN3 breaks.

In order to make MN8 close better, fig. 6 adopts C2, and the point E becomes negative pressure through C2, so as to ensure reliable closing of MN 8. In other schemes, the E point may be set to 0 or VDDL, i.e. only the not gate and MN6 are reserved in the second module.

MN5, MP5 may also remain only one, with two switches in parallel being more reliable on the one hand, and reducing the switch impedance on the other hand, the third module does not need the ENB signal when MP5 is only.

In order to ensure the reliability of the C1, the MN8 can be disconnected before the MN5 and the MP5 are conducted, so that a delay module T_delay is added before the enable signals ENA and ENB, and the two enable signals are delayed, thereby delaying the switching time of the MN6, the MN5 and the MP5 switches. In addition, when the level of the C2 is switched, since the MN4 is conducted with a certain delay, the MN7 is also conducted briefly, so that the MN7 can be set as an inverted ratio tube, and the current can be reduced. (the inverted ratio tube is a mos tube with L > W. The resistance is larger, the current is smaller, and the inverted ratio tube is generally used for a low-power-consumption circuit.) or a resistor R1 is added to reduce the charge loss on a capacitor C2, so that the smooth inversion of MN4 is ensured.

Regarding the turn-on sequence of the switch MP3 and MN3, when the optimal sequence is out=vddh, MP3 is turned on later, and when out=vssl, MP3 is turned off first, so that negative pressure is prevented from being increased by VDDH. In this case, a delay module may be added after the third module 230 and the nand gate generate the INA to adjust the MP3 on or off.

Through the circuit in the embodiment of the disclosure, the level conversion from positive pressure to negative pressure can be realized, the negative pressure part is not provided with a cross coupling tube, the problem of the intermediate state of the level conversion is solved theoretically, and the problem of faster discharge turnover speed of the point B in the conversion process is solved by adopting the switched capacitor technology.

As shown in fig. 7, the embodiment of the present disclosure further provides a signal processing apparatus 200, including:

the level shifter circuit 210 as described above; the level shifter circuit 210 may be any of the level shifter circuits 100 of fig. 1-6.

And a load circuit 220 connected to the level shifter circuit 210.

The signal processing device 200 may be a memory, a processor, a display panel, or other electrical device requiring the use of a level shifting circuit.

It should be appreciated that reference throughout this specification to "some embodiments," "one embodiment," or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing is merely an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think about the changes or substitutions within the technical scope of the present disclosure, and should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (10)

1. A level shifter circuit, comprising:

a first switch with a first end connected to the first high level end _， The second end is connected with the signal output end of the level conversion circuit; a second switch with a first end connected to the first low level end _， The second end is connected with the signal output end of the level conversion circuit;

the input end of the first conversion circuit is respectively connected with the second high-level end and the second low-level end, and the output end of the first conversion circuit is connected with the control end of the first switch;

the first end of the first capacitor is connected with the control end of the second switch;

a blocking circuit connected to a first end of the first capacitor to block leakage of charge of the first capacitor in a charged state of the first capacitor;

and the output end of the second conversion circuit is connected with the second end of the first capacitor, and the input end of the second conversion circuit is connected with the second high-level end or the second low-level end so as to provide a first voltage or a second voltage for the first capacitor.

2. The level shifter circuit of claim 1, wherein the blocking circuit comprises:

the first end of the third switch is connected with the first end of the first capacitor, and the second end of the third switch is connected with the second low-level end; the control end of the third switch is used for receiving a changed first input level signal so as to control the third switch to release the charge of the first capacitor when being conducted, so that the second switch is turned off; or when the third switch is controlled to be turned off, the charge leakage of the first capacitor is blocked.

3. The level shifter circuit of claim 2, wherein the blocking circuit further comprises:

and the control circuit is connected with the control end of the third switch to provide the first input level signal to switch the on or off state of the third switch.

4. A level shifter circuit as set forth in claim 3 wherein said control circuit includes:

a second capacitor having a first end for receiving a varying second input level signal;

a fourth switch, the first end of which is connected with the first end of the second capacitor, and the second end of which is connected with the control end of the third switch, so that the voltage of the control end of the third switch is the same as the first end of the second capacitor;

and the first end of the fifth switch is connected with the second end of the second capacitor, and the second end of the fifth switch is connected to the control end of the third switch so that the voltage of the control end of the third switch is the same as that of the second end of the second capacitor.

5. The level shifter circuit of claim 4, wherein the control circuit further comprises: and the first end of the sixth switch is connected with the second end of the second capacitor, the second end of the sixth switch is connected with a second low level, and the second end of the second capacitor is connected with the second low level through the sixth switch.

6. The level shifter circuit of claim 5, wherein the sixth switch has a first terminal connected to the second low-level terminal, a second terminal connected to the second terminal of the second capacitor, and a control terminal connected to the second terminal of the fourth switch and the second terminal of the fifth switch; when the fourth switch is turned on, the sixth switch is turned off, so that electric leakage of the second capacitor is reduced; when the fifth switch is turned on, the sixth switch is turned on to release the charge on the second capacitor.

7. The level shifter circuit of claim 6, wherein the control circuit further comprises: and the first end of the first resistor is connected with the second end of the second capacitor, and the second end of the first resistor is connected with the first end of the sixth switch.

8. The level shift circuit according to any one of claims 4 to 7, wherein the control circuit further includes: and the input end of the first inverter is used for receiving the second input level signal, and the output end of the first inverter is connected with the first end of the second capacitor.

9. The level shifter circuit of any one of claims 4 to 7, wherein the second input level signal received at the input of the control circuit is an enable signal, the enable signal being used to indicate an active state or an inactive state of the level shifter circuit;

And the control circuit controls the third switch to be turned off when the enabling signal indicates the working state, and controls the third switch to be turned on when the enabling signal indicates the non-working state.

10. The level shifter circuit of claim 9, wherein the level shifter circuit further comprises:

an input signal terminal for receiving an input signal;

and the enabling signal end is used for receiving the enabling signal, wherein the enabling signal indicates the level conversion circuit to control the conduction of the first switch and the second switch together with the input signal when in the working state.