CN117524893A - High-lead bump chip and gold wire ball mixed flip-chip interconnection method - Google Patents

Abstract

The invention provides a high-lead bump chip and gold wire ball mixed flip-chip interconnection method, which comprises the following steps: testing coplanarity of flip-chip bonding pads; plasma cleaning of the substrate; bonding at least one layer of gold wire balls on the substrate flip bonding pad according to the coplanarity test result; plasma cleaning of the substrate; stamping high-lead salient points on the chip at positions corresponding to the gold wire balls, so that pits are formed on the surfaces of the high-lead salient points; the chip is turned over until the high lead convex points dip soldering flux downwards; the chip and the substrate are identified and aligned, so that pits on the surface of the high-lead salient point are in one-to-one correspondence with gold wire ball tail wires on the flip-chip bonding pad of the substrate, the chip moves downwards for a specified distance, and the chip is released to finish the mounting; and carrying out reflow soldering on the mounted device to complete flip-chip interconnection. The invention solves the problems that the coplanarity of the substrate flip-chip bonding pad is insufficient, the substrate warpage causes that the high lead salient point and the flip-chip bonding pad cannot be contacted to form bonding under the high temperature bonding condition, the wettability of the high lead salient point is poor, and the salient point and the bonding pad are easy to be in cold joint, thereby improving the flip-chip bonding yield.

Description

A hybrid flip-chip interconnection method of high-lead bump chips and gold balls

Technical field

The invention belongs to the technical field of electronic packaging, and particularly relates to a hybrid flip-chip interconnection method of high-lead bump chips and gold balls.

Background technique

As semiconductor integrated devices continue to develop towards high density and high performance, traditional wire bonding technology can no longer meet the demand, and flip chip soldering technology emerged as the times require. Flip-chip soldering is a technology that inverts a chip with area array bumps so that the bump side is mounted on the substrate to interconnect the chip and the substrate. It has the advantages of large number of interconnection bumps, short signal transmission distance, and mechanical strength. Advanced features are an effective way to meet high-density, high-performance packaging requirements. High-lead bumps have high Pb content and low Sn content, which can effectively avoid the problem of excessive growth of IMC (intermetallic compounds). They have the advantages of high melting point and strong remelting resistance, and are used in high-reliability flip-chip soldering devices. Encapsulation.

In recent years, the integration level of flip-chip soldering devices has been increasing, and the size of flip-chip substrates has increased and the structure of the substrate has become more complex. This has made it more difficult to control the coplanarity of flip-chip pads on the substrate, which has brought challenges to flip-chip interconnection soldering technology. bring new challenges. The coplanarity of flip-chip pads has a key influence on the quality of flip-chip welding. If the coplanarity of the pads is too large, the chip bumps and the pads will not be in contact or have poor contact during the soldering process. In addition, high-lead bumps The chip welding temperature is high, and the substrate warps seriously under high temperature conditions, and the coplanarity of the pads further increases, exacerbating the situation where the chip bumps and pads cannot form a weld or have poor welding, causing the device to open circuit during electrical testing and become unusable. Affect flip-chip welding yield.

In order to achieve effective interconnection between large-size, complex structure substrates and high-lead bump chips, the coplanarity of the flip-chip pads on the substrate needs to be compensated to reduce the co-planarity of the flip-chip pads. The current solutions to this problem mainly include pre-solder on the flip-chip pad and laser ball placement, but there are many limiting factors in both technologies. The method of presetting solder on the flip-chip pad is to print solder on the substrate pad through a printing stencil. First, the fit between the printing stencil and the substrate is poor, the amount of solder printing is difficult to control, and the amount of solder is too small. It is difficult to meet the requirement of reducing the coplanarity of the pads. Too much solder will lead to bridging of solder joints after flip-chip soldering. Second, this method requires processing of printed stencils, and the substrates are one-to-one according to the coplanarity of the flip-chip pads. Processing and adapting printing stencils is difficult and costly. For the laser ball planting method, the large coplanarity of the flip-chip pad will cause the ball spraying distance to be too long during ball planting, causing the ball planting position to shift, or the spraying ball distance to be too short, and the nozzle to be sprayed incompletely. The solder balls are blocked and damaged. In addition, during laser ball placement, the solder balls begin to cool after they fall on the flip-chip pad. There is insufficient welding time, resulting in low connection strength between the solder balls and the flip-chip pad and easy falling off.

Contents of the invention

The technical problems solved by this invention are: the coplanarity of flip-chip pads on large-size, complex-structured substrates is too large, and the welding temperature of high-lead bump chips is relatively high. During the welding process of flip-chip devices, the substrates are heated and warped, causing them to collapse. The coplanarity of the mounting pads is further increased, and the high-lead bumps of the chip cannot contact or have poor contact with the flip-chip pads, resulting in no welding or poor welding, causing the device to open circuit during electrical testing and become unusable, affecting the flip-chip welding yield.

The technical solutions provided by the invention are as follows:

A hybrid flip-chip interconnection method of high-lead bump chips and gold balls, including:

Conduct coplanarity testing of flip-chip pads on the substrate;

Perform plasma cleaning on the substrate before bonding the wire balls;

Bond one or more layers of gold wire balls on the flip-chip pad of the substrate based on the flip-chip pad coplanarity test results;

Perform plasma cleaning on the substrate before chip placement;

The high-lead bumps on the chip corresponding to the gold balls are stamped to form pits on the surface of the high-lead bumps;

Use chip flipping equipment to flip the chip so that the high-lead bumps are facing down to dip in flux;

The chip and the substrate are identified and aligned so that the pits on the surface of the high-lead bumps correspond to the gold ball tail wires on the flip-chip pad of the substrate. The chip moves down a specified distance and the chip is released to complete the mounting;

The mounted components are reflow soldered to complete chip flip-chip interconnection.

According to the hybrid flip-chip interconnection method of high-lead bump chips and gold balls provided by the present invention, it has the following beneficial effects:

(1) The present invention provides a hybrid flip-chip interconnection method of high-lead bump chips and gold wire balls. The bonding gold wire ball process has a wider compatibility range for the coplanarity of substrate flip-chip pads. Compared with the laser ball placement process, There will be no bonding position deviation or damage to equipment parts. At the same time, the truncated cone-shaped pit pad structure is adopted, so that the bonding strength between the bonded gold wire ball and the pad is better than the bonding strength of the laser ball planting;

(2) The present invention provides a hybrid flip-chip interconnection method between a high-lead bump chip and a gold ball. The tail wire of the bonded gold ball is relatively soft and is easily deformed after being pressed by the chip's high-lead bumps, thereby ensuring that the chip All high-lead bumps can fully contact with gold balls or flip-chip pads on the substrate to form good welding;

(3) The present invention provides a hybrid flip-chip interconnection method between high-lead bump chips and gold balls. The bonded gold balls do not melt during the soldering process, which avoids the excessive amount of solder caused by the preset solder method. The problem of Yiqiaolian;

(4) The present invention provides a hybrid flip-chip interconnection method between high-lead bump chips and gold balls. The gold ball bonding does not require special tooling fixtures. According to the pad coplanarity test results, on conventional bonding equipment Through programming, gold wire ball bonding at different heights in different areas can be achieved, with flexible and convenient operation and low cost.

Description of drawings

Figure 1 is a flow chart of the hybrid flip-chip interconnection method of the present invention;

2 to 6 are schematic diagrams of the hybrid flip-chip interconnection process of the present invention.

Detailed ways

By describing the present invention in detail below, the features and advantages of the present invention will become clearer and clearer with these descriptions.

The word "exemplary" as used herein means "serving as an example, example, or illustrative." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or superior to other embodiments.

The invention provides a hybrid flip-chip interconnection method of high-lead bump chips and gold balls, as shown in Figure 1, which includes the following steps:

S1, conduct coplanarity test on the flip-chip pad on the substrate;

S2, perform plasma cleaning on the substrate before bonding the wire balls;

S3, bond one or more layers of gold wire balls on the flip-chip pad of the substrate based on the flip-chip pad coplanarity test results;

S4, perform plasma cleaning on the substrate before chip placement (that is, perform plasma cleaning on the substrate after bonding the gold wire balls);

S5, use a needle array stamping device to stamp the high-lead bumps on the chip corresponding to the gold balls, so that pits are formed on the surface of the high-lead bumps;

S6, use chip flip-chip equipment to flip the chip so that the high-lead bumps face down to dip in flux;

S7, place the substrate under the chip with the flip-chip pad facing up. Use chip flip-chip equipment to align the high-lead bumps on the chip with the flip-chip pads on the substrate one by one. Move the chip downwards a certain distance so that the flip-chip pads face upward. Place the gold ball tail wire on the mounting pad into the pit on the surface of the high-lead bump to release the chip to complete mounting;

S8, transfer the mounted device to the reflow furnace for reflow soldering to complete chip flip-chip interconnection.

In step S1, the substrate is a ceramic substrate. There is a circular flip-chip pad on the substrate. There is a truncated cone-shaped pit structure in the center of the flip-chip pad. The depth of the truncated cone-shaped pit structure is 5 μm to 10 μm. The diameter of the upper surface is 30μm~40μm, the diameter of the lower surface of the truncated cone-shaped pit structure is 40μm~50μm, the surface of the flip-chip pad is gold-plated, and the thickness of the gold layer is 0.05μm~0.5μm.

In steps S2 and S4, the plasma cleaning power is 300W ~ 400W, the plasma cleaning time is 60s ~ 90s, only argon is used, and no oxygen is used. The interval between the completion of plasma cleaning before bonding and gold wire ball bonding does not exceed 60 minutes. , the interval between the completion of plasma cleaning before chip placement and the downward movement of the chip does not exceed 60 minutes.

In step S3, gold wire is used to bond gold wire balls on the truncated cone-shaped pit structure of the flip-chip pad. After bonding, the height of the single-layer gold wire ball is 25 μm to 30 μm, and the height of the gold wire ball tail wire is 5 μm to 10 μm.

The number of gold wire ball bonding layers is determined based on the coplanarity test value. The highest point of the flip-chip pad on the substrate is regarded as point 0, and a flip-chip pad with coplanarity in the 0~-40μm area is bonded with one layer of gold wire balls. Flip-chip bonding of two layers of gold wire balls with coplanarity in the area of -40μm ~ -80μm (excluding -40μm), flip chip bonding with coplanarity in the area of -80μm ~ -120μm (excluding -80μm) Pad bonding three layers of gold wire balls.

In step S5, the lead content of the high-lead bumps is greater than 80wt%, the diameter of the high-lead bumps is 100 μm to 200 μm, and the depth of the pits stamped on the surface of the high-lead bumps is 1.5 to 2 times the height of the gold ball tail wire. The diameter is 1.5 to 2 times the diameter of the gold ball tail wire.

In step S7, the chip moves downward by a distance such that the gap between the chip and the substrate is between 75%*high lead bump diameter and 85%*high lead bump diameter.

In step S8, the reflow soldering process parameters include: the reflow soldering peak temperature is 20°C to 30°C above the liquidus line of the high lead bump, the reflow time is 60s to 90s, the reflow furnace uses a nitrogen atmosphere, and the oxygen content does not exceed 200ppm.

Example

Example 1

Figures 2 to 6 are schematic diagrams of a hybrid flip-chip interconnection between a high-lead bump chip and a gold ball according to the present invention, which specifically includes:

(1) Conduct a coplanarity test on the flip-chip pad 2 on the substrate 1.

The substrate is a ceramic substrate. There is a circular flip-chip pad on the substrate. There is a truncated cone-shaped pit structure 3 in the center of the flip-chip pad. The depth of the truncated cone-shaped pit structure 3 is 8 μm. The diameter of the upper surface of the truncated cone-shaped pit structure 3 is The diameter of the lower surface of the truncated cone-shaped pit structure 3 is 45 μm, and the surface of the flip-chip pad is gold-plated with a gold layer thickness of 0.12 μm, as shown in Figure 2.

(2) Perform plasma cleaning on the substrate 1 before bonding the wire balls.

(3) Place the substrate flip-chip pad on the workbench of the bonding machine with the flip-chip pad facing up. Based on the flip-chip pad coplanarity test results, bond one to three layers on the circular cone-shaped pit 3 in the center of the flip-chip pad. Gold ball 4; after bonding, the height of the single-layer gold ball is 30 μm, and the height of the tail wire of the gold ball is 7 μm, see Figure 3.

Taking the highest point of the flip-chip pad on the substrate as point 0, the flip-chip pad has a coplanarity in the 0~-40μm area and is bonded with a layer of gold wire balls, and the coplanarity is -40μm~-80μm (excluding -40μm) The flip-chip pad in the area is bonded with two layers of gold balls, and the flip-chip pad in the area with coplanarity between -80 μm and -120 μm (excluding -80 μm) is bonded with three layers of gold balls.

(4) Perform plasma cleaning on the substrate after bonding the gold wire balls.

In steps 2 and 4, the plasma cleaning power is 350W, the plasma cleaning time is 70s, only argon is used, and no oxygen is used. The interval between the completion of plasma cleaning before bonding and gold wire ball bonding does not exceed 60 minutes, and the chip is placed. The interval between the completion of the front plasma cleaning and the downward movement of the chip shall not exceed 60 minutes.

(5) Place the high-lead bumps 6 on the chip 5 downward. The back of the chip is adsorbed and fixed on the flip-chip equipment placement head 8 through the vacuum 7. The needle end 10 of the needle array stamping device 9 faces upward. The needle array stamping device The back side is adsorbed and fixed on the flip-chip equipment base 12 through vacuum 11. After being recognized and aligned by the camera, the placement head 8 moves down 13 to a specified distance to make the chip bumps contact the pin end of the stamping tool and form pits on the bump surface. 14, see Figure 4;

The high-lead bumps are made of lead-tin alloy material with a lead content of 90wt%. The diameter of the high-lead bumps is 150 μm. The depth of the pits stamped on the surface of the high-lead bumps is twice the height of the gold ball tail wire. The diameter of the pits is gold. 2 times the diameter of the silk ball tail wire.

(6) The mounting head 8 drives the chip 5 to move to the flux tank to dip in the flux.

(7) Remove the needle array stamping device 9 and place the substrate flip-chip pad on the flip-chip equipment base 12 with the flip-chip pad facing upward. After the camera identifies and aligns it, make the bump surface pits 14 and the substrate flip-chip pad The upper gold ball tail wires 15 correspond one to one, and the chip is moved down 16 to a specified distance, so that the gap 17 between the chip and the substrate is 80% * the diameter of the highest lead bump, and the chip is released to complete the mounting, as shown in Figure 5.

(8) Transfer the chip-mounted devices to the reflow furnace for reflow soldering. The peak temperature of the reflow soldering is 20°C above the liquidus line of the high-lead bumps. The reflow time is 70 seconds. The reflow furnace uses a nitrogen atmosphere and the oxygen content does not exceed 200ppm. , the high-lead bumps are in contact with the flip-chip pad of the substrate to form good solder joints 18, see Figure 6.

The substrate size of the verification device is 62mm*62mm, and the number of flip-chip pads is 5,000. After direct flip-chip welding of high-lead bump chips and substrate pads, the device electrical connection test result is about 20% pin path (approximately If 20% of the bumps and pads are effectively interconnected), the device is unqualified; after using this method, the electrical connection test result of the flip-chip soldering device is 100% via (all bumps and pads are effectively interconnected), and the device is qualified.

Example 2

Figures 2 to 6 are schematic diagrams of a hybrid flip-chip interconnection between a high-lead bump chip and a gold ball according to the present invention, which specifically includes:

(1) Conduct a coplanarity test on the flip-chip pad 2 on the substrate 1.

The substrate is a ceramic substrate. There is a circular flip-chip pad on the substrate. There is a truncated cone-shaped pit structure 3 in the center of the flip-chip pad. The depth of the truncated cone-shaped pit structure 3 is 6 μm. The upper surface diameter of the truncated cone-shaped pit structure 3 is The diameter of the lower surface of the truncated cone-shaped pit structure 3 is 47 μm, and the surface of the flip-chip pad is gold-plated with a gold layer thickness of 0.15m, as shown in Figure 2.

(2) Perform plasma cleaning on the substrate 1 before bonding the wire balls.

(3) Place the substrate flip-chip pad on the workbench of the bonding machine with the flip-chip pad facing up. Based on the flip-chip pad coplanarity test results, bond one to three layers on the circular cone-shaped pit 3 in the center of the flip-chip pad. Gold ball 4; after bonding, the height of the single-layer gold ball is 25 μm, and the height of the tail wire of the gold ball is 10 μm, see Figure 3.

Taking the highest point of the flip-chip pad on the substrate as point 0, the flip-chip pad has a coplanarity in the 0~-40μm area and is bonded with a layer of gold wire balls, and the coplanarity is -40μm~-80μm (excluding -40μm) The flip-chip pad in the area is bonded with two layers of gold balls, and the flip-chip pad in the area with coplanarity between -80 μm and -120 μm (excluding -80 μm) is bonded with three layers of gold balls.

(4) Perform plasma cleaning on the substrate after bonding the gold wire balls.

In steps 2 and 4, the plasma cleaning power is 350W, the plasma cleaning time is 70s, only argon is used, and no oxygen is used. The interval between the completion of plasma cleaning before bonding and gold wire ball bonding does not exceed 60 minutes, and the chip is placed. The interval between the completion of the front plasma cleaning and the downward movement of the chip shall not exceed 60 minutes.

(5) Place the high-lead bumps 6 on the chip 5 downward. The back of the chip is adsorbed and fixed on the flip-chip equipment placement head 8 through the vacuum 7. The needle end 10 of the needle array stamping device 9 faces upward. The needle array stamping device The back side is adsorbed and fixed on the flip-chip equipment base 12 through vacuum 11. After being recognized and aligned by the camera, the placement head 8 moves down 13 to a specified distance to make the chip bumps contact the pin end of the stamping tool and form pits on the bump surface. 14, see Figure 4;

The high-lead bumps are alloy materials with a lead content of 90wt%. The diameter of the high-lead bumps is 150 μm. The depth of the pits stamped on the surface of the high-lead bumps is 1.5 times the height of the tail wire of the gold wire ball. The diameter of the pits is 150 μm. 1.5 times the diameter of the tail filament.

(6) The mounting head 8 drives the chip 5 to move to the flux tank to dip in the flux.

(7) Remove the needle array stamping device 9 and place the substrate flip-chip pad on the flip-chip equipment base 12 with the flip-chip pad facing upward. After the camera identifies and aligns it, make the bump surface pits 14 and the substrate flip-chip pad The upper gold ball tail wires 15 correspond one to one, and the chip is moved down 16 to a specified distance, so that the gap 17 between the chip and the substrate is 80% * the diameter of the highest lead bump, and the chip is released to complete the mounting, as shown in Figure 5.

(8) Transfer the chip-mounted devices to the reflow furnace for reflow soldering. The peak temperature of the reflow soldering is 20°C above the liquidus line of the high-lead bumps. The reflow time is 70 seconds. The reflow furnace uses a nitrogen atmosphere and the oxygen content does not exceed 200ppm. , the high-lead bumps are in contact with the flip-chip pad of the substrate to form good solder joints 18, see Figure 6.

The substrate size of the verification device is 62mm*62mm, and the number of flip-chip pads is 5,000. After direct flip-chip welding of high-lead bump chips and substrate pads, the device electrical connection test result is about 20% pin path (approximately If 20% of the bumps and pads are effectively interconnected), the device is unqualified; after using this method, the electrical connection test result of the flip-chip soldering device is 100% via (all bumps and pads are effectively interconnected), and the device is qualified.

The present invention has been described in detail above with reference to specific embodiments and exemplary examples. However, these descriptions should not be construed as limitations of the present invention. Those skilled in the art understand that without departing from the spirit and scope of the invention, various equivalent substitutions, modifications or improvements can be made to the technical solution and its implementation of the invention, and these all fall within the scope of the invention. The scope of protection of the present invention is determined by the appended claims.

Contents not described in detail in the specification of the present invention are well-known technologies to those skilled in the art.

Claims (10)

1. The high-lead bump chip and gold wire ball mixed flip-chip interconnection method is characterized by comprising the following steps of:

carrying out coplanarity test on the flip-chip bonding pads on the substrate;

performing plasma cleaning before bonding alloy wire balls on a substrate;

bonding one or more layers of gold wire balls on the flip-chip bonding pad of the substrate according to the flip-chip bonding pad coplanarity test result;

plasma cleaning is carried out on the substrate before chip attaching;

stamping high-lead salient points on the chip at positions corresponding to the gold wire balls, so that pits are formed on the surfaces of the high-lead salient points;

flip chip equipment is used for flip chip until the high lead bumps dip soldering flux downwards;

the chip and the substrate are identified and aligned, so that pits on the surface of the high-lead salient point are in one-to-one correspondence with gold wire ball tail wires on the flip-chip bonding pad of the substrate, the chip moves downwards for a specified distance, and the chip is released to finish the mounting;

and carrying out reflow soldering on the mounted device to complete flip-chip interconnection.

2. The method of mixed flip-chip interconnection of high lead bump chip and gold wire ball according to claim 1, wherein in the step of testing coplanarity of flip-chip bonding pads on a substrate, a truncated cone-shaped pit structure is arranged at the center of each flip-chip bonding pad.

3. The method for flip chip interconnection of high lead bump chip and gold wire ball mixture as claimed in claim 2, wherein in the step of testing coplanarity of flip chip bonding pads on the substrate, the depth of the truncated cone-shaped pit structure is 5 μm-10 μm, the diameter of the upper surface of the truncated cone-shaped pit structure is 30 μm-40 μm, and the diameter of the lower surface of the truncated cone-shaped pit structure is 40 μm-50 μm.

4. The method of mixed flip-chip interconnection of high lead bump chip and gold wire ball according to claim 1, wherein in the step of testing coplanarity of flip-chip bonding pads on a substrate, the surface of the flip-chip bonding pads is gold-plated, and the thickness of the gold layer is 0.05 μm to 0.5 μm.

5. The method for mixed flip-chip interconnection of high-lead bump chips and gold wire balls according to claim 1, wherein in the step of performing plasma cleaning before bonding the alloy wire balls on the substrate, the plasma cleaning power is 300-400W, the plasma cleaning time is 60-90 s, argon is only used, oxygen is not used, and the interval time from the completion of plasma cleaning before bonding to the bonding of the gold wire balls is not more than 60min.

6. The method for mixed flip-chip interconnection of high-lead bump chips and gold wire balls according to claim 2, wherein in the step of bonding one or more layers of gold wire balls on the flip-chip bonding pad of the substrate according to the test result of coplanarity of the flip-chip bonding pad, gold wires are adopted to bond the alloy wire balls on the truncated cone-shaped pit structure of the flip-chip bonding pad, the height of the single-layer gold wire balls after bonding is 25-30 μm, and the height of the tail wires of the gold wire balls is 5-10 μm.

7. The method according to claim 1, wherein in the step of bonding one or more gold wire balls on the flip-chip pad of the substrate according to the result of the coplanarity test of the flip-chip pad, the number of gold wire ball bonding layers is determined according to the coplanarity test value, the highest point of the flip-chip pad of the substrate is taken as 0 point, the flip-chip pad with coplanarity within the range of 0 to-40 μm bonds one layer of gold wire balls, the coplanarity within the range of-40 μm to-80 μm bonds two layers of gold wire balls without-40 μm flip-chip pad, and the coplanarity within the range of-80 μm to-120 μm bonds three layers of gold wire balls without-80 μm flip-chip pad bonding.

8. The method for mixed flip-chip interconnection of high-lead bump chips and gold wire balls according to claim 1, wherein in the step of plasma cleaning the substrate before chip placement, the plasma cleaning power is 300-400W, the plasma cleaning time is 60-90 s, argon is only used, oxygen is not used, and the interval time from the completion of plasma cleaning before chip placement to the downward movement of the chips is not more than 60min.

9. The method for mixed flip-chip interconnection of a high-lead bump chip and a gold wire ball according to claim 1, wherein in the step of stamping the high-lead bump on the chip at a position corresponding to the gold wire ball to form a pit on the surface of the high-lead bump, the diameter of the high-lead bump is 100 μm-200 μm, preferably the depth of the stamped pit on the surface of the high-lead bump is 1.5-2 times the height of a tail wire of the gold wire ball, and the diameter of the pit is 1.5-2 times the diameter of the tail wire of the gold wire ball.

10. The method for mixed flip-chip interconnection of high-lead bump chip and gold wire ball according to claim 1, wherein the chip and the substrate are aligned by identification, so that pits on the surface of the high-lead bump and gold wire ball tail wires on the flip-chip bonding pad of the substrate are in one-to-one correspondence, the chip is moved downwards by a specified distance, and in the step of releasing the chip to complete the mounting, the chip is moved downwards by the specified distance: and enabling a gap between the chip and the substrate to be between 75% and 85% of the high lead bump diameter.