CN117524847A - Debugging method of high-flatness epitaxial wafer - Google Patents
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- CN117524847A CN117524847A CN202311407409.0A CN202311407409A CN117524847A CN 117524847 A CN117524847 A CN 117524847A CN 202311407409 A CN202311407409 A CN 202311407409A CN 117524847 A CN117524847 A CN 117524847A
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Abstract
The invention relates to a debugging method of a high-flatness epitaxial wafer, which belongs to the technical field of silicon wafer processing and comprises the following operation steps: the first step: the front morphology is mostly bowl-shaped, namely the edge is upwarped with depth, which results in poorer ESFQR. And a second step of: changing the power of the lamp tube in the process of epitaxial technology processing, heating the silicon wafer from 750 ℃ to 900 ℃, then heating to 1130 ℃ and preserving heat for 45 seconds to enable the film to grow on the silicon surface to 2um; and growing an epitaxial layer on the surface of the polished wafer through an epitaxial deposition reaction to prepare the epitaxial wafer. And a third step of: then the temperature is reduced from 1130 ℃ to 900 ℃; and depositing a thin film layer on the surface of the epitaxial layer of the epitaxial wafer by using a physical vapor deposition method. Fourth step: and removing the thin film layer and the local epitaxial layer on the surface of the epitaxial wafer by using a plasma etching method. Has the characteristics of convenient operation and good improvement effect. The epitaxial wafer with negative flatness increment and high flatness can be obtained by adjusting the power of the epitaxial lamp tube, which is more beneficial to the production of the following semiconductor chips.
Description
Technical Field
The invention relates to the technical field of silicon wafer processing, in particular to a debugging method of a high-flatness epitaxial wafer.
Background
The silicon epitaxial wafer is used for growing an epitaxial monocrystalline silicon film on the polished silicon wafer by adopting a chemical vapor deposition method, so that the improvement and control of the surface quality and the conductivity of the silicon wafer are realized. The epitaxial wafer is a necessity of a middle-stage process and a back-stage process of the chip, a high-performance semiconductor cannot be manufactured without the epitaxial wafer, and the flatness of the epitaxial wafer is an important performance index, which is important for producing the semiconductor chip.
The problem that the flatness of the epitaxial wafer is low is generally existed in the epitaxial wafer produced at present, the flatness requirement of the epitaxial wafer is more and more strict along with the increase of company clients and product specifications, and various debugging tests and data summarization find out that the process parameters influencing the flatness of the epitaxial wafer are quite large, so that how to debug the epitaxial wafer with high flatness by adjusting different process parameters, so that the flatness of the epitaxial wafer meets the client requirements, and the epitaxial wafer becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention mainly solves the defects existing in the prior art, and provides a debugging method of a high-flatness epitaxial wafer, which has the characteristics of convenience in operation and good improvement effect. The epitaxial wafer with negative flatness increment and high flatness can be obtained by adjusting the power of the epitaxial lamp tube, which is more beneficial to the production of the following semiconductor chips.
The technical problems of the invention are mainly solved by the following technical proposal:
a debugging method of a high-flatness epitaxial wafer comprises the following operation steps:
the first step: epitaxial wafers with high flatness are prepared by selecting polished wafers with stable morphology, and most of front-value morphology is bowl-shaped, namely edges are tilted upwards and have depth, so that ESFQR is poor.
And a second step of: changing the power of the lamp tube in the process of epitaxial technology processing, heating the silicon wafer from 750 ℃ to 900 ℃, then heating to 1130 ℃ and preserving heat for 45 seconds to enable the film to grow on the silicon surface to 2um; and growing an epitaxial layer on the surface of the polished wafer through an epitaxial deposition reaction to prepare the epitaxial wafer.
And a third step of: then the temperature is reduced from 1130 ℃ to 900 ℃; and depositing a thin film layer on the surface of the epitaxial layer of the epitaxial wafer by using a physical vapor deposition method.
Fourth step: and removing the thin film layer and the local epitaxial layer on the surface of the epitaxial wafer by using a plasma etching method.
The plasma etching method adopts a plasma etching machine to generate plasma by using high-energy electron bombardment gas, and the processing of the material surface is realized by using the chemical reaction characteristic of the plasma etching machine. A plasma is a charged gas system in which electrons, ions, atoms and molecules interact to produce various chemical reactions.
The plasma in a plasma etcher can be generated in two ways, one is a radio frequency eddy current discharge and the other is a microwave power discharge. The radio frequency eddy current discharge is that under the action of radio frequency electric field, gas is heated to become plasma, and the discharge work is stable, but high density plasma can not be realized. Microwave power discharge can produce a higher density, more reactive plasma, but the operation is less stable.
Preferably, in the epitaxial process, the increment of ESFQR of ARC1.2:1 is obviously reduced by comparing the ratio of the power of the upper row to the power of the lower row (ARC) 1:1 with the ratio of the power of the upper row to the power of the lower row (ARC) 1.2:1, and the graph shows that the edge is more gentle, so that better flatness data are obtained.
Preferably, the method for performing thin film layer deposition is an epitaxial deposition method, and the process of adjusting the deposition parameters of the reference thin film layer based on the surface flatness data of the epitaxial wafer to obtain the preset deposition parameters is performed.
Preferably, the center of the circle of the epitaxial wafer is defined as more than two areas from inside to outside, thickness data of each area is obtained, the thickness data of each area is compared with target thickness data to obtain a difference value, and deposition time and power of each area are adjusted based on the difference value.
The invention can achieve the following effects:
compared with the prior art, the debugging method of the high-flatness epitaxial wafer has the characteristics of convenience in operation and good improvement effect. The epitaxial wafer with negative flatness increment and high flatness can be obtained by adjusting the power of the epitaxial lamp tube, which is more beneficial to the production of the following semiconductor chips.
Detailed Description
The technical scheme of the invention is further specifically described by the following examples.
Examples: a debugging method of a high-flatness epitaxial wafer comprises the following operation steps:
the first step: epitaxial wafers with high flatness are prepared by selecting polished wafers with stable morphology, and most of front-value morphology is bowl-shaped, namely edges are tilted upwards and have depth, so that ESFQR is poor.
And a second step of: the power of the lamp tube is changed in the process of the epitaxial process, and in the process of the epitaxial process, the ratio of the power ratio (ARC) of the upper row to the lower row lamp tube is 1:1 and the ratio of the power ratio (ARC) of the upper row to the lower row lamp tube is 1.2:1, the increment of ESFQR of the ARC1.2:1 is obviously reduced, and the graph shows that the edge is flatter, so that better flatness data are obtained. The silicon wafer is heated from 750 ℃ to 900 ℃, then heated to 1130 ℃ and kept for 45 seconds, so that the film grows to 2um on the surface of the silicon wafer. And growing an epitaxial layer on the surface of the polished wafer through an epitaxial deposition reaction to prepare the epitaxial wafer.
And a third step of: then the temperature is reduced from 1130 ℃ to 900 ℃; and depositing a thin film layer on the surface of the epitaxial layer of the epitaxial wafer by using a physical vapor deposition method.
The method for depositing the film layer is an epitaxial deposition method, and the process of adjusting the deposition parameters of the reference film layer based on the surface flatness data of the epitaxial wafer to obtain preset deposition parameters. And defining more than two areas from inside to outside by taking the center of the circle of the epitaxial wafer as the center, obtaining thickness data of each area, comparing the thickness data of each area with target thickness data to obtain a difference value, and adjusting the deposition time and power of each area based on the difference value.
Fourth step: and removing the thin film layer and the local epitaxial layer on the surface of the epitaxial wafer by using a plasma etching method. The plasma etching method is a plasma chemical vapor etching method.
In conclusion, the debugging method of the high-flatness epitaxial wafer has the characteristics of convenience in operation and good improvement effect. The epitaxial wafer with negative flatness increment and high flatness can be obtained by adjusting the power of the epitaxial lamp tube, which is more beneficial to the production of the following semiconductor chips.
The above embodiments are merely examples of the present invention, but the present invention is not limited thereto, and any changes or modifications made by those skilled in the art are included in the scope of the present invention.
Claims (4)
1. The debugging method of the high-flatness epitaxial wafer is characterized by comprising the following operation steps of:
the first step: preparing an epitaxial wafer with high flatness by selecting a polished wafer with stable morphology, wherein most of front morphology is bowl-shaped, namely the edge of the epitaxial wafer is tilted upwards to have depth, so that ESFQR is poor;
and a second step of: changing the power of the lamp tube in the process of epitaxial technology processing, heating the silicon wafer from 750 ℃ to 900 ℃, then heating to 1130 ℃ and preserving heat for 45 seconds to enable the film to grow on the silicon surface to 2um; growing an epitaxial layer on the surface of the polished wafer through an epitaxial deposition reaction to prepare an epitaxial wafer;
and a third step of: then the temperature is reduced from 1130 ℃ to 900 ℃; depositing a thin film layer on the surface of the epitaxial layer of the epitaxial wafer by using a physical vapor deposition method;
fourth step: and removing the thin film layer and the local epitaxial layer on the surface of the epitaxial wafer by using a plasma etching method.
2. The method for debugging a high-flatness epitaxial wafer of claim 1, wherein: in the epitaxial process, the ratio of the power ratio (ARC) of the upper row to the lower row of lamp tubes (ARC) 1:1 is compared with the ratio of the power ratio (ARC) of the upper row to the lower row of lamp tubes (ARC) 1.2:1, the increment of ESFQR of the ARC1.2:1 is obviously reduced, and the graph shows that the edge is flatter, and better flatness data are obtained.
3. The method for debugging a high-flatness epitaxial wafer of claim 1, wherein: the method for depositing the film layer is an epitaxial deposition method, and the process of adjusting the deposition parameters of the reference film layer based on the surface flatness data of the epitaxial wafer to obtain preset deposition parameters.
4. The method for debugging a high-flatness epitaxial wafer of claim 3, wherein: and defining more than two areas from inside to outside by taking the center of the circle of the epitaxial wafer as the center, obtaining thickness data of each area, comparing the thickness data of each area with target thickness data to obtain a difference value, and adjusting the deposition time and power of each area based on the difference value.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118136497A (en) * | 2024-05-08 | 2024-06-04 | 西安奕斯伟材料科技股份有限公司 | Epitaxial silicon wafer and method for manufacturing the same |
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2023
- 2023-10-27 CN CN202311407409.0A patent/CN117524847A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118136497A (en) * | 2024-05-08 | 2024-06-04 | 西安奕斯伟材料科技股份有限公司 | Epitaxial silicon wafer and method for manufacturing the same |
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