CN117497585B - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN117497585B CN117497585B CN202311843701.7A CN202311843701A CN117497585B CN 117497585 B CN117497585 B CN 117497585B CN 202311843701 A CN202311843701 A CN 202311843701A CN 117497585 B CN117497585 B CN 117497585B
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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Abstract
The invention discloses a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises: a substrate; the semiconductor epitaxial layer is positioned on one side of the substrate; the semiconductor epitaxial layer is internally provided with a heterojunction of two-dimensional electron gas; the semiconductor epitaxial layer comprises a gate region and drift regions positioned on two opposite sides of the gate region; a gate structure located in a gate region of the semiconductor epitaxial layer; a spacer layer located in the drift region of the semiconductor epitaxial layer; a silicon element supply layer located on a side of the spacer layer away from the substrate; a barrier layer positioned on one side of the gate structure away from the substrate and on the side wall of the gate structure; the barrier layer is used for blocking the diffusion of silicon in the silicon element supply layer to the gate structure. The technical scheme provided by the invention effectively improves the concentration of the 2DEG, reduces the on-resistance, improves the working efficiency of the device, and reduces the probability of gate leakage.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
Nitride-based semiconductor devices utilize a heterojunction interface between two materials having different bandgaps to form a quantum well-like structure that accommodates a two-dimensional electron gas region, thereby meeting the requirements of high power/frequency devices.
Nevertheless, there are still some reliability issues that are of concern. Fig. 1 is a schematic cross-sectional structure of a semiconductor device provided in the prior art, and referring to fig. 1, the semiconductor device includes a first nitride semiconductor layer 1 and a second nitride semiconductor layer 2 having different band gaps, a gate structure 4 is disposed on the second nitride semiconductor layer 2, and a SiN passivation layer 3 is disposed on a surface of the gate structure and a surface of the second nitride semiconductor layer 2. The Si content in the SiN passivation layer 3 affects the performance of the semiconductor device. If the Si content in the SIN is high, si diffuses toward the gate structure 4, and gate leakage is formed in the sidewall region of the gate structure 4; if the Si content in SIN is low, si cannot be effectively diffused downward, and thus the concentration of 2DEG (Two Dimensional Electron Gas, two-dimensional electron gas) cannot be effectively increased. Therefore, how to effectively increase the concentration of the 2DEG to reduce the on-resistance, improve the working efficiency of the device, and reduce the probability of gate leakage is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the invention provides a semiconductor device and a preparation method thereof, which are used for effectively improving the concentration of 2DEG, reducing on-resistance, improving the working efficiency of the device and reducing the probability of gate leakage.
According to an aspect of the present invention, there is provided a semiconductor device including:
a substrate;
a semiconductor epitaxial layer located on one side of the substrate; the semiconductor epitaxial layer is internally provided with a heterojunction of two-dimensional electron gas; the semiconductor epitaxial layer comprises a grid electrode region and drift regions positioned on two opposite sides of the grid electrode region;
the grid structure is positioned in a grid region of the semiconductor epitaxial layer;
a spacer layer located in the drift region of the semiconductor epitaxial layer;
a silicon element supply layer located on a side of the spacer layer away from the substrate;
a barrier layer positioned on one side of the gate structure away from the substrate and on the side wall of the gate structure; the barrier layer is used for blocking diffusion of silicon in the silicon element supply layer to the gate structure.
Optionally, a vertical projection of the silicon element supply layer on the semiconductor epitaxial layer is located in a drift region of the semiconductor epitaxial layer;
and the area of the vertical projection of the silicon element supply layer on the semiconductor epitaxial layer is smaller than or equal to the area of the vertical projection of the spacing layer on the semiconductor epitaxial layer.
Optionally, the spacer layer is further located on a side of the gate structure away from the substrate and on a sidewall of the gate structure;
and spacer layers located on a side of the gate structure remote from the substrate and on sidewalls of the gate structure are between the barrier layer and the gate structure.
Optionally, the material of the barrier layer includes silicon oxide; the material of the silicon element supply layer is silicon.
Optionally, the material of the spacer layer includes silicon nitride; and the silicon content of the material of the spacer layer is 20% -40%.
Optionally, the semiconductor device further includes:
a strained layer between the spacer layer and the semiconductor epitaxial layer, and between the spacer layer and the gate structure; and the strain layer covers the surface of the semiconductor epitaxial layer and the surface of the gate structure; wherein the material of the strained layer comprises aluminum nitride.
Optionally, the semiconductor device further includes a source electrode and a drain electrode, which are located on a side of the semiconductor epitaxial layer away from the substrate; and the source electrode and the drain electrode are positioned on opposite sides of the gate structure;
wherein the silicon element supply layer is located between the gate structure and the drain electrode and between the gate structure and the source electrode.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a semiconductor epitaxial layer on one side of the substrate; the semiconductor epitaxial layer is internally provided with a heterojunction of two-dimensional electron gas; the semiconductor epitaxial layer comprises a grid electrode region and drift regions positioned on two opposite sides of the grid electrode region;
forming a grid structure in a grid region of the semiconductor epitaxial layer;
forming a spacer layer in the drift region of the semiconductor epitaxial layer;
forming a barrier layer on one side of the gate structure away from the substrate and on the side wall of the gate structure;
forming a silicon element supply layer on a side of the spacer layer away from the substrate; the barrier layer is used for blocking silicon in the silicon element supply layer from diffusing to the gate structure.
Optionally, when forming a spacer in the drift region of the semiconductor epitaxial layer, the method further includes:
forming a spacer layer on one side of the gate structure away from the substrate and on the side wall of the gate structure;
forming a barrier layer on a side of the gate structure away from the substrate and on a side wall of the gate structure, including:
depositing a silicon oxide material on the surface of one side of the spacer layer away from the substrate to form the barrier layer, and etching away the barrier layer positioned in the drift region to expose the spacer layer;
forming a silicon element supply layer on a side of the spacer layer away from the substrate, comprising:
and depositing a silicon material on the surface of the side, away from the substrate, of the barrier layer and the exposed surface of the spacing layer to form a silicon element supply layer, and etching the silicon element supply layer on the side, away from the substrate, of the barrier layer.
Optionally, after the gate region of the semiconductor epitaxial layer forms the gate structure, the method further includes:
forming a strain layer on the surface of the semiconductor epitaxial layer and the surface of the gate structure; wherein the material of the strained layer comprises aluminum nitride; the spacer layer is located on a side of the strained layer remote from the substrate.
The beneficial effects are that: the embodiment of the invention provides a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises: a substrate; the semiconductor epitaxial layer is positioned on one side of the substrate; the semiconductor epitaxial layer is internally provided with a heterojunction of two-dimensional electron gas; the semiconductor epitaxial layer comprises a gate region and drift regions positioned on two opposite sides of the gate region; a gate structure located in a gate region of the semiconductor epitaxial layer; a spacer layer located in the drift region of the semiconductor epitaxial layer; a silicon element supply layer located on a side of the spacer layer away from the substrate; a barrier layer positioned on one side of the gate structure away from the substrate and on the side wall of the gate structure; the barrier layer is used for blocking the diffusion of silicon in the silicon element supply layer to the gate structure. According to the technical scheme provided by the embodiment of the invention, the silicon element supply layer and the barrier layer are arranged separately, and silicon can be provided for the semiconductor epitaxial layer of the drift region through the silicon element supply layer with high silicon element content, so that the concentration of 2DEG is effectively improved, the on-resistance is reduced, and the working efficiency of a device is improved; the side wall and the upper surface of the gate structure are wrapped by the blocking layer with good silicon blocking property, so that silicon in the blocking silicon element supply layer is prevented from diffusing to the gate structure, and the probability of gate leakage can be effectively reduced.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional structure of a semiconductor device provided in the prior art;
fig. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of another semiconductor device according to an embodiment of the present invention;
fig. 4 is a top view of a semiconductor device according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of the structure of FIG. 4 along section line AA 1;
fig. 6 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 7 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 8 to 13 are schematic cross-sectional views of steps S220 to S260 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 14 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 15 to 19 are schematic cross-sectional views of steps S340 to S370 in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
An embodiment of the present invention provides a semiconductor device, and fig. 2 is a schematic cross-sectional structure of the semiconductor device provided in the embodiment of the present invention, and referring to fig. 2, the semiconductor device includes:
a substrate 10;
a semiconductor epitaxial layer 20 located on one side of the substrate 10; wherein the semiconductor epitaxial layer 20 has a heterojunction of two-dimensional electron gas therein; the semiconductor epitaxial layer 20 includes a gate region Q1 and drift regions Q2 located on opposite sides of the gate region Q1;
a gate structure 30 located in the gate region Q1 of the semiconductor epitaxial layer 20;
a spacer layer 40 located at least in the drift region Q2 of the semiconductor epitaxial layer 20;
a silicon element supply layer 50 on a side of the spacer layer 40 of the drift region Q2 remote from the substrate 10;
a barrier layer 60 on a side of the gate structure 30 remote from the substrate 10 and on sidewalls of the gate structure 30; the barrier layer 60 is used to block diffusion of silicon in the elemental silicon feed layer 50 toward the gate structure 30.
In particular, the substrate 10 may be a semiconductor substrate. The material of the substrate 10 may include, but is not limited to Si, siGe, siC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor-on-insulator (such as silicon-on-insulator (SOI) or other suitable substrate 10 materials, in some embodiments the substrate 10 may include, for example, but not limited to, a group III element, a group IV element, a group V element, or a combination thereof (e.g., a III-V compound).
In some embodiments, the substrate 10 may include a buffer layer that may be in contact with the semiconductor epitaxial layer 20, the buffer layer to reduce lattice and thermal mismatch between the substrate 10 and the semiconductor epitaxial layer 20, thereby addressing defects due to mismatch/variance. The buffer layer may comprise a III-V compound. The III-V compounds may include, but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Thus, exemplary materials for the buffer layer may further include, for example, but are not limited to GaN, alN, alGaN, inAlGaN, or combinations thereof. In some embodiments, the substrate 10 may further include a nucleation layer. The nucleation layer may be formed under the buffer layer. The nucleation layer is used to provide a transition to accommodate the mismatch/difference between the substrate 10 and the III-nitride layer of the buffer layer. Exemplary materials for the nucleation layer may include, but are not limited to, any of AlN or an alloy thereof.
The semiconductor epitaxial layer 20 may include a first nitride semiconductor layer 21 and a second nitride semiconductor layer 22. The first nitride semiconductor layer 21 is located on one side of the substrate 10, and the second nitride semiconductor layer 22 is located on one side of the first nitride semiconductor layer 21 away from the substrate 10, and has a band gap different from that of the first nitride semiconductor layer 21. There is a heterojunction of two-dimensional electron gas between the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22. The material of the first nitride semiconductor layer 21 may include, but is not limited to, nitrides or III-V compounds, such as GaN, alN, inN, inxAlyGa (1-x-y) N (where x+y.ltoreq.1), alyGa (1-y) N (where y.ltoreq.1). The material of the second nitride semiconductor layer 22 may include, but is not limited to, a group III-V nitride semiconductor material, such as GaN, alGaN, inN, alInN, inGaN, alInGaN, or a combination thereof. The band gap (i.e., the forbidden band width) of the material of the first nitride semiconductor layer 21 and the band gap of the material of the second nitride semiconductor layer 22 are selected to be different from each other so that the electron affinities are different from each other and a heterojunction is formed therebetween.
The band gap of the material of the first nitride semiconductor layer 21 is set to be smaller than that of the material of the second nitride semiconductor layer 22, for example, the first nitride semiconductor layer 21 may be selected to be a GaN layer having a band gap of about 3.4eV, and the second nitride semiconductor layer 22 may be selected to be an AlGaN layer having a band gap of about 4.0 eV, whereby the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22 may function as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the junction interface between the channel layer and the barrier layer such that electrons accumulate in the triangular well, thereby creating a two-dimensional electron gas (2 DEG) region adjacent to the heterojunction. Accordingly, the nitride-based semiconductor device can include at least one GaN-based high-resistance mobility transistor (HEMT). It should be noted that the formation of the 2DEG region is positively correlated to the degree of polarization effect between the channel and the barrier layer.
A gate structure 30 is disposed on/over/on the semiconductor epitaxial layer 20. The gate structure 30 includes a doped III-V semiconductor layer 31 and a gate electrode 32. A doped III-V semiconductor layer is disposed on and in contact with semiconductor epitaxial layer 20. A doped III-V semiconductor layer 31 is disposed/sandwiched between the semiconductor epitaxial layer 20 and the gate electrode 32. A gate electrode 32 is disposed on and in contact with the doped III-V semiconductor layer 31. The doped III-V semiconductor layer 31 may be a p-type doped III-V semiconductor layer. Exemplary materials for doped III-V semiconductor layer 31 may include, for example, but are not limited to, p-doped III-V nitride semiconductor materials such as p-type gallium nitride, p-type aluminum gallium nitride, p-type indium nitride, p-type aluminum indium nitride, p-type indium gallium nitride, p-type aluminum indium gallium nitride, or combinations thereof. In some embodiments, the p-type doping material is implemented by using p-type impurities, such as beryllium (Be), zinc (Zn), cadmium (Cd), and magnesium (Mg). Exemplary materials for gate electrode 32 may include metals or metal compounds. The gate electrode 32 may be formed as a single layer or multiple layers having the same or different compositions. Exemplary materials for the metal or metal compound may include, for example, but are not limited to, tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), metal alloys or compounds thereof, or other metal compounds.
The spacer layer 40 is located at least in the drift region Q2 of the semiconductor epitaxial layer 20, and the silicon element supply layer 50 is located on the side of the spacer layer 40 of the drift region Q2 remote from the substrate 10. The silicon element supply layer 50 contains silicon, and the silicon content is greater than a preset value. After the subsequent heat treatment, the silicon in the silicon element supply layer 50 continuously diffuses toward the interface between the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22 through the spacer layer 40, so that the concentration of 2DEG is effectively increased, the on-resistance is reduced, and the working efficiency of the device is improved. The spacer layer 40 serves to prevent the silicon element supply layer 50 from directly contacting the semiconductor epitaxial layer 20, thereby preventing chemical reaction between the silicon element supply layer 50 and the semiconductor epitaxial layer 20, and causing loss of the silicon that is movably diffused in the silicon element supply layer 50. The barrier layer 60 wraps the sidewall and the upper surface of the gate structure 30, and the silicon in the silicon element supply layer 50 can be effectively prevented from diffusing to the gate structure 30 by the barrier layer 60 with good silicon barrier property, so that the probability of gate leakage is reduced.
According to the semiconductor device provided by the embodiment of the invention, the silicon element supply layer 50 and the barrier layer 60 are arranged separately, and silicon is provided for the semiconductor epitaxial layer 20 of the drift region Q2 through the silicon element supply layer 50 with high silicon element content, so that the 2DEG concentration is effectively improved, the on-resistance is reduced, and the working efficiency of the device is improved; the barrier layer 60 with good silicon barrier property wraps the side wall and the upper surface of the gate structure 30, so that silicon in the barrier silicon element supply layer 50 is prevented from diffusing to the gate structure 30, and the probability of gate leakage can be effectively reduced.
On the basis of the above embodiments, referring to fig. 2, in one embodiment of the present invention, the material of the barrier layer 60 includes silicon oxide; the material of the elemental silicon feed layer 50 is silicon.
Specifically, the silicon element supply layer 50 is a pure silicon layer, so that the silicon content of the silicon element supply layer 50 can be maximized, the 2DEG concentration can be further improved, the on-resistance is reduced, and the working efficiency of the device is improved. Pure silicon layers in devices can be grown in batches by using furnace tubes, and pure silicon layers in single-chip microcomputer single-growth devices can also be used. The silicon in the silicon element supply layer 50 may be amorphous silicon or polycrystalline silicon. Can be set according to actual needs. Silicon oxide (SiO) 2 ) The silicon oxide layer is used as the barrier layer 60, so that the silicon in the barrier silicon element supply layer 50 can be further prevented from diffusing to the gate structure 30, and the probability of gate leakage can be further reduced. In other embodiments of the present invention, the barrier layer 60 may be other materials having properties that block silicon diffusion.
On the basis of the above embodiments, please continue to refer to fig. 2, in which in one embodiment of the present invention, the vertical projection of the silicon element supply layer 50 on the semiconductor epitaxial layer 20 is located in the drift region Q2 of the semiconductor epitaxial layer 20;
and the area of the perpendicular projection of the silicon element supply layer 50 on the semiconductor epitaxial layer 20 is smaller than or equal to the area of the perpendicular projection of the spacer layer 40 on the semiconductor epitaxial layer 20.
Specifically, the vertical projection of the silicon element supply layer 50 on the semiconductor epitaxial layer 20 is located in the drift region Q2 of the semiconductor epitaxial layer 20, so that the silicon diffused downwards in the silicon element supply layer 50 can be ensured to enter the semiconductor epitaxial layer 20 located in the drift region Q2, and the diffusion path of the silicon element can be shortened. The area of the vertical projection of the silicon element supply layer 50 on the semiconductor epitaxial layer 20 is smaller than or equal to the area of the vertical projection of the spacer layer 40 on the semiconductor epitaxial layer 20, so that the requirement that the whole silicon element supply layer 50 is completely separated from the second nitride semiconductor layer 22 below can be satisfied, and the loss of the silicon which is movably diffused in the silicon element supply layer 50 can be avoided.
Based on the above embodiments, in one embodiment of the present invention, referring to fig. 2, the spacer layer 40 is further located on the side of the gate structure 30 away from the substrate 10 and on the side wall of the gate structure 30;
and spacer layer 40, which is located on the side of gate structure 30 remote from substrate 10 and on the side wall of gate structure 30, is between barrier layer 60 and gate structure 30.
Specifically, in addition to the spacer 40 provided in the drift region Q2 of the semiconductor epitaxial layer 20, the spacer 40 is provided on the side of the gate structure 30 away from the substrate 10 and on the side wall of the gate structure 30. The spacer layer 40 located in the drift region Q2 of the semiconductor epitaxial layer 20, and the spacer layer 40 located on the side of the gate structure 30 remote from the substrate 10 and the side wall of the gate structure 30 are prepared at the same time and are integrally provided. The spacer layer 40 may be used as a passivation layer to protect the surface of the gate structure 30 and the surface of the semiconductor epitaxial layer 20. The spacer layer 40 may comprise silicon nitride (SiN) and has the characteristics of low cost and low manufacturing difficulty. The silicon content of the spacer layer 40 material ranges from 20% to 40%. The problem of gate leakage due to too high a silicon content in the spacer 40 can be prevented. In addition, the silicon content in the material of the spacer layer 40 is set to be more than 20%, so that the problem of gate leakage due to too high nitrogen content, which is caused by too low silicon content in the spacer layer 40, can be prevented.
On the basis of the above embodiments, in one embodiment of the present invention, fig. 3 is a schematic cross-sectional structure of another semiconductor device provided in the embodiment of the present invention, and referring to fig. 3, the semiconductor device further includes:
a strained layer 70 between the spacer layer 40 and the semiconductor epitaxial layer 20, and between the spacer layer 40 and the gate structure 30; and, the strained layer 70 covers the surface of the semiconductor epitaxial layer 20 and the surface of the gate structure 30; wherein the material of the strained layer 70 comprises aluminum nitride (AlN).
Specifically, the lattice constant of the material of the strained layer 70 is smaller than the lattice constant of the material of the second nitride semiconductor layer 22 and smaller than the lattice constant of the material of the P-type III-V semiconductor layer 31 in the gate structure 30, so that the strained layer 70 may provide a tensile stress, increasing the migration rate of the 2 DEG. For example, the lattice constant of the AlN material of the strained layer 70 is smaller than the lattice constant of the AlGaN material of the second nitride semiconductor layer 22, and smaller than the lattice constant of the p-GaN material in the gate structure 30. Because the strain layer 70 is added between the spacer layer 40 and the semiconductor epitaxial layer 20, the silicon content in the spacer layer 40 material can be increased, and the silicon content in the spacer layer 40 material can be 20% -40%.
Based on the above embodiments, in one embodiment of the present invention, fig. 4 is a top view of a semiconductor device provided in the embodiment of the present invention, and fig. 5 is a schematic cross-sectional structure of the structure shown in fig. 4 along a sectional line AA1, and referring to fig. 4 and fig. 5, the semiconductor device further includes a source electrode S and a drain electrode D, which are located on a side of the semiconductor epitaxial layer 20 away from the substrate 10; and source electrode S and drain electrode D are located on opposite sides of gate structure 30 (G); wherein the silicon element supply layer 50 is located between the gate structure 30 and the drain electrode D and between the gate structure 30 and the source electrode S.
Specifically, the source electrode S is located at a side of the second nitride semiconductor layer 22 away from the substrate 10, and is in contact with the second nitride semiconductor layer 22. The drain electrode D is located at a side of the second nitride semiconductor layer 22 remote from the substrate 10 and is in contact with the second nitride semiconductor layer 22. The source electrode S and the drain electrode D are located on opposite sides of the gate structure 30. The source electrode S and drain electrode D may include, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The source electrode S and the drain electrode D may be a single layer, or a plurality of layers having the same or different compositions. In some embodiments, the source electrode S and the drain electrode D form ohmic contacts with the second nitride semiconductor layer 22. Ohmic contact may be achieved by applying Ti, al, or other suitable materials to the source electrode S and the drain electrode D.
Referring to fig. 4, the semiconductor device mostly adopts a multi-gate finger structure, the gate structure 30, the source electrode S and the drain electrode D are in a strip shape, and the space between the gate structure 30, the source electrode S and the drain electrode D can be adjusted by itself when layout design is performed. But the striped gate structure 30, the source electrode S and the drain electrode D have exposed end surfaces outside the active region, and thus cause edge effects to cause leakage in the gate-off state. An IMP (Implant) process may be added to form an Implant layer 01 as shown in fig. 4, breaking the edge 2DEG to prevent leakage and reduce edge effects.
The embodiment of the invention also provides a method for preparing a semiconductor device, which is used for preparing the semiconductor device according to any of the above embodiments, and fig. 6 is a flowchart of a method for preparing a semiconductor device according to an embodiment of the invention, and referring to fig. 6, the method for preparing a semiconductor device includes:
s110, providing a substrate.
S120, forming a semiconductor epitaxial layer on one side of a substrate; the semiconductor epitaxial layer is internally provided with a heterojunction of two-dimensional electron gas; the semiconductor epitaxial layer comprises a gate region and drift regions positioned on two opposite sides of the gate region.
S130, forming a grid structure in a grid region of the semiconductor epitaxial layer.
And S140, forming a spacer layer in the drift region of the semiconductor epitaxial layer.
And S150, forming a barrier layer on the side of the gate structure away from the substrate.
S160, forming a silicon element supply layer on one side of the spacer layer away from the substrate; the barrier layer is used for blocking silicon in the silicon element supply layer from diffusing to the gate structure.
According to the preparation method of the semiconductor device, the silicon element supply layer and the barrier layer are arranged separately, silicon is provided for the semiconductor epitaxial layer of the drift region through the silicon element supply layer with high silicon element content, so that the concentration of 2DEG is effectively improved, the on-resistance is reduced, and the working efficiency of the device is improved; the side wall and the upper surface of the gate structure are wrapped by the blocking layer with good silicon blocking property, so that silicon in the blocking silicon element supply layer is prevented from diffusing to the gate structure, and the probability of gate leakage can be effectively reduced.
Fig. 7 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention; fig. 8 to 13 are schematic cross-sectional structures of step S220 to step S260 in a method for manufacturing a semiconductor device according to an embodiment of the present invention, and referring to fig. 7 to 13, the method for manufacturing a semiconductor device includes:
s210, providing a substrate.
S220, forming a semiconductor epitaxial layer on one side of the substrate; the semiconductor epitaxial layer is internally provided with a heterojunction of two-dimensional electron gas; the semiconductor epitaxial layer comprises a gate region and drift regions positioned on two opposite sides of the gate region.
Specifically, referring to fig. 8, forming the semiconductor epitaxial layer 20 on one side of the substrate 10 includes: a first nitride semiconductor layer 21 and a second nitride semiconductor layer 22 are sequentially formed on one side of the substrate 10. The second nitride semiconductor layer 22 has a band gap different from that of the first nitride semiconductor layer 21, so that a heterojunction of two-dimensional electron gas can be provided between the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22. The material of the first nitride semiconductor layer 21 may include, but is not limited to, nitrides or III-V compounds, such as GaN, alN, inN, inxAlyGa (1-x-y) N (where x+y.ltoreq.1), alyGa (1-y) N (where y.ltoreq.1). The material of the second nitride semiconductor layer 22 may include, but is not limited to, a group III-V nitride semiconductor material, such as GaN, alGaN, inN, alInN, inGaN, alInGaN, or a combination thereof.
S230, forming a gate structure in a gate region of the semiconductor epitaxial layer.
Specifically, referring to fig. 9, forming the gate structure 30 in the gate region Q1 of the semiconductor epitaxial layer 20 may specifically include: a III-V semiconductor layer 31 and a gate electrode 32 are sequentially formed on the semiconductor epitaxial layer 20; the III-V semiconductor layer 31 and the gate electrode 32 are etched, leaving only the layer III-V semiconductor layer 31 and the gate electrode 32 in the gate region Q1, thereby forming the gate structure 30.
S240, forming a spacer layer on the drift region of the semiconductor epitaxial layer, one side of the gate structure away from the substrate and the side wall of the gate structure.
Specifically, referring to fig. 10, when forming the spacer layer 40 in the drift region Q2 of the semiconductor epitaxial layer 20, the method further includes: spacers 40 are formed on the side of the gate structure 30 remote from the substrate 10 and on the sidewalls of the gate structure 30. The spacer layer 40 serves as a passivation layer protecting the surface of the gate structure 30 and the surface of the semiconductor epitaxial layer 20. The spacer layer 40 may comprise silicon nitride (SiN) and has the characteristics of low cost and low manufacturing difficulty. The silicon content of the spacer layer 40 material ranges from 20% to 40%. The problem of gate leakage due to too high a silicon content in the spacer 40 can be prevented. In addition, the silicon content in the material of the spacer layer 40 is set to be more than 20%, so that the problem of gate leakage due to too high nitrogen content, which is caused by too low silicon content in the spacer layer 40, can be prevented.
S250, depositing a silicon oxide material on the surface of the side, away from the substrate, of the spacer layer to form a barrier layer, and etching away the barrier layer in the drift region to expose the spacer layer 40.
Specifically, referring to fig. 11 and 12, forming a barrier layer 60 on a side of the gate structure 30 away from the substrate 10 and on a sidewall of the gate structure 30 includes: a silicon oxide material is deposited on the surface of the spacer layer 40 on the side remote from the substrate 10 to form a barrier layer 60 and the barrier layer 60 in the drift region Q2 is etched away to expose the spacer layer 40. Silicon oxide (SiO) 2 ) The silicon oxide layer is used as the barrier layer 60, so that the silicon in the barrier silicon element supply layer 50 can be further prevented from diffusing to the gate structure 30, and the probability of gate leakage can be further reduced. In other embodiments of the present invention, the barrier layer 60 may be other materials having properties that block silicon diffusion.
S260, depositing a silicon material on the surface of the barrier layer 60 on the side away from the substrate 10 and the surface of the exposed spacer layer 40 to form the silicon element supply layer 50, and etching away the silicon element supply layer 50 on the side of the barrier layer 60 away from the substrate 10.
Specifically, referring to fig. 13 and 2, forming a silicon element supply layer 50 on a side of the spacer layer 40 remote from the substrate 10 includes: a silicon material is deposited on the surface of the barrier layer 60 on the side remote from the substrate 10 and the surface of the exposed spacer layer 40 to form the silicon element supply layer 50, and the silicon element supply layer 50 on the side of the barrier layer 60 remote from the substrate 10 is etched away. Wherein the silicon element supply layer 50 is used to supply silicon to the semiconductor epitaxial layer 20 of the drift region Q2. The silicon element supply layer 50 is a pure silicon layer, so that the silicon content of the silicon element supply layer 50 can be maximized, the 2DEG concentration can be further improved, the on-resistance is reduced, and the working efficiency of the device is improved. Pure silicon layers in devices can be grown in batches by using furnace tubes, and pure silicon layers in single-chip microcomputer single-growth devices can also be used.
Fig. 14 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present invention; fig. 15 to 19 are schematic cross-sectional structures of step S340 to step S370 in a method for manufacturing a semiconductor device according to an embodiment of the present invention, and referring to fig. 14 to 19, the method for manufacturing a semiconductor device includes:
s310, providing a substrate.
S320, forming a semiconductor epitaxial layer on one side of the substrate; the semiconductor epitaxial layer is internally provided with a heterojunction of two-dimensional electron gas; the semiconductor epitaxial layer comprises a gate region and drift regions positioned on two opposite sides of the gate region. Reference is made specifically to step S220, and details thereof are not repeated here.
S330, forming a gate structure in the gate region of the semiconductor epitaxial layer. Reference is made specifically to step S230, and details thereof are not repeated here.
S340, forming a strain layer on the surface of the semiconductor epitaxial layer and the surface of the gate structure; the material of the strained layer comprises aluminum nitride.
Specifically, referring to fig. 15, after forming the gate structure 30 in the gate region Q1 of the semiconductor epitaxial layer 20, the method further includes: forming a strain layer 70 on the surface of the semiconductor epitaxial layer 20 and the surface of the gate structure 30; wherein the material of the strained layer 70 comprises aluminum nitride; the spacer layer 40 is located on the side of the strained layer 70 remote from the substrate 10. The lattice constant of the material of the strained layer 70 is smaller than the lattice constant of the material of the second nitride semiconductor layer 22 and smaller than the lattice constant of the material of the P-type III-V semiconductor layer 31 in the gate structure 30, so that the strained layer 70 may provide a tensile stress, increasing the migration rate of the 2 DEG.
S350, forming a spacing layer on the side of the strain layer away from the substrate. Reference may be made specifically to fig. 16, and will not be described again here.
S360, depositing a silicon oxide material on the surface of the side, away from the substrate, of the spacer layer to form a barrier layer, and etching away the barrier layer located in the drift region to expose the spacer layer. Reference may be made specifically to fig. 17 and 18, and no further description is given here.
And S370, depositing a silicon material on the surface of the side, away from the substrate, of the barrier layer and the surface of the exposed spacer layer to form a silicon element supply layer, and etching away the silicon element supply layer on the side, away from the substrate, of the barrier layer.
The silicon element supply layer is used for providing silicon for the semiconductor epitaxial layer of the drift region, and the blocking layer is used for blocking diffusion of silicon in the silicon element supply layer to the gate structure. Reference may be made specifically to fig. 19 and 3, and no further description is given here.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
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