CN117472666A - Access method, debugging system and electronic device of open source processor and internal cache - Google Patents

Abstract

The application relates to an access method, a debugging system and electronic equipment of an open source processor and an internal cache, and belongs to the field of computers. The open source processor is configured to interface with a JTAG tool configured to access configuration information of an internal cache of the open source processor, the open source processor comprising: a cache, a system register and an access module; the system register is connected with the cache and is configured to store configuration information, wherein the configuration information comprises: access address, operation type, access mode; and the access module is connected with the system register and the cache, and is configured to analyze the configuration information and access the cache according to the configuration information. According to the method and the device, access to the internal Cache of the open source processor can be realized, so that when the Bug occurs in the debugging process, instructions and data which are in a problem at present can be known by analyzing the data in the internal Cache (Cache) of the open source processor, and the positioning and problem solving can be accelerated.

Description

Access method, debugging system and electronic device of open source processor and internal cache

Technical Field

The application belongs to the field of computers, and particularly relates to an access method, a debugging system and electronic equipment of an open source processor and an internal cache.

Background

RISC-V is an open instruction set architecture built based on a reduced instruction set RISC (Reduced Instruction Set Computer ) that is implemented by a Bokrill division-related team at the university of California, where RISC-V represents the fifth generation of RISC. RISC-V instruction set architecture plays an important role in the fields of Internet of things, embedded equipment, industrial control, artificial intelligence and the like, and is also widely applied. With the popularization of RISC-V, how to efficiently complete debugging and verification work in the integrated design process of RISC-V chips has great influence on project progress. While board level testing is performed, on-line debugging is typically accomplished on an FPGA (Field Programmable Gate Array ) platform using the JTAG (Joint Test Action Group, joint test action group) protocol.

When the JTAG technology is used for on-line debugging of the RISC-V chip, various bugs (faults) are encountered, and a great deal of time is spent for positioning and solving the problems. The problems of simple interruption or abnormality are encountered, and the problems can be rapidly positioned and solved by analyzing the related general registers and the system registers. When a problem occurs in the design of the RISC-V chip or other problems occur in code operation, it is often difficult to analyze the positioning reason according to the above-mentioned register, and data in the Cache (Cache) inside the RISC-V chip needs to be checked for analysis, and the instruction and the data which are in the problem at present can be known through the data analysis of the Cache, so that the positioning and the problem solving can be accelerated. However, currently, in JTAG debugging process, it is difficult to view the data of the Cache inside the RISC-V chip.

Disclosure of Invention

In view of this, an object of the present application is to provide an access method, a debug system and an electronic device for an open source processor and an internal Cache, so as to implement access to an internal Cache of a RISC-V chip in a process of debugging the RISC-V chip based on JTAG.

Embodiments of the present application are implemented as follows:

in a first aspect, embodiments of the present application provide an open source processor configured to connect with a JTAG tool configured to access configuration information cached inside the open source processor, the open source processor comprising: a cache, a system register and an access module; a system register is connected with the cache, the system register configured to store the configuration information, wherein the configuration information comprises: access address, operation type, access mode; and the access module is connected with the system register and the cache, and is configured to analyze the configuration information and access the cache according to an access address, an operation type and an access mode in the configuration information.

In the embodiment of the application, the configuration information for accessing the internal Cache of the open source processor can be configured through JTAG tools, the configuration information is analyzed through the access module, and the Cache is accessed according to the configuration information, so that the internal Cache of the open source processor can be accessed, and when the Bug occurs in the debugging process, the instruction and the data of the current problem can be known through analyzing the data in the internal Cache of the open source processor, and the positioning and the problem solving can be accelerated.

With reference to a possible implementation manner of the embodiment of the first aspect, if the operation type is a write operation and the access mode is a single-step processing mode, the access module is configured to write information in the system register into a cache pointed to by the access address based on the single-step processing mode; or if the operation type is a write operation and the access mode is a batch processing mode, the access module is configured to write information in the external memory pointed to by the access address into the cache based on the batch processing mode.

In the embodiment of the application, two access modes are provided, so that writing operation and quick positioning are conveniently performed on information in a Cache in the debugging process of a RISC-V processor, and the JTAG online debugging efficiency is improved.

With reference to a possible implementation manner of the embodiment of the first aspect, if the operation type is a read operation and the access mode is a single-step processing mode, the access module is configured to read information in a cache pointed to by the access address into the system register based on the single-step processing mode; or if the operation type is a read operation and the access mode is a batch processing mode, the access module is configured to read the information in the cache to an external memory based on the batch processing mode.

In the embodiment of the application, two access modes are provided, so that the information in the Cache can be conveniently read and positioned in the debugging process of the RISC-V processor, and the JTAG online debugging efficiency is improved.

With reference to a possible implementation manner of the embodiment of the first aspect, the cache includes an instruction cache and a data cache; the configuration information also includes an access type indicating whether to access the instruction cache or the data cache.

In the embodiment of the application, when the cache comprises the instruction cache and the data cache, the access to the instruction cache or the data cache is realized by adding the configuration information of the access type, so that the flexibility is improved.

With reference to a possible implementation manner of the first aspect embodiment, the configuration information further includes a cache line size, where the cache line size is used to indicate a size of the cache line to be accessed.

In the embodiment of the application, the cache line size is increased, so that the required cache line size is conveniently selected to access the access, and the flexibility is improved.

With reference to a possible implementation manner of the first aspect embodiment, the open source processor further includes: the access module and the cache are respectively connected with the internal bus module, the internal bus module is also connected with the system bus module, and the system bus module is also configured to be connected with an external memory; the internal bus module is configured to realize interactive transmission between the cache and the external memory under the action of the access module; the system bus module is configured to convert an access of the internal bus module into an access of an external bus or to convert an access of an access bus into an access of the internal bus module.

In the embodiment of the application, the interactive transmission between the cache and the external memory can be realized rapidly through the internal bus module and the system bus module, and a guarantee is provided for batch data reading and writing.

In a second aspect, an embodiment of the present application provides a debug system, including: a JTAG tool and an open source processor as provided by and/or in combination with any one of the possible implementations of the first aspect embodiment described above, the JTAG tool being connected to the open source processor, the JTAG tool being configured to be configured to access configuration information cached inside the open source processor.

In a third aspect, an embodiment of the present application provides an electronic device, including: a memory and an open source processor as provided by the above-described first aspect embodiment and/or in combination with any one of the possible implementations of the first aspect embodiment, the open source processor being connected to the memory.

In a fourth aspect, an embodiment of the present application provides a method for accessing an internal cache of an open source processor, where the method includes: the system register in the open source processor receives and stores configuration information configured by JTAG tools and used for accessing the internal cache of the open source processor, wherein the configuration information comprises: access address, operation type, access mode; and the access module in the open source processor analyzes the configuration information and accesses the cache in the open source processor according to the access address, the operation type and the access mode in the configuration information.

With reference to one possible implementation manner of the fourth aspect embodiment, accessing a cache in the open source processor according to an access address, an operation type, and an access mode in the configuration information includes: if the operation type is write operation and the access mode is single-step processing mode, the access module writes the information in the system register into a cache pointed by the access address based on the single-step processing mode; or if the operation type is write operation and the access mode is batch processing mode, writing information in an external memory pointed by the access address into the cache based on the batch processing mode; or if the operation type is a read operation and the access mode is a single-step processing mode, the access module reads information in a cache pointed by the access address into the system register based on the single-step processing mode; or if the operation type is a read operation and the access mode is a batch processing mode, the access module reads the information in the cache to an external memory based on the batch processing mode.

With reference to a possible implementation manner of the fourth aspect, the cache includes an instruction cache and a data cache; the configuration information also includes an access type indicating whether to access the instruction cache or the data cache.

Additional features and advantages of the application will be set forth in the description which follows. The objects and other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art. The above and other objects, features and advantages of the present application will become more apparent from the accompanying drawings.

Fig. 1 shows a schematic structural diagram of an open source processor according to an embodiment of the present application.

Fig. 2 is a schematic structural diagram of an open source processor connected to an external memory according to an embodiment of the present application.

Fig. 3 shows a schematic structural diagram of a debug system according to an embodiment of the present application.

Fig. 4 is a flowchart illustrating an access method of an internal cache of an open source processor according to an embodiment of the present application.

Fig. 5 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. The following examples are given by way of illustration for more clearly illustrating the technical solutions of the present application, and are not intended to limit the scope of protection of the present application. Those skilled in the art will appreciate that the embodiments described below and features of the embodiments can be combined with one another without conflict.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Furthermore, the term "and/or" in this application is merely an association relation describing an association object, and indicates that three relations may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone.

In the description of the embodiments of the present application, unless explicitly specified and limited otherwise, the term "electrically connected" may be either directly or indirectly through intermediaries.

In order to realize access to the Cache inside the RISC-V chip in the process of debugging the RISC-V chip based on JTAG, so that when the Bug occurs in the debugging process, the instruction and the data which are in question at present can be known by analyzing the data in the Cache inside the RISC-V chip, and the positioning and the solving of the question can be accelerated. The embodiment of the application provides an access method, a debugging system and electronic equipment for an open source processor and an internal Cache (Cache), which can realize access to the internal Cache of the open source processor in a process of debugging the open source processor based on JTAG.

The open source processor in the present application is a processor based on an open source instruction architecture, and may be a RISC-V processor, for example, a RISC-V central processor (Central Processing Unit, CPU). The processor may be a central processing unit, a network processor (Network Processor, NP), a microprocessor, or the like; and may also be a digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. Or any conventional processor or the like.

As shown in fig. 1, an open source processor provided in an embodiment of the present application includes: cache, system registers, and access module. The system register is respectively connected with the cache and the access module, and the access module is also connected with the cache.

The open source processor in the present application is also configured to interface with JTAG tools, which support JTAG access to RISC-V processor internal registers through an abstract command mode, according to the RISC-VDebug protocol. In the embodiment of the application, the JTAG tool is configured to be used for accessing the configuration information of the internal Cache of the open source processor, the JTAG tool can convert JTAG request into read-write of the system register through JTAG protocol, configure the configuration information of the internal Cache of the open source processor for the system register, store the access information (which can be an instruction or data) required to be written into the internal Cache of the open source processor into the system register, and read the access information from the internal Cache of the open source processor from the system register, thereby realizing the access to the internal Cache of the open source processor.

The system register is used for receiving and storing configuration information configured by the JTAG tool, and also is used as a transfer station for storing interaction information between the JTAG tool and the cache, for example, when the JTAG tool wants to write information into the cache, the information needs to be temporarily stored in the system register first, information read from the cache is temporarily stored, and then the JTAG tool reads the temporarily stored information from the system register.

The system register in the application is a self-defined system register, and besides JTAG tools, the RISC-V processor can also access the system register to realize the configuration of the self-defined system register. If only JTAG tools are required to have access to the custom system register, the address of the system register may be defined as 0xE 00-0 xEFC, or may be defined as other unused addresses, such as a certain address in the interval 0x0000-0x0 FFF. The system register includes: the system comprises a read-write control register and a read-write information register, wherein the read-write control register is used for storing configuration information, and the read-write information register is used for temporarily storing read-write information.

The configuration information may be used to control the operation type, access mode, etc. of accessing the internal cache of the open source processor. Accordingly, the configuration information includes: access address, operation type, access mode, etc. The operation type may be a read operation type or a write operation type. The access mode can be a single-step processing mode or a batch processing mode, wherein the single-step processing mode can finish transmission of a single Cache line at most at one time, and the batch processing mode can finish transmission of a plurality of Cache lines at one time, so that the efficiency is higher.

The embodiment of the application provides two access modes of the Cache, is convenient for performing read-write operation on information in the Cache and rapidly positioning in the debugging process of the RISC-V processor, and improves the efficiency of JTAG online debugging. In addition, the RISC-V processor can realize additional operation on the Cache through the self-defined system register.

Wherein, the read operation can be represented by 1' b 0; 1' b1 represents a write operation, although the reverse can be true. Way1 may be represented by 1' b0, representing a single step processing mode; 1' b1 represents way2 and represents a batch processing mode, although the reverse is also possible.

The access module is connected with the system register and the cache, and is used for analyzing the configuration information, accessing the cache in the open source processor according to the access address, the operation type and the access mode in the configuration information, and realizing the read/write access to the cache.

In one embodiment, the accessing module accesses the cache in the open source processor according to the access address, the operation type and the access mode in the configuration information may be: if the operation type is a write operation (e.g., the operation type is 1'b 1), and the access mode is a single-step processing mode (e.g., the access mode is 1' b 0), the access module is configured to write the information temporarily stored in the system register into the cache pointed by the access address based on the single-step processing mode; alternatively, if the operation type is a write operation and the access mode is a batch processing mode (e.g., the access mode is 1' b 1), the access module is configured to write information in the external memory pointed to by the access address to the cache based on the batch processing mode.

In one embodiment, the accessing module accesses the cache in the open source processor according to the access address, the operation type and the access mode in the configuration information may be: if the operation type is a read operation (e.g., the operation type is 1' b 0), and the access mode is a single-step processing mode, the access module is configured to read information in the cache pointed to by the access address into the system register based on the single-step processing mode; or if the operation type is a read operation and the access mode is a batch processing mode, the access module is configured to read the information in the cache to the external memory based on the batch processing mode.

In one embodiment, the open source processor internal cache may be an instruction cache and/or a data cache. If the cache is an instruction cache, the accessed information is an instruction, and if the cache is a data cache, the accessed information is data. Optionally, the Cache includes an instruction Cache and a Data Cache, and correspondingly, the configuration information further includes an access type, where the access type is used to indicate whether to access the instruction Cache or the Data Cache, for example, the access type is 3' b000, which indicates a Tag portion of the instruction Cache, the access type is 3' b001 which indicates a Data portion of the instruction Cache, and the access type is 3' b010 which indicates a Tag portion of the access Data Cache; an access type of 3'b011 indicates accessing the Data portion of the Data Cache, e.g., an access type of 3' b1xx indicates accessing other caches, such as L2Cache, L3Cache, etc.

If the access type indicates that the instruction Cache is accessed, the read/write operations are all read/write for the instruction Cache, and the read/write information is the instruction. If the access type indicates that the data Cache is accessed, the read/write operations are all read/write for the data Cache, and the read/write information is data.

In an alternative embodiment, the configuration information further includes a Cache line size, where the Cache line size is used to indicate a size of a Cache line to be accessed, for example, a Cache line size of 3' b000 indicates byte access, a Cache line size of 3' b001 indicates half word access, a Cache line size of 3' b010 indicates word access, 3' b011 indicates double word access, and 3' b1xx indicates a transmitted Cache line number. If the configuration information does not include a cache line size, the cache is accessed according to a default cache line size.

In order to better understand the above configuration information, in one embodiment, the above configuration information is shown in table 1.

TABLE 1

The access address in table 1 may include an external memory address and a cache address, and when the access mode is a single-step processing mode, only the cache address needs to be used, and when the access mode is a batch processing mode, the external memory address and the cache address may be used at the same time, and in this case, information in the external memory pointed by the external memory address may be written into the cache pointed by the cache address based on the batch processing mode, or information in the cache pointed by the cache address may be read into the external memory pointed by the external memory address based on the batch processing mode.

It will be appreciated that in configuring the values of the operation type, access mode, cache line size in table 1, only one of the items needs to be selected for configuration during one access, for example, for the operation type, either as a read operation or as a write operation, and the same is true for the access mode, access type, cache line size, etc., for example, for the access mode, either way1 or way2 is selected, which may result in a run error if multiple items are simultaneously configured.

In one embodiment, as shown in fig. 2, the open source processor further includes: an internal bus module and a system bus module. Wherein fig. 2 only shows the case where the cache contains both a data cache and an instruction cache. The access module comprises a read-write Address Channel (Address Channel) and a read-write data Channel (Date Channel), and accesses to the cache are completed through the read-write Address Channel and the read-write data Channel.

The access module and the cache are respectively connected with the internal bus module, the internal bus module is also connected with the system bus module, and the system bus module is also configured to be connected with the external memory. The internal bus module is configured to realize interactive transmission between the cache and the external memory under the action of the access module; the system bus module is configured to convert an access of the internal bus module into an access of the external bus or to convert an access of the access bus into an access of the internal bus module. The internal bus module comprises a Cache Channel (Cache Channel) and a System Channel (System Channel), wherein the Cache Channel is connected with the Cache, the System Channel is connected with the System bus module, and the Cache Channel is communicated with the System Channel.

The system Bus module may support AXI (Advanced eXtensible Interface ), AHB (Advanced High-performance Bus), and other protocols.

The external Memory may be, but is not limited to, a random access Memory (Random Access Memory, RAM), a Read Only Memory (ROM), a programmable Read Only Memory (Programmable Read-Only Memory, PROM), an erasable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable Read Only Memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

Wherein the access module is configured to read the information in the cache to the external memory based on the batch processing mode only if the external memory is a memory supporting a write function.

The embodiment of the application also provides a debugging system, as shown in fig. 3, which comprises the JTAG tool and the open source processor, wherein the JTAG tool is connected with the open source processor and is configured to access configuration information cached in the open source processor. The debug system may further comprise an external memory coupled to the open source processor.

In an alternative embodiment, the JTAG tool may include a DTM (Debug Transport Module) module, DMI (Debug Module Interface) interface, and DM (Debug Module) module, wherein the DTM module interacts with an external debug tool, the DMI interface for the DTM module to interact with the DM module, and the DM module to interact with system registers in the RISC-V processor. The DM module comprises an abstract level command register and an information register, the DTM module configures the abstract level command register through a DMI interface and writes configuration information, wherein the configuration information written into the abstract level command register is the configuration information of the system register. And the DTM module writes information which needs to be written into the internal cache of the open source processor into the information register of the DM module through the DMI interface. The system register in the open source processor reads the information in the information register of the DM module and temporarily stores the information so that the access module writes the information into the cache.

The embodiment of the application also provides an access method of the internal cache of the open source processor, as shown in fig. 4, and the access method of the internal cache of the open source processor provided by the embodiment of the application is explained below with reference to fig. 4.

S1: and a system register in the open source processor receives and stores configuration information configured through JTAG tools and used for accessing the internal cache of the open source processor.

Wherein, the configuration information includes: access address, operation type, access mode.

Optionally, the internal cache of the open source processor includes an instruction cache and a data cache, and correspondingly, the configuration information further includes an access type, where the access type is used to indicate whether to access the instruction cache or the data cache.

Optionally, the configuration information further includes a cache line size, where the cache line size is used to indicate a size of a cache line to be accessed, and if the configuration information does not include the cache line size, the cache is accessed according to a default cache line size.

S2: and the access module in the open source processor analyzes the configuration information and accesses the cache in the open source processor according to the access address, the operation type and the access mode in the configuration information.

The process of accessing the cache in the open source processor according to the access address, the operation type and the access mode in the configuration information may be:

if the operation type is write operation and the access mode is single-step processing mode, the access module writes the information in the system register into a cache pointed by the access address based on the single-step processing mode; or if the operation type is write operation and the access mode is batch processing mode, writing information in the external memory pointed by the access address into the cache based on the batch processing mode; or if the operation type is a read operation and the access mode is a single-step processing mode, the access module reads the information in the cache pointed by the access address into the system register based on the single-step processing mode; or if the operation type is a read operation and the access mode is a batch processing mode, the access module reads the information in the cache to the external memory based on the batch processing mode.

The implementation principle and the generated technical effects of the access method for the internal cache of the open source processor provided by the embodiment of the present application are the same as those of the embodiment of the open source processor, and for the sake of brief description, reference may be made to corresponding contents in the embodiment of the open source processor where the method embodiment is not mentioned.

As shown in fig. 5, fig. 5 shows a block diagram of an electronic device 200 according to an embodiment of the present application. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240. The processor may be an open source processor as described above, such as a RISC-V processor.

The transceiver 210, the memory 220, and the processor 240 are electrically connected directly or indirectly to each other to realize data transmission or interaction. For example, the components may be electrically coupled to each other via one or more communication buses 230 or signal lines. Wherein the transceiver 210 is configured to transmit and receive data. The memory 220 is used to store a computer program comprising at least one software function module that may be stored in the memory 220 in the form of software or Firmware (Firmware) or cured in an Operating System (OS) of the electronic device 200. The processor 240 is configured to execute a computer program stored in the memory 220. For example, the processor 240 is configured to perform the above-described access method for the internal cache of the open source processor.

The Memory 220 may be, but is not limited to, a random access Memory (Random Access Memory, RAM), a Read Only Memory (ROM), a programmable Read Only Memory (Programmable Read-Only Memory, PROM), an erasable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable Read Only Memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

The processor 240 may be an integrated circuit chip with signal processing capabilities. The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), a microprocessor, etc.; but also digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. Or the processor 240 may be any conventional processor or the like.

The electronic device 200 includes, but is not limited to, a mobile phone, a tablet, a computer, etc.

It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other manners as well. The apparatus embodiments described above are merely illustrative, for example, flow diagrams and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, the functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. An open source processor configured to interface with a JTAG tool configured to access configuration information cached within the open source processor, the open source processor comprising:

caching;

a system register coupled to the cache, the system register configured to store the configuration information, wherein the configuration information comprises: access address, operation type, access mode;

and the access module is connected with the system register and the cache, and is configured to analyze the configuration information and access the cache according to an access address, an operation type and an access mode in the configuration information.

2. The open source processor of claim 1 wherein,

if the operation type is a write operation and the access mode is a single-step processing mode, the access module is configured to write information in the system register into a cache pointed by the access address based on the single-step processing mode; or,

if the operation type is a write operation and the access mode is a batch processing mode, the access module is configured to write information in an external memory pointed to by the access address into the cache based on the batch processing mode.

3. The open source processor of claim 1 wherein,

if the operation type is a read operation and the access mode is a single-step processing mode, the access module is configured to read information in a cache pointed by the access address into the system register based on the single-step processing mode; or,

if the operation type is a read operation and the access mode is a batch processing mode, the access module is configured to read information in the cache to an external memory based on the batch processing mode.

4. The open source processor of claim 1 wherein the caches include an instruction cache and a data cache; the configuration information also includes an access type indicating whether to access the instruction cache or the data cache.

5. The open source processor of claim 1 wherein the configuration information further comprises a cache line size indicating a size of the cache line to access.

6. The open source processor of any one of claims 1-5 wherein the open source processor further comprises: the access module and the cache are respectively connected with the internal bus module, the internal bus module is also connected with the system bus module, and the system bus module is also configured to be connected with an external memory;

the internal bus module is configured to realize interactive transmission between the cache and the external memory under the action of the access module;

the system bus module is configured to convert an access of the internal bus module into an access of an external bus or to convert an access of an access bus into an access of the internal bus module.

7. A debug system, comprising: a JTAG tool and the open source processor of any of claims 1-6, the JTAG tool being connected to the open source processor, the JTAG tool being configured to access configuration information cached inside the open source processor.

8. An electronic device, comprising: a memory and an open source processor as claimed in any one of claims 1 to 6, the open source processor being connected to the memory.

9. An access method for an internal cache of an open source processor, the method comprising:

the system register in the open source processor receives and stores configuration information configured by JTAG tools and used for accessing the internal cache of the open source processor, wherein the configuration information comprises: access address, operation type, access mode;

and the access module in the open source processor analyzes the configuration information and accesses the cache in the open source processor according to the access address, the operation type and the access mode in the configuration information.

10. The method of claim 9, wherein accessing the cache in the open source processor according to the access address, the operation type, and the access mode in the configuration information comprises:

if the operation type is write operation and the access mode is single-step processing mode, the access module writes the information in the system register into a cache pointed by the access address based on the single-step processing mode; or,

if the operation type is write operation and the access mode is batch processing mode, writing information in an external memory pointed by the access address into the cache based on the batch processing mode; or,

if the operation type is a read operation and the access mode is a single-step processing mode, the access module reads information in a cache pointed by the access address into the system register based on the single-step processing mode; or,

and if the operation type is a read operation and the access mode is a batch processing mode, the access module reads the information in the cache to an external memory based on the batch processing mode.