CN117459330B - High-reliability EMI friendly Ethernet circuit - Google Patents

Abstract

The application relates to the technical field of industrial control instruments, in particular to a high-reliability EMI friendly Ethernet circuit which comprises an MCU module, a filtering module, a PHY communication module and an RJ45 network interface module, wherein the MCU module is connected with the filtering module, the filtering module is connected with the PHY communication module, the PHY communication module is connected with the RJ45 network interface module, the RJ45 network interface module is used for connecting network equipment, the PHY communication module is used for converting analog signals into digital signals and transmitting the digital signals, the filtering module is used for filtering the digital signals, and the MCU module is used for analyzing and processing the filtered digital signals. The application has the beneficial effect of improving the radiation protection performance of the traditional Ethernet.

Description

High-reliability EMI friendly Ethernet circuit

Technical Field

The application relates to the technical field of industrial control instruments, in particular to a high-reliability EMI friendly Ethernet circuit.

Background

Ethernet (Ethernet) refers to the baseband local area network specification created by Xerox corporation and developed jointly by Xerox, intel and DEC corporation, and is the most common communication protocol standard adopted by the existing local area networks today. The ethernet network uses CSMA/CD (carrier sense multiple access and collision detection) technology and runs on multiple types of cables at a rate of 10M/S. Ethernet is similar to the IEEE802.3 family of standards, including standard Ethernet (10 Mbit/s), fast Ethernet (100 Mbit/s), and 10G (10 Gbit/s) gigabit Ethernet.

In the related art, an ethernet interface circuit generally comprises an MCU, a physical layer interface PHY (physical Layer PHY), and an RJ45 network port. The MCU integrates the MAC controller, the physical layer interface PHY comprises a PHY layer chip, the PHY layer chip is in REF_CLK_OUT mode when in work, the PHY layer chip is externally connected with a high-frequency crystal oscillator of 25Mhz to provide basic clock signals for the PHY layer chip, the clock signals are internally multiplied to 50Mhz, and then the 50Mhz reference clock is output to the MAC controller through a REFCLK pin of the PHY layer chip. The MCU is arranged on the equipment controller, and the communication between the equipment controller and the network equipment is realized through the signal transmission among the MCU, the PHY layer chip and the RJ45 network port.

The prior art solutions described above have the following drawbacks: the MAC controller and the PHY layer chip are directly connected by a signal line, and the line can generate larger EMI radiation interference, so that the radiation of the ethernet circuit exceeds the standard, and the ethernet circuit is not suitable for some special scenes such as industrial environments, so there is room for improvement.

Disclosure of Invention

In order to improve the radiation protection performance of the Ethernet, the application provides a high-reliability EMI friendly Ethernet circuit.

The high-reliability EMI friendly Ethernet circuit provided by the application adopts the following technical scheme:

The utility model provides a high reliability EMI friendly ethernet circuit, includes MCU module, filter module, PHY communication module and RJ45 network interface module, the MCU module with filter module connects, filter module with PHY communication module connects, PHY communication module with RJ45 network interface module connects, wherein:

The RJ45 network interface module is used for connecting network equipment;

the PHY communication module is used for converting analog signals into digital signals and transmitting the digital signals;

The filtering module is used for filtering the digital signals;

The MCU module is used for analyzing and processing the filtered digital signals.

By adopting the technical scheme, the network equipment sends analog signals to the PHY communication module through the RJ45 network interface module, the PHY communication module converts the analog signals into digital signals and transmits the digital signals to the filtering module, the filtering module filters the digital signals, the MCU module recognizes the digital signals and processes the digital signals, the MCU module transmits the processed digital signals to the filtering module, the filtering module filters the digital signals, the filtered digital signals are transmitted to the PHY communication module, the PHY communication module converts the digital signals into the analog signals and transmits the analog signals to the network equipment through the RJ45 network interface module, the MCU module is arranged on the equipment controller, communication between the network equipment and the equipment controller is realized through signal transmission among the RJ45 communication module, the PHY communication module, the filtering module and the MCU module, and the filtering module filters sharp waves in the digital signals in the digital signal transmission process.

Preferably, the filtering module comprises a first filtering unit, the first filtering unit comprises a pi-type filtering circuit, the pi-type filtering circuit comprises a first filtering capacitor, a second filtering capacitor and a filtering magnetic bead, one end of the filtering magnetic bead is connected with the PHY communication module, the other end of the filtering magnetic bead is connected with the MCU module, one end of the first filtering capacitor is connected between the filtering magnetic bead and the MCU module, one end of the second filtering capacitor is connected between the filtering magnetic bead and the PHY communication module, and the other end of the first filtering capacitor and the other end of the second filtering capacitor are grounded.

Through adopting above-mentioned technical scheme, pi type filter circuit utilizes first filter capacitor, second filter capacitor and filtering magnetic bead combination to form pi type network structure, realize filtering process through selectively transmitting the digital signal in specific frequency range, carry out frequency division and branching under the effect of first filter capacitor, second filter capacitor and filtering magnetic bead based on the input signal, and finally obtain the output signal after the filtration, pi type filter circuit can carry out filtering process to low frequency and high frequency signal, help the suppression to main frequency and harmonic, high frequency noise and peak interference on signal line and the electric power line have been reduced, thereby the radiation emission of ethernet has been improved, satisfy most application occasions that have the requirement to the radiation.

Preferably, the filtering module further comprises a second filtering unit, the second filtering unit comprises a magnetic bead group, and two ends of a magnetic bead of the magnetic bead group are respectively connected with the PHY communication module and the MCU module.

Through adopting above-mentioned technical scheme, the magnetic bead both ends of magnetic bead group are connected with PHY communication module and with MCU module respectively, when carrying out signal transmission between PHY communication module and MCU module, the magnetic bead group suppresses high frequency noise and the peak interference on signal line and the electric wire to reduce the radiation on signal line and the electric wire, further improved the radiation protection performance of ethernet, and have the ability of absorbing the static pulse, make the circuit keep stable.

Preferably, the anti-interference device further comprises an anti-interference module, wherein the anti-interference module comprises a network transformer and an anti-interference unit, the network transformer is connected with the PHY communication module, the network transformer is connected with the RJ45 network interface module, and the anti-interference unit is connected with the network transformer.

By adopting the technical scheme, the analog signals output by the PHY communication module are transmitted to the network transformer, the network transformer can filter differential signals in the analog signals transmitted by the PHY communication module by using the coil coupling of differential mode coupling to strengthen the signals, and the differential signals are coupled to the other end of the connecting network cable through the conversion of electromagnetic fields to realize electric isolation and signal transmission, the anti-interference unit further plays an anti-interference role on the analog signals output by the network transformer, the analog signals processed by the network transformer and the anti-interference unit are transmitted to the RJ45 network interface module, and the RJ45 network interface module transmits the analog signals to network equipment.

Preferably, the device further comprises a voltage stabilizing module, wherein the voltage stabilizing module comprises a TVS diode group, and two poles of a TVS diode of the TVS diode group are connected with the PHY communication module and the network transformer.

By adopting the technical scheme, the TVS diode has higher current conduction capability, when the two poles of the TVS diode are impacted by reverse transient high energy, the high resistance between the two poles is changed into low resistance at the speed of 10-12S level, and the surge power of thousands of watts is absorbed at the same time, so that the voltage clamp between the two poles is positioned at a safe value, and the precise components in the electronic circuit are effectively protected from being damaged by the surge pulse.

Preferably, the anti-interference unit comprises a first anti-interference circuit and a second anti-interference circuit, and the first anti-interference circuit and the second anti-interference circuit are both connected with the network transformer.

Through adopting above-mentioned technical scheme, first anti-interference circuit and second anti-interference circuit all are connected with the network transformer, and first anti-interference circuit and second anti-interference circuit play the filtering effect jointly to the interference signal of circuit for the circuit remains stable.

Preferably, the first anti-interference circuit comprises a first resistor, a first high-voltage capacitor and a first gas discharge tube, the second anti-interference circuit comprises a second resistor, a second high-voltage capacitor and a second gas discharge tube, one end of the first gas discharge tube is connected between the network transformer and the first resistor, the other end of the first resistor is connected with one end of the first high-voltage capacitor, the other end of the first gas discharge tube is connected with the other end of the first high-voltage capacitor and then grounded, one end of the second gas discharge tube is connected between the network transformer and the second resistor, the other end of the second resistor is connected with one end of the second high-voltage capacitor, and the other end of the second gas discharge tube is connected with the other end of the second high-voltage capacitor and then grounded.

By adopting the technical scheme, when surge (common mode) or static electricity is coupled in from the network cable, the first gas discharge tube and the second gas discharge tube can discharge most of interference signals to the ground, so that a later-stage circuit is protected from being damaged.

Preferably, the PHY communication module includes a PHY chip, a crystal oscillator clock unit and a status indication unit, where the crystal oscillator clock unit and the status indication unit are connected with the PHY chip.

Through adopting above-mentioned technical scheme, crystal oscillator clock unit and status indication unit all are connected with the PHY chip, and crystal oscillator clock unit provides basic clock signal for the PHY chip, and the crystal oscillator clock unit combines the circuit of PHY chip inside, produces the clock frequency that the PHY chip must for the PHY chip operation is more stable, and status indication unit indicates network connection state and net speed condition, makes operating personnel have certain understanding to the network situation.

Preferably, the model of the PHY chip is LAN8720A-CP-TR, and the intensity of a radiation electric field induced by a signal wire of a REFCLK pin of the PHY chip when the signal wire is transmitted is 15dBuV/m-45dBuV/m.

By adopting the technical scheme, the intensity range of the radiation electric field caused by signal transmission of the signal wire of the REFCLK pin of the PHY chip is 15dBuV/m-45dBuV/m, so that the use standard of the Ethernet in the industrial environment is achieved, and the Ethernet can be used in the industrial environment. Preferably, the TVS diode group includes a first TVS diode and a second TVS diode, one end of the first TVS diode is connected with a twenty-first pin of the PHY chip, the other end of the first TVS diode is connected with a twentieth pin of the PHY chip, one end of the second TVS diode is connected with a twenty-third pin of the PHY chip, the other end of the second TVS diode is connected with a twenty-second pin of the PHY chip, and both ends of the first TVS diode and both ends of the second TVS diode are connected with the network transformer.

Through adopting above-mentioned technical scheme, first TVS diode and second TVS diode are connected between PHY chip and network transformer, filter differential mode surge to a certain extent, weaken pulse signal's intensity to reduce pulse signal and get into the transient voltage of PHY chip, effectively improve Ethernet circuit's interference killing feature.

In summary, the present application includes at least one of the following beneficial technical effects: the network equipment sends analog signals to the PHY communication module through the RJ45 network interface module, the PHY communication module converts the analog signals into digital signals and transmits the digital signals to the filtering module, the filtering module filters the digital signals, the MCU module recognizes the digital signals and processes the digital signals, the MCU module transmits the processed digital signals to the filtering module, the filtering module filters the digital signals, the filtered digital signals are transmitted to the PHY communication module, the PHY communication module converts the digital signals into analog signals and transmits the analog signals to the network equipment through the RJ45 network interface module, the MCU module is arranged on the equipment controller, communication between the network equipment and the equipment controller is realized through signal transmission among the RJ45 communication module, the PHY communication module, the filtering module and the MCU module, the filtering module filters sharp waves in the digital signals in the digital signal transmission process, the signals are not easy to be interfered on the premise of meeting normal functions, the radiation is obviously weakened, the radiation interference of an Ethernet circuit is reduced, and the radiation resistance of the Ethernet is improved.

Drawings

FIG. 1 is a flow diagram of an embodiment of the present application.

Fig. 2 is a schematic circuit diagram of an embodiment of the present application.

Fig. 3 is a circuit schematic of a PHY communication module in an embodiment of the application.

Fig. 4 is a schematic circuit diagram of a filter module in an embodiment of the application.

Fig. 5 is a diagram of radiation authentication prior to filtering in accordance with an embodiment of the present application.

Fig. 6 is a filtered radiation authentication graph of an embodiment of the present application.

Fig. 7 is a waveform diagram of a clock line prior to filtering in accordance with an embodiment of the present application.

Fig. 8 is a waveform diagram of a filtered clock line according to an embodiment of the present application.

Fig. 9 is a schematic circuit diagram of a voltage regulator module in an embodiment of the application.

Fig. 10 is a schematic circuit diagram of an immunity module in an embodiment of the application.

Fig. 11 is a schematic circuit diagram of an RJ45 network interface module in an embodiment of the application.

Reference numerals illustrate: 1. a filtering module; 11. a first filtering unit; 12. a second filtering unit; 2. a PHY communication module; 21. a crystal oscillator clock unit; 3. a voltage stabilizing module; 31. TVS diode group; 4. an anti-interference module; 41. an anti-interference unit; 411. a first anti-interference circuit; 412. a second anti-interference circuit; 5. RJ45 network interface module.

Detailed Description

The application is described in further detail below with reference to fig. 1-11.

The embodiment of the application discloses a high-reliability EMI friendly Ethernet circuit which is applied to communication connection between an equipment controller and network equipment, wherein the equipment controller can be a tension controller, a sensor interface is arranged on the equipment controller, and a sensor sends a sensor value to the equipment controller through the sensor interface. When the network device needs the sensor value, the network device sends a query signal to the device controller through the Ethernet, and the device controller transmits the sensor value to the network device through the Ethernet. The query signal sent by the network device is an analog signal, and the sensor value sent by the device controller is a digital signal. Referring to fig. 1 and 2, the circuit includes an MCU module, a filter module 1, a PHY communication module 2, a voltage stabilizing module 3, an immunity module 4 and an RJ45 network interface module 5, the MCU module is connected with the filter module 1, the filter module 1 is connected with the PHY communication module 2, the PHY communication module 2 is connected with the voltage stabilizing module 3, the voltage stabilizing module 3 is connected with the immunity module 4, and the immunity module 4 is connected with the RJ45 network interface module 5. The RJ45 network interface module 5 is used for connecting network equipment, the PHY communication module 2 is used for converting analog signals into digital signals and transmitting the digital signals, the filtering module 1 is used for filtering the digital signals, and the MCU module is used for analyzing and processing the filtered digital signals. The MCU module comprises an MCU chip, the MCU chip is arranged on the equipment controller, the model of the MCU chip is STM32F407VET6, and the communication between the equipment controller and the network equipment is realized through the signal transmission among the MCU chip, the PHY communication module 2 and the RJ45 network interface module 5.

Correspondingly, the network equipment sends an analog signal to the RJ45 network interface module 5, the analog signal is input to the PHY communication module 2 after passing through the voltage stabilizing module 3 and the disturbance rejection module 4, the voltage stabilizing module 3 plays a voltage stabilizing role in the signal transmission process, and the disturbance rejection module 4 plays a disturbance rejection role in the signal transmission process, so that the disturbance rejection capability of the circuit in special scenes such as industrial environments is enhanced, and the communication stability between the network equipment and the equipment controller is kept. The PHY communication module 2 converts the analog signals into digital signals and transmits the digital signals to the filtering module 1, the filtering module 1 filters the digital signals, the filtered digital signals are transmitted to the MCU chip, the MCU chip recognizes and processes the digital signals, the MCU chip transmits the processed digital signals to the filtering module 1, the filtering module 1 filters the digital signals, the filtered digital signals are transmitted to the PHY communication module 2, the PHY communication module 2 converts the digital signals into analog signals, and the analog signals are transmitted to the network equipment through the RJ45 network interface module 5 after being processed by the voltage stabilizing module 3 and the immunity module 4. The filtering module 1 filters spike waves in the digital signals in the digital signal transmission process, the signals are not easy to interfere on the premise of meeting the normal communication function, external radiation can be obviously weakened, and the radiation interference of an Ethernet circuit is reduced, so that the radiation protection performance of the Ethernet is improved.

Specifically, referring to fig. 2 and 3, the PHY communication module 2 includes a PHY chip U1, a crystal oscillator clock unit 21, and a status indication unit. The model number of PHY chip U1 is LAN8720A-CP-TR. The crystal oscillator clock unit 21 and the status indication unit are both connected with the PHY chip U1. The crystal oscillator clock unit 21 comprises a crystal oscillator chip Y1 and peripheral circuits thereof, wherein the model of the crystal oscillator chip Y1 is X503225MSB4SI, a first pin of the crystal oscillator chip Y1 is connected with a fifth pin (XTAL 1/XLKIN pin) of the PHY chip U1, and a third pin of the crystal oscillator chip Y1 is connected with a fourth pin (XTAL 2 pin) of the PHY chip U1. The status indication unit includes a network connection indicator and a network SPEED indicator, the network connection indicator is connected with a third pin (link_led pin) of the PHY chip U1, and the network SPEED indicator is connected with a second pin (speed_led pin) of the PHY chip U1. The network connection indicator lamp displays a network connection state, and when the PHY chip U1 detects that network data transmission exists, the network connection indicator lamp is controlled to be lightened, and when the PHY chip U1 detects that the CRS is high, the network connection indicator lamp is controlled to flash. When the PHY chip U1 detects that the network data is transmitted at 100M, the network speed indicator lamp is controlled to be lighted. An operator can judge the condition of the network through the network connection indicator lamp and the network speed indicator lamp so as to have a certain knowledge on the condition of the network.

The PHY chip U1 is in the ref_clk_out mode when operating, the crystal oscillator clock unit 21 provides a 25Mhz clock signal to the PHY chip U1, the crystal oscillator clock unit 21 multiplies the clock signal to 50Mhz by internal circuitry within the PHY chip U1, i.e., the clock frequency necessary for the PHY chip U1, and then outputs a 50Mhz reference clock to the MCU chip via the fourteenth pin (REFCLK pin) of the PHY chip U1. The crystal oscillator clock unit 21 provides a basic clock signal for the circuit, so that the PHY chip U1 operates more stably. During the clock signal transmission process, the radiation generated on the signal line connected to the REFCLK pin of the PHY chip U1 is relatively large, so the filter module 1 needs to be disposed on the signal line connected to the REFCLK pin of the PHY chip U1 to reduce the radiation interference.

Further, referring to fig. 2 and 4, the filter module 1 includes a first filter unit 11, the first filter unit 11 includes a pi-type filter circuit, and the pi-type filter circuit includes a first filter capacitor C89, a second filter capacitor C90, and a filter bead FB12. One end of the filter magnetic bead FB12 is connected with a fourteenth pin (REFCLK pin) of the PHY chip U1, the other end of the filter magnetic bead FB12 is connected with the MCU chip, one end of the first filter capacitor C89 is connected between the filter magnetic bead FB12 and the MCU chip, one end of the second filter capacitor C90 is connected between the filter magnetic bead FB12 and the fourteenth pin (REFCLK pin) of the PHY chip U1, and the other end of the first filter capacitor C89 and the other end of the second filter capacitor C90 are grounded.

The pi-type filter circuit forms a pi-type network structure by utilizing the combination of the first filter capacitor C89, the second filter capacitor C90 and the filter inductor FB12, realizes filter processing by selectively transmitting digital signals in a specific frequency range, divides frequency and branches based on an input signal under the action of the first filter capacitor C89, the second filter capacitor C90 and the filter inductor FB12, and finally obtains a filtered output signal. The signal line connected to the fourteenth pin (REFCLK pin) of the PHY chip U1 needs to transmit a clock signal and a digital signal, and generates large high-frequency noise and peak interference, and the radiation interference is large. The pi-type filter circuit can carry out filter processing on low-frequency and high-frequency signals, is favorable for inhibiting main frequency and harmonic waves, reduces high-frequency noise and peak interference on a signal line and a power line, improves radiation emission of the Ethernet, and can meet most of application occasions with requirements on radiation.

The specific experimental test data are shown in the attached drawings. Fig. 5 shows a radiation authentication diagram before filtering, and it can be seen that, before the filtering module 1 is introduced, the radiation electric field strength induced during signal transmission ranges from 15dBuV/m to 60dBuV/m, that is, the radiation interference is larger. As can be seen from fig. 6, after the filter module 1 is introduced, the radiation electric field intensity induced during signal transmission ranges from 15dBuV/m to 45dBuV/m, and is lower than that before the filter module 1 is introduced, thereby achieving the effect of improving radiation emission. Fig. 7 shows a waveform of the clock line, which shows that the amplitude parameter before the filter module 1 is introduced is 944mV, which is said to be relatively noisy. After the filter module 1 is introduced, as can be seen from fig. 8, the amplitude parameter is 696mV, which is lower than the amplitude parameter before the filter module 1 is introduced, thereby achieving the effect of reducing high-frequency noise and improving radiation emission.

The filtering module 1 further includes a second filtering unit 12, where the second filtering unit 12 includes a magnetic bead group including a magnetic bead FB3, a magnetic bead FB4, a magnetic bead FB5, a magnetic bead FB6, a magnetic bead FB8, a magnetic bead FB9, a magnetic bead FB10, and a magnetic bead FB11. One end of the magnetic bead FB3 is connected with a twelfth pin (MDIO pin) of the PHY chip U1, and the other end of the magnetic bead FB3 is connected with the MCU chip; one end of the magnetic bead FB4 is connected with a thirteenth pin (MDC pin) of the PHY chip U1, and the other end of the magnetic bead FB4 is connected with the MCU chip; one end of the magnetic bead FB5 is connected with a sixteenth pin (TXEN pin) of the PHY chip U1, and the other end of the magnetic bead FB5 is connected with the MCU chip; one end of the magnetic bead FB6 is connected with a seventeenth pin (TXD 0 pin) of the PHY chip U1, and the other end of the magnetic bead FB6 is connected with the MCU chip; one end of the magnetic bead FB8 is connected with an eighteenth pin (TXD 1 pin) of the PHY chip U1, and the other end of the magnetic bead FB8 is connected with the MCU chip; one end of the magnetic bead FB9 is connected with an eighth pin (RXD 0 pin) of the PHY chip U1, and the other end of the magnetic bead FB9 is connected with the MCU chip; one end of the magnetic bead FB10 is connected with a seventh pin (RXD 1 pin) of the PHY chip U1, and the other end of the magnetic bead FB10 is connected with the MCU chip; one end of the magnetic bead FB11 is connected with an eleventh pin (CSR_DV pin) of the PHY chip U1, and the other end of the magnetic bead FB11 is connected with the MCU chip. When the PHY chip U1 and the MCU chip are used for signal transmission, the magnetic beads inhibit high-frequency noise and peak interference on the signal line and the power line, so that radiation on the signal line and the power line is reduced, the radiation protection performance of the Ethernet is further improved, and the circuit is stable due to the capability of absorbing electrostatic pulses.

Referring to fig. 2 and 9, the voltage stabilizing module 3 includes a TVS diode group 31, the TVS diode group 31 includes a first TVS diode D10 and a second TVS diode D13, one end of the first TVS diode D10 is connected to a twenty-first pin (td_p pin) of the PHY chip U1, the other end of the first TVS diode D10 is connected to a twentieth pin (td_n pin) of the PHY chip U1, one end of the second TVS diode D13 is connected to a twenty-third pin (rd_p pin) of the PHY chip U1, and the other end of the second TVS diode D13 is connected to a twenty-second pin (rd_n pin) of the PHY chip U1. Both ends of the first TVS diode D10 and both ends of the second TVS diode D13 are connected to the immunity module 4. If the voltage is higher than the breakdown voltage of the first TVS diode D10 and the second TVS diode D13, the first TVS diode D10 and the second TVS diode D13 will be turned on, and the first TVS diode D10 and the second TVS diode D13 have higher current conduction capability. When the two poles of the first TVS diode D10 and the second TVS diode D13 are subjected to reverse transient high-energy impact, the high-resistance between the two poles is changed into low-resistance at the speed of the magnitude of 10-12S, and the surge power of thousands of watts is absorbed at the same time, so that the voltage clamp between the two poles is positioned at a safe value, the precise components in an electronic circuit are effectively protected from being damaged by surge pulses, the first TVS diode D10 and the second TVS diode D13 are connected between the PHY chip U1 and the anti-interference module 4, differential mode surge is filtered to a certain extent, the strength of pulse signals is weakened, the transient voltage of the pulse signals entering the PHY chip U1 is reduced, the anti-interference capability of an Ethernet circuit is effectively improved, and the reliability of products is improved.

When the PHY chip U1 receives the digital signal sent by the MCU chip, the digital signal is converted into an analog signal, and then the analog signal is transmitted to the network device through the RJ45 network interface module 5. However, in the case of a relatively long network transmission distance, it is sometimes necessary to send the network transmission distance to an address of 100 meters or more, which may lead to signal loss. In addition, the external network cable is directly connected with the PHY chip U1, electromagnetic induction and static electricity also easily cause damage to the PHY chip U1, and in order to ensure the safety of the integrated circuit chip, reduce error codes caused by external EMI and inhibit electromagnetic noise emission energy in a circuit, an anti-interference module 4 is arranged between the PHY chip U1 and the RJ45 network interface module 5.

Referring to fig. 2 and 10, the immunity module 4 includes a network transformer T2 and an anti-interference unit 41, the model of the network transformer T2 is HR641680E, a first pin (td+ pin) of the network transformer T2 is connected between the first TVS diode D10 and a twenty-first pin (td_p pin) of the PHY chip U1, and a third pin (TD-pin) of the network transformer T2 is connected between the first TVS diode D10 and a twentieth pin (td_n pin) of the PHY chip U1. The sixth pin (rd+ pin) of the network transformer T2 is connected between the second TVS diode D13 and the twenty-third pin (rd_p pin) of the PHY chip U1, the eighth pin (RD-pin) of the network transformer T2 is connected between the second TVS diode D13 and the twenty-second pin (rd_n pin) of the PHY chip U1, and the network transformer T2 is connected with the RJ45 network interface module 5. The network transformer T2 has the functions of increasing driving capability, enhancing anti-interference capability, impedance matching and protecting isolation.

The anti-interference unit 41 is connected with the network transformer T2, the anti-interference unit 41 further plays an anti-interference role on the signal output by the network transformer T2, the analog signal processed by the network transformer T2 and the anti-interference unit 41 is transmitted to the RJ45 network interface module 5, and the RJ45 network interface module 5 transmits the analog signal to network equipment. The network transformer T2 can transmit data, can filter differential signals in analog signals output by the PHY chip U1 by using coil coupling of differential mode coupling to enhance the signals, and is coupled to the other end of the connecting network cable with different levels through the conversion of electromagnetic fields; different levels between different network devices connected by the network cable can be isolated, so that the devices are prevented from being damaged by different voltages transmitted by the network cable; the PHY chip U1 end can be isolated from the outside, the anti-interference capability is greatly enhanced, and a great protection effect is added to the PHY chip U1, so that the PHY chip U1 is protected from damage (such as lightning) caused by electrical errors.

Specifically, the anti-interference unit 41 includes a first anti-interference circuit 411 and a second anti-interference circuit 412, and the first anti-interference circuit 411 and the second anti-interference circuit 412 are both connected to the network transformer T2. The first anti-interference circuit 411 and the second anti-interference circuit 412 are both connected with the network transformer T2, and the first anti-interference circuit 411 and the second anti-interference circuit 412 together filter interference signals of the circuit, so that the circuit is kept stable.

The first anti-interference circuit 411 includes a first resistor R75, a first high-voltage capacitor C83, and a first gas discharge tube G3, and the second anti-interference circuit 412 includes a second resistor R76, a second high-voltage capacitor C101, and a second gas discharge tube G4. One end of the first gas discharge tube G3 is connected between the fifteenth pin (CT pin) of the network transformer T2 and the first resistor R75, and the other end of the first resistor R75 is connected to one end of the first high-voltage capacitor C83, and the other end of the first gas discharge tube G3 is grounded after being connected to the other end of the first high-voltage capacitor C83. One end of the second gas discharge tube G4 is connected between the tenth pin (CT pin) of the network transformer T2 and the second resistor R76, the other end of the second resistor R76 is connected to one end of the second high-voltage capacitor C101, and the other end of the second gas discharge tube G4 is connected to the other end of the second high-voltage capacitor C101 and then grounded. When a surge (common mode) or static electricity is coupled in from the network cable, the first gas discharge tube G3 and the second gas discharge tube G4 can discharge most of interference signals to the ground, thereby protecting the subsequent-stage circuit from damage.

Furthermore, referring to fig. 2 and 11, the RJ45 network interface module 5 includes an RJ45 connector J2, the RJ45 connector J2 being of the type R-RJ45R08P-C000. The first pin (tx+ pin) of the RJ45 connector J2 is connected with the sixteenth pin (tx+ pin) of the network transformer T2, the third pin (rx+ pin) of the RJ45 connector J2 is connected with the eleventh pin (rx+ pin) of the network transformer T2, the sixth pin (RX-pin) of the RJ45 connector J2 is connected with the ninth pin (RX-pin) of the network transformer T2, the ninth pin (ledl+ pin) of the RJ45 connector J2 is connected with the network connection indicator lamp, and the tenth pin (LEDL-pin) of the RJ45 connector J2 is connected with the network speed indicator lamp. The RJ45 connector J2 is connected with one end of a network cable, the other end of the network cable is connected with network equipment, and the network equipment transmits signals through the RJ45 connector J2.

The implementation principle of the high-reliability EMI friendly Ethernet circuit provided by the embodiment of the application is as follows:

The network device sends out an analog signal, the analog signal is transmitted to the PHY chip U1 through the network transformer T2 and the TVS diode group 31, the PHY chip U1 converts the analog signal into a digital signal, the digital signal is transmitted to the MCU chip after being filtered by the pi-type filter circuit and the magnetic bead group, and the pi-type filter circuit can reduce the Ethernet radiation. The pi-type filter circuit and the magnetic beads filter spike waves in the digital signals in the digital signal transmission process, the signals are not easy to interfere on the premise of meeting the normal communication function, external radiation can be obviously weakened, radiation interference of the Ethernet circuit is reduced, and therefore the radiation protection performance of the Ethernet is improved.

The MCU chip analyzes and processes the received digital signals and then sends out processed digital signals, the processed digital signals are filtered by the pi-type filter circuit and the magnetic bead group and then are transmitted to the PHY chip U1, the PHY chip U1 converts the digital signals into analog signals, and the analog signals are transmitted to network equipment through the TVS diode group 31 and the network transformer T2 and then through the RJ45 connector J2. The TVS diode group 31 can weaken the intensity of pulse signals, and the network transformer T2 increases the driving capability and anti-interference capability of the circuit, and also has the functions of impedance matching and protection isolation. The anti-interference capability of the circuit is enhanced in special scenes such as industrial environments, so that communication stability between the network equipment and the MCU chip is kept.

The above embodiments are not intended to limit the scope of the present application, so: all equivalent changes in structure, shape and principle of the application should be covered in the scope of protection of the application.

Claims (6)

1. A high reliability EMI friendly ethernet circuit characterized by: the device comprises an MCU module, a filtering module (1), a PHY communication module (2) and an RJ45 network interface module (5), wherein the MCU module is connected with the filtering module (1), the filtering module (1) is connected with the PHY communication module (2), and the PHY communication module (2) is connected with the RJ45 network interface module (5), wherein:

the RJ45 network interface module (5) is used for connecting network equipment;

the PHY communication module (2) is used for converting analog signals into digital signals and transmitting the digital signals;

the filtering module (1) is used for filtering the digital signals;

the MCU module is used for analyzing and processing the filtered digital signals;

The filter module (1) comprises a first filter unit (11), the first filter unit (11) comprises a pi-type filter circuit, the pi-type filter circuit comprises a first filter capacitor, a second filter capacitor and a filter magnetic bead, one end of the filter magnetic bead is connected with the PHY communication module (2), the other end of the filter magnetic bead is connected with the MCU module, one end of the first filter capacitor is connected between the filter magnetic bead and the MCU module, one end of the second filter capacitor is connected between the filter magnetic bead and the PHY communication module (2), and the other end of the first filter capacitor and the other end of the second filter capacitor are grounded;

The anti-interference device further comprises an anti-interference module (4), wherein the anti-interference module (4) comprises a network transformer and an anti-interference unit (41), the network transformer is connected with the PHY communication module (2), the network transformer is connected with the RJ45 network interface module (5), and the anti-interference unit (41) is connected with the network transformer;

The anti-interference unit (41) comprises a first anti-interference circuit (411) and a second anti-interference circuit (412), and the first anti-interference circuit (411) and the second anti-interference circuit (412) are connected with the network transformer;

The first anti-interference circuit (411) comprises a first resistor, a first high-voltage capacitor and a first gas discharge tube, the second anti-interference circuit (412) comprises a second resistor, a second high-voltage capacitor and a second gas discharge tube, one end of the first gas discharge tube is connected between the network transformer and the first resistor, the other end of the first resistor is connected with one end of the first high-voltage capacitor, the other end of the first gas discharge tube is connected with the other end of the first high-voltage capacitor and then grounded, one end of the second gas discharge tube is connected between the network transformer and the second resistor, the other end of the second resistor is connected with one end of the second high-voltage capacitor, and the other end of the second gas discharge tube is connected with the other end of the second high-voltage capacitor and then grounded.

2. A high reliability EMI friendly ethernet circuit as set forth in claim 1, wherein: the filtering module (1) further comprises a second filtering unit (12), the second filtering unit (12) comprises a magnetic bead group, and two ends of a magnetic bead of the magnetic bead group are respectively connected with the PHY communication module (2) and the MCU module.

3. A high reliability EMI friendly ethernet circuit as set forth in claim 1, wherein: the device further comprises a voltage stabilizing module (3), wherein the voltage stabilizing module (3) comprises a TVS diode group (31), and two poles of the TVS diode group (31) are connected with the PHY communication module (2) and the network transformer.

4. A high reliability EMI friendly ethernet circuit as set forth in claim 3, wherein: the PHY communication module (2) comprises a PHY chip, a crystal oscillator clock unit (21) and a state indicating unit, wherein the crystal oscillator clock unit (21) and the state indicating unit are connected with the PHY chip.

5. The high reliability EMI friendly ethernet circuit as set forth in claim 4, wherein: the model of the PHY chip is LAN8720A-CP-TR, and the intensity range of a radiation electric field induced by a signal wire of a REFCLK pin of the PHY chip when the signal wire is transmitted is 15dBuV/m-45dBuV/m.

6. The high reliability EMI friendly ethernet circuit as set forth in claim 5, wherein: the TVS diode group (31) comprises a first TVS diode and a second TVS diode, one end of the first TVS diode is connected with a TD_P pin of the PHY chip, the other end of the first TVS diode is connected with a TD_N pin of the PHY chip, one end of the second TVS diode is connected with a RD_P pin of the PHY chip, the other end of the second TVS diode is connected with a RD_N pin of the PHY chip, and both ends of the first TVS diode and both ends of the second TVS diode are connected with a network transformer.