CN117457649A

CN117457649A - Low-voltage SCR structure protection device triggered by gate control diode

Info

Publication number: CN117457649A
Application number: CN202311682819.6A
Authority: CN
Inventors: 郝壮壮; 张伟; 赵德益; 蒋骞苑; 苏海伟; 叶毓明
Original assignee: Shanghai Wei'an Semiconductor Co ltd
Current assignee: Shanghai Wei'an Semiconductor Co ltd
Priority date: 2023-12-08
Filing date: 2023-12-08
Publication date: 2024-01-26

Abstract

The invention provides a low-voltage SCR structure protection device triggered by a gate-controlled diode, which relates to the field of semiconductor technology and includes: a substrate, an epitaxial layer is grown upward on the substrate, and N-type well regions and P-type well regions are respectively formed on the epitaxial layer. ;The tops of the N-type well region and the P-type well region are doped to form a P-type lightly doped region and an N-type lightly doped region, and the P-type lightly doped region and the N-type lightly doped region of the N-type well region are connected As the anode, the P-type lightly doped region and the N-type lightly doped region of the P-type well region are connected as the cathode; the tunnel junction region is formed on the top of the side of the P-type well region close to the N-type well region; at least one The gate-controlled diode covers the top of the epitaxial layer between the N-type well region and the P-type well region and part of the tunnel junction region. The beneficial effect is to form a tunnel junction in the epitaxial layer, so that the protection device has low capacitance, low leakage, and low turn-on voltage. At the same time, the gate has higher withstand voltage characteristics, which improves the protection effect and robustness of the subsequent circuit.

Description

Low-voltage SCR structure protection device triggered by gate control diode

Technical Field

The invention relates to the technical field of semiconductors, in particular to a low-voltage SCR structure protection device triggered by a gate control diode.

Background

In recent years, the development of integrated circuit manufacturing technology is rapid, rapid updating and updating of electronic products are brought, and low-voltage and ultra-high-speed data transmission interfaces such as USB3.1, HDMI2.1, type-C and the like are widely applied to the electronic products. In order to ensure the quality and reliability of electronic products, the chip and the circuit of the external interface must have a certain level of ESD resistance, so that more and more protection devices are required. SCR (Silicon-Controlled Rectifier), which is a protective device with strong robustness per unit area and small parasitic capacitance, is widely applied to various products.

For SCR protection devices required in low operating voltage (1.5V-3.3V), low parasitic capacitance (< 0.5 pF) applications, there are several common conventional design structures as follows.

As shown in fig. 1, a conventional design may be designed with a lighter 300NW doping concentration and a lighter 301PW doping concentration, and at a smaller voltage, an initial current is provided through 401p+/300NW/200Epi punch-through breakdown or 200Epi/301PW/402n+ punch-through breakdown, so as to trigger the 401p+/300NW/301PW/402n+ scr structure to be turned on, thereby discharging the ESD current from the anode to the cathode and protecting the subsequent circuit. However, in the structural design of fig. 1, it is difficult to control the doping of 300NW/301PW properly, and there is a problem of large fluctuation in electrical property in mass production. In addition, 401P+/300NW/200Epi or 200Epi/301PW/402N+ forms a parasitic triode structure with a floating base electrode, and large leakage current is easy to generate under normal working voltage of a later-stage circuit, so that the work of the later-stage circuit is abnormal.

As shown in fig. 2, a conventional design is that 404n+ and 405p+ structures are added at the boundary of 300NW and 301PW, and the zener breakdown characteristic is realized by using both of the two heavy dopings at a smaller voltage, so as to provide an initial current for triggering the SCR structure. However, in this design, the heavily doped characteristics of 404n+ and 405p+ make both generate larger parasitic junction capacitance, which affects the normal transmission of high-speed data. In addition, heavily doped 404n+ and 405p+ are also prone to generate large leakage under normal operating voltages.

One conventional design, as shown in fig. 3, is to add a gated diode between 300NW and 301PW, with 404n+ and 405p+ forming the diode cathode and anode, with 500 gate oxide and 501 gate as the gated diode. The 501 grid is usually connected with the anode directly to provide a potential higher than 405P+ and can also be connected with an external trigger circuit, and the trigger circuit provides a potential higher than 405P+ so as to turn on the SCR structure. In principle, the 501 grid electrode applies potential to a 200Epi channel region under a 500 grid oxide layer under a certain high potential, so that the energy band barrier width at a 404N+/200Epi interface or a 200Epi/405P+ interface is reduced, and after a certain barrier width is met, carriers can cross a junction barrier through band tunneling effect, so that initial current is formed, and an SCR structure is triggered to discharge ESD current.

There are several major problems with this design:

<1>.404n+ as a heavily doped region, parasitic capacitance is increased;

when the length of the grid electrode of <2>.501 is smaller, the heavily doped 404N+ enables the depletion region under normal working voltage to expand to 200Epi and 301PW regions, and the punch-through electric leakage between the depletion region and 402N+ is easy to cause;

<3>. Since the SCR structure needs to be turned on by providing an initial current at a small voltage, the 500 gate oxide layer needs to be made thin to ensure 501 gate control over the 200Epi channel region. When the starting voltage of 1.5V-5V is realized, the thickness of a common 500 gate oxide layer is 20A-50A. On one hand, the method needs a more advanced manufacturing process, the manufacturing cost of the product is increased, and the gate oxide layer is easily influenced by thickness fluctuation to cause electric fluctuation of the product; on the other hand, the thinner gate oxide layer is difficult to bear higher voltage, the device robustness is poor, and the 500 gate oxide layer is easy to break down by high gate voltage in the device protection process, so that the device is invalid.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides a low-voltage silicon controlled rectifier structure protection device triggered by a grid-controlled diode, which comprises:

the substrate is upwards grown with an epitaxial layer, and an N-type well region and a P-type well region are respectively formed on the epitaxial layer;

the top of the N-type well region and the top of the P-type well region are doped to form a P-type lightly doped region and an N-type lightly doped region, the P-type lightly doped region and the N-type lightly doped region of the N-type well region are connected to serve as anodes, and the P-type lightly doped region and the N-type lightly doped region of the P-type well region are connected to serve as cathodes;

the tunneling junction region is formed at the top of one side of the P-type well region, which is close to the N-type well region;

and the gate control diode covers the top of the epitaxial layer between the N-type well region and the P-type well region and part of the tunneling junction region.

Preferably, the tunneling junction region includes:

the P-type heavily doped region is formed at the top of one side of the P-type well region, which is close to the N-type well region, the N-type doped region is formed by doping one side of the P-type heavily doped region, which is close to the N-type well region, and the gate control diode covers the top of the epitaxial layer between the N-type well region and the P-type well region and the top of the N-type doped region.

Preferably, an oxide layer is further formed between the substrate and the epitaxial layer.

Preferably, the gate control diode comprises a gate oxide layer and a gate electrode connected with the top of the gate oxide layer;

and the gate oxide layer covers the top of the epitaxial layer between the N-type well region and the P-type well region and the top of the N-type doped region.

The invention also provides a low-voltage silicon controlled rectifier structure protection device triggered by the grid-controlled diode, which comprises:

the epitaxial device comprises a substrate, wherein an epitaxial layer grows upwards on the substrate, and two symmetrical N-type well regions are formed at the top of the epitaxial layer;

a P-type lightly doped region and an N-type lightly doped region are formed on the top of each N-type well region in a doped manner, and the P-type lightly doped region and the N-type lightly doped region in each N-type well region are connected to serve as a first electrode and a second electrode respectively;

the tunneling junction region is formed between the two N-type well regions;

and each grid-controlled diode corresponds to one N-type well region, and each grid-controlled diode covers the top of the epitaxial layer and the top of part of the tunneling junction region between the corresponding N-type well region and the tunneling junction region.

Preferably, the tunneling junction region includes:

the P-type heavily doped region is formed between the two N-type well regions, and two sides, close to each N-type well region, of the P-type heavily doped region are doped respectively to form N-type doped regions;

each gate control diode covers the top of the epitaxial layer between the corresponding N-type well region and the tunneling junction region and the top of the N-type doped region on the corresponding side.

the gate oxide layer covers the top of the epitaxial layer between the corresponding N-type well region and the tunneling junction region and the top of the N-type doped region on the corresponding side.

The technical scheme has the following advantages or beneficial effects: a tunneling junction is formed in the epitaxial layer, the width of a potential barrier at the tunneling junction can be narrowed and the electric field can be enhanced by the N region with specific doping concentration, so that the gate control diode can be started under a thicker gate oxide layer and a lower voltage, enough initial current is provided to trigger the SCR structure, the SCR structure has low capacitance, low electric leakage and low starting voltage, meanwhile, the grid electrode has higher voltage-resisting characteristic, and the protection effect and the robustness of a later-stage circuit are improved.

Drawings

FIG. 1 is a conventional SCR protective device design;

FIG. 2 is a conventional SCR protective device design;

FIG. 3 is a conventional SCR protective device design;

FIG. 4 is a schematic diagram of a low voltage SCR structure protection device triggered by a gate control diode according to a first embodiment of the present invention;

FIG. 5 is a band diagram of a region 5nm under a gate oxide layer at the same voltage in the first embodiment;

FIG. 6 shows the electric field strength in the region 5nm below the gate oxide layer at the same voltage in the first embodiment;

FIG. 7 is a graph showing the IV test curves of three 20um length cells in accordance with the first embodiment;

FIG. 8 is a CV test curve of a 20um length cell of two structures of a conventional design (40A gate oxide thickness) and a proprietary design (250A gate oxide thickness) in the first embodiment;

FIG. 9 is a schematic diagram of a low voltage SCR structure protection device with an oxide layer added in accordance with the first embodiment;

fig. 10 is a schematic structural diagram of a low-voltage SCR structure protection device with a dual gate structure in the first embodiment;

FIG. 11 is a cross-sectional view of A-A' of FIG. 10;

FIG. 12 is a cross-sectional view of B-B' of FIG. 10;

fig. 13 is a schematic structural diagram of a low-voltage SCR structure protection device triggered by a gate control diode in the second embodiment;

fig. 14 is a schematic structural diagram of a low-voltage SCR structure protection device with a dual gate structure in the second embodiment.

Detailed Description

The invention will now be described in detail with reference to the drawings and specific examples. The present invention is not limited to the embodiment, and other embodiments may fall within the scope of the present invention as long as they conform to the gist of the present invention.

In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, there is now provided a low-voltage SCR structure protection device triggered by a gate control diode, as shown in fig. 4, comprising:

the substrate 1, the substrate 1 grows upwards and has the epitaxial layer 2, there are N type trap area 3 and P type trap area 31 on the epitaxial layer 2 separately;

the top of the N-type well region 3 and the top of the P-type well region 31 are doped with P-type lightly doped regions 41 and 43 and N-type lightly doped regions 40 and 42, the P-type lightly doped region 41 and the N-type lightly doped region 40 of the N-type well region 3 are connected to serve as anodes, and the P-type lightly doped region 43 and the N-type lightly doped region 42 of the P-type well region 31 are connected to serve as cathodes;

a tunneling junction region 7 formed on top of one side of the P-type well region 31 close to the N-type well region 3;

at least one gated diode 5, the gated diode 5 overlying the top of the epitaxial layer 2 between the N-well region 3 and the P-well region 31 and a portion of the tunnel junction region 7.

Embodiment one:

in this embodiment, as shown in fig. 4, the tunneling junction region 7 includes:

the P-type heavily doped region 45, the P-type heavily doped region 45 is formed on the top of one side of the P-type well region 31, and one side of the P-type heavily doped region 45, which is close to the N-type well region 3, is doped to form an N-type doped region 6;

the gated diode 5 overlies the top of the epitaxial layer 2 and the top of the N-doped region 6 between the N-well 3 and the P-well 31.

In this embodiment, the doping concentration of the N-type doped region 6 is 1E 17-1E 19, and the length is 0.05 um-0.5 um.

In this embodiment, the gated diode 5 includes a gate oxide layer 51 and a gate electrode 52 connected to the top of the gate oxide layer;

the gate oxide layer 51 covers the top of the epitaxial layer 2 and the top of the N-doped region 6 between the N-well region 3 and the P-well region 31.

Specifically, the Epi2 is an intrinsic epitaxial layer, and can be realized by lightly doped N-epitaxy or P-epitaxy in process manufacture, and the preferable doping concentration is 2E 12-5E 13.P+45 is a heavily doped region, and the preferred doping concentration is 1E 19-3E 20. The N region 6 is an N-type doped region 6, the doping morphology of the N-type doped region can obviously adjust the overall starting voltage of the device, when the low starting voltage is required, the preferable doping concentration is 1E 17-1E 19, and the preferable length is 0.05 um-0.5 um. The thickness of the gate oxide layer 51 is preferably 100A to 500A, and a withstand voltage of about ten to several tens volts can be provided. The gate oxide layer 51 and the gate 52 cross over NW3, N region 6, p+45 to form the gated diode 5. The anode of the gated diode 5 is composed of P + 45. The cathode of the grid-controlled diode 5 is formed by NW3, and the doping concentration of the NW3 is lighter, so that low parasitic capacitance is realized on one hand; on the other hand, the expansion of the depletion region in the Epi2 and PW31 under the working voltage is restrained, and the leakage current is reduced. The N region 6 and p+45 form a tunneling junction region 7, and the N region 6 with specific doping concentration can narrow the barrier width at the tunneling junction and enhance the electric field, so that under the thicker gate oxide layer 51, the turn-on of the gate control diode 5 can be realized under lower voltage, and enough initial current is provided to trigger the SCR structure.

Based on the 1.5V working voltage application design, the three structures of the traditional design (40A gate oxide thickness), the traditional design (250A gate oxide thickness) and the patent design (250A gate oxide thickness) are compared. Fig. 5 is a band diagram of a region 5nm under the gate oxide layer 51 at the same voltage. Fig. 6 shows the electric field strength in the region 5nm below the gate oxide layer 51 under the same voltage. Fig. 7 shows IV test curves for three 20um length cells.

Based on the conventional design (40A gate oxide thickness), compared with the conventional design (250A gate oxide thickness), it can be seen that the influence of the gate on the underlying channel region is weakened due to the influence of the thicker gate oxide, the width of the energy band barrier is widened as seen in fig. 5, and the peak value of the electric field strength is weakened as seen in fig. 6. As the field strength is reduced and the potential barrier is widened, the tunneling of the carrier potential barrier becomes more difficult, and it can be seen from fig. 7 that the conventional design (250A gate oxide thickness) structure still has no initial current after the voltage is greater than 1.5V, which can cause the SCR structure to be unable to be opened in time in ESD protection, resulting in the loss of protection effect.

The patent design (250A gate oxide thickness) was again compared. Due to the introduction of the N-doped region 6, even under a gate oxide layer of 250A thickness, the barrier width of the patent design is seen to be narrowest from fig. 5, and the electric field strength peak is seen to be close to that of the conventional design (40A gate oxide layer thickness) from fig. 6. Because the narrower barrier width increases the probability of carrier tunneling barrier, it can be seen from fig. 7 that the patent design (250A gate oxide thickness) structure has an initial current after the voltage is greater than 1.5V, which is beneficial to triggering the SCR structure to turn on and thus drain the ESD current.

Fig. 8 is a graph showing CV testing of 20um length cells for both conventional (40A gate oxide thickness) and proprietary (250A gate oxide thickness) designs. Therefore, the NW3 and the thicker gate oxide layer 51 are adopted to form the gate control diode 5, so that the parasitic capacitance of the whole device is effectively reduced.

In this embodiment, an oxide layer 11 is also formed between the substrate 1 and the epitaxial layer 2.

Specifically, the structure in this embodiment may also be implemented using an SOI (Silicon On Insulator ) process, and the structure is shown in fig. 9. There is a layer of BOX11 (Buried Oxide) between Sub1 and Epi 2. The oxide layer 11 can reduce parasitic effect between the device and the substrate 1; meanwhile, the thickness of the channel region below the gate oxide layer 51 can be adjusted, and the control capability of the gate 52 on the channel is improved.

Further, in this embodiment, the gate diodes 5 may be preferably arranged in two, as shown in fig. 10, and the dual gate structure is formed by using STI (Shallow Trench Isolation ) or DTI (Deep Trench Isolation, deep trench isolation) technology commonly used in the manufacturing process, and the dual gate interconnect, the gate 52 may be connected to an anode or an external trigger circuit. The schematic structural diagrams of the section A-A 'and the section B-B' of fig. 11 are shown in fig. 11 and 12. Taking STI technology as an example, a symmetrical trench structure is formed by etching 51, 52 regions. A gate oxide layer 51 is grown to a certain thickness, typically by means of thermal oxygen growth, and then a gate material is filled into the trench structure where the gate oxide layer 51 has been grown by a deposition process. The gate material may be polysilicon. The advantage of this embodiment is that when the gate electrodes 52 are applied with a voltage, the double gate electrodes 52 that are close to each other can apply stronger control to the channel, and can provide a higher electric field strength near the tunneling junction, so that an initial current composed of more tunneling currents can be generated, which is beneficial to quickly triggering the SCR structure, so as to quickly discharge the ESD current, and provide a better protection effect for the subsequent circuit.

The invention also provides a low-voltage SCR structure protection device triggered by the gate control diode, as shown in fig. 13, comprising:

the substrate 100, the substrate 100 is grown with an epitaxial layer 200 upwards, and two symmetrical N-type well regions 300 are formed on the top of the epitaxial layer;

the top of each N-type well region 300, 300 'is doped with a P-type lightly doped region 401, 401' and an N-type lightly doped region 400, 400', and the P-type lightly doped region 401, 401' and the N-type lightly doped region 400, 400 'of each N-type well region 300, 300' are connected to serve as a first electrode and a second electrode respectively;

a tunneling junction region 700 formed between the two N-type well regions 300, 300';

at least two gated diodes (500+501), (500 '+501'), each corresponding to one N-type well region 300, 300', respectively, each gated diode (500+501), (500' +501 ') covering the top of the epitaxial layer 200 and the top of a portion of the tunnel junction region 700 between the corresponding N-type well region 300, 300' and tunnel junction region 700.

Embodiment two:

in this embodiment, as shown in fig. 13, the tunneling junction 700 includes:

the P-type heavily doped region 405, wherein the P-type heavily doped region 405 is formed between the two N-type well regions 300 and 300', and two sides of the P-type heavily doped region 405, which are close to the N-type well regions 300 and 300', are doped respectively to form N-type doped regions 600 and 600';

each gated diode (500+501)/(500 '+501') covers the top of the epitaxial layer 2 between the corresponding N-type well region 300/300 'and the tunnel junction region 700 and the top of the corresponding N-type doped region 600/600' on one side.

In this embodiment, the doping concentration of the N-type doped regions 600, 600' is 1E 17-1E 19, and the length is 0.05 um-0.5 um.

In this embodiment, the gated diode includes a gate electrode 501/501' connected to the top of the gate oxide layer 500/500' and the gate oxide layer 500/500 ';

the gate oxide layer 500/500' covers the top of the epitaxial layer 2 between the corresponding N-type well region 300/300' and the tunnel junction region 700 and the top of the corresponding N-type doped region 600/600' on one side.

Specifically, the embodiment can implement a protection device with a bidirectional SCR structure by symmetrical design, and the structure is shown in fig. 13. The first gate 501 is commonly connected to a first electrode formed by n+400 and p+401 or an external trigger circuit to provide a potential higher than p+45, or may be connected to an external trigger circuit to provide a potential higher than p+45, so as to promote the carrier tunneling junction barrier to generate an initial current, thereby turning on the SCR structure. Likewise, the second gate 501' may be connected to a second electrode formed of n+400', p+401', or an external trigger circuit. The structure can realize the SCR protection from the first electrode to the second electrode or from the second electrode to the first electrode.

Preferably, the gate diode 5 may also be preferably arranged in four, as shown in the top view of fig. 14, and the dual gate structure is also formed by using STI (Shallow Trench Isolation ) or DTI (Deep Trench Isolation, deep trench isolation) technology commonly used in the manufacturing process, and the dual gate interconnect is formed, and the gate may be connected to the anode or the external trigger circuit. Taking STI technology as an example, a symmetrical trench structure is formed by etching 500, 501 regions. A gate oxide layer 500 is grown to a certain thickness, typically by thermal oxygen growth, and then a gate material is filled into the trench structure where the gate oxide layer 500 has been grown by a deposition process. The gate material may be polysilicon. The advantage of this embodiment is that when the gate 501 is applied with a voltage, the double gates 501 close to each other can apply stronger control to the channel, and can provide higher electric field strength near the tunneling junction 700, so as to generate more initial current composed of tunneling current, which is beneficial to quickly triggering the SCR structure, so as to quickly release ESD current, and provide better protection effect for the subsequent circuit.

In this embodiment, an oxide layer 101 is further formed between the substrate 100 and the epitaxial layer 200.

The structure in this embodiment may also be implemented using a SOI (Silicon On Insulator ) process. There is a layer of BOX101 (Buried Oxide) between Sub100 and Epi 200. The oxide layer 101 can reduce parasitic effects between the device and the substrate 100; meanwhile, the thickness of the channel region below the gate oxide layer 500 can be adjusted, so that the control capability of the gate 501 on the channel is improved.

The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations herein, which should be included in the scope of the present invention.

Claims

1. A gate controlled diode triggered low voltage silicon controlled rectifier structural protection device comprising:

2. The low voltage silicon controlled rectifier structure protection device of claim 1, wherein the tunnel junction region comprises:

3. The low voltage silicon controlled rectifier structure protection device of claim 1, wherein an oxide layer is further formed between the substrate and the epitaxial layer.

4. The low voltage silicon controlled rectifier structure protection device of claim 2, wherein the gated diode comprises a gate oxide layer and a gate connected to a top of the gate oxide layer;

5. A gate controlled diode triggered low voltage silicon controlled rectifier structural protection device comprising:

the tunneling junction region is formed between the two N-type well regions;

6. The low voltage silicon controlled rectifier structure protection device of claim 5, wherein said tunnel junction region comprises:

7. The low voltage silicon controlled rectifier structure protection device of claim 5, further comprising an oxide layer formed between the substrate and the epitaxial layer.

8. The low voltage silicon controlled rectifier structure protection device of claim 7, wherein the gated diode comprises a gate oxide layer and a gate connected to a top of the gate oxide layer;