[go: up one dir, main page]

CN117457048B - Signal processing circuit and memory - Google Patents

Signal processing circuit and memory Download PDF

Info

Publication number
CN117457048B
CN117457048B CN202311760895.4A CN202311760895A CN117457048B CN 117457048 B CN117457048 B CN 117457048B CN 202311760895 A CN202311760895 A CN 202311760895A CN 117457048 B CN117457048 B CN 117457048B
Authority
CN
China
Prior art keywords
signal
command address
circuit
sampling
trigger
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202311760895.4A
Other languages
Chinese (zh)
Other versions
CN117457048A (en
Inventor
谢延鹏
唐玉玲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Storage Technology Xi'an Co ltd
Original Assignee
Changxin Storage Technology Xi'an Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Storage Technology Xi'an Co ltd filed Critical Changxin Storage Technology Xi'an Co ltd
Priority to CN202311760895.4A priority Critical patent/CN117457048B/en
Publication of CN117457048A publication Critical patent/CN117457048A/en
Application granted granted Critical
Publication of CN117457048B publication Critical patent/CN117457048B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

The embodiment of the disclosure provides a signal processing circuit and a memory, wherein the signal processing circuit comprises: the command address sampling circuit is used for carrying out sampling processing on the initial command address signals at least twice every half of an external clock period to obtain at least two command address signals, and synchronously outputting the at least two command address signals; the initial command address signal includes N command address sub-signals, N is smaller than the number M of command address pins of the semiconductor memory, and M is an integer multiple of N. Thus, when the semiconductor memory enters the circuit probe test mode, the number of the command address pins for transmission is halved, and the signal processing circuit can correctly sample and decode the CA signal at the moment.

Description

Signal processing circuit and memory
Technical Field
The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a signal processing circuit and a memory.
Background
With the continuous development of semiconductor technology, higher and higher requirements are being placed on the data transmission speed when manufacturing and using devices such as computers. In order to obtain a faster Data transmission speed, a series of devices such as a memory capable of transmitting Data at Double Data Rate (DDR) have been developed.
In a dynamic random access memory (DRAM, dynamic Random Access Memory), a Command Address (CMD/ADD) signal inputted through a Command Address pin is simply called a CA signal, and can be sampled as an Address or can be sampled and decoded as an instruction.
However, the DDR memory has different requirements for CA signal transmission in different operation modes, for example, when the DDR5 memory operates at low frequency, the semiconductor memory enters a circuit probe Test (CP Test, circuit Probe Test) mode, the number of command address pins available for transmission is reduced by half, and the original signal processing circuit cannot sample and decode the CA signal correctly.
Disclosure of Invention
Accordingly, embodiments of the present disclosure provide a signal processing circuit and a memory for solving at least one technical problem existing in the prior art.
An aspect of an embodiment of the present disclosure provides a signal processing circuit for a semiconductor memory; the signal processing circuit includes: the command address sampling circuit is used for carrying out sampling processing on the initial command address signals at least twice every half of an external clock period to obtain at least two command address signals, and synchronously outputting the at least two command address signals; the initial command address signal includes N command address sub-signals, N is smaller than the number M of command address pins of the semiconductor memory, and M is an integer multiple of N.
In some embodiments, the command address sampling circuit includes:
A first sampling sub-circuit for sampling the initial command address signal at a first time and outputting a first command address signal containing first command address information;
A second sampling sub-circuit for sampling the initial command address signal at a second time and outputting a second command address signal containing second command address information in synchronization with the first command address signal; the second time is delayed by half the external clock period from the first time.
In some embodiments, the command address sampling circuit further comprises:
A third sampling sub-circuit for sampling the initial command address signal at a third time and outputting a third command address signal containing third command address information in synchronization with the first command address signal; the third time is delayed by half of the external clock period than the second time;
A fourth sampling sub-circuit for sampling the initial command address signal at a fourth time and outputting a fourth command address signal containing fourth command address information in synchronization with the first command address signal; the fourth time is delayed from the third time by half of the external clock period.
In some embodiments, the first sampling sub-circuit includes a first flip-flop, a second flip-flop, and a third flip-flop;
the data input end of the first trigger receives the initial command address signal, the data output end of the first trigger is connected with the data input end of the second trigger, and the clock input end of the first trigger receives a first internal clock signal;
The clock input end of the second trigger receives the first internal clock signal, and the data output end of the second trigger is connected with the data input end of the third trigger;
the clock input end of the third trigger receives a second internal clock signal, and the data output end of the third trigger outputs the first command address signal;
the first internal clock signal is complementary to the second internal clock signal, and the first internal clock signal and the second internal clock signal are the same frequency as the external clock signal.
In some embodiments, the second sampling sub-circuit includes a fourth flip-flop and a fifth flip-flop;
the output and input end of the fourth trigger receives the initial command address signal, the data output end of the fourth trigger is connected with the data input end of the fifth trigger, and the clock input end of the fourth trigger receives the second internal clock signal;
The clock input end of the fifth trigger receives the second internal clock signal, and the data output end of the fifth trigger outputs the second command address signal.
In some embodiments, the third sampling sub-circuit includes the first and sixth flip-flops multiplexed with the first sampling sub-circuit;
the data input end of the sixth trigger is connected with the data output end of the first trigger, the clock input end of the sixth trigger receives the second internal clock signal, and the data output end of the sixth trigger outputs the third command address signal.
In some embodiments, the fourth sampling sub-circuit includes the fourth flip-flop multiplexed with the second sampling sub-circuit, a data output of the fourth flip-flop outputting the fourth command address signal.
In some embodiments, further comprising: a chip select signal sampling circuit and a command decoding circuit;
the chip selection signal sampling circuit is used for sampling an initial chip selection signal and outputting a first chip selection signal;
The command decoding circuit is used for receiving the first slice selection signal and i command address sub-signals for decoding and outputting command signals; wherein i is less than N;
The time when the effective signal of the first slice signal reaches the command decoding circuit is later than the time when the effective signal of all i command address sub-signals reaches the command decoding circuit, and the cut-off time of the effective signal of the first slice signal is earlier than the cut-off time of the effective signal of all i command address sub-signals.
In some embodiments, the chip select signal sampling circuit includes a seventh flip-flop, an eighth flip-flop, a delay circuit, and a latch;
the data input end of the seventh trigger receives the reverse signal of the initial chip selection signal, the clock input end of the seventh trigger receives a first internal clock signal, and the data output end of the seventh trigger outputs a first intermediate signal;
the input end of the delay circuit receives the first intermediate signal, and the output end of the delay circuit is connected with the set end of the latch and outputs a first intermediate delay signal;
The data input end of the eighth trigger receives the reverse signal of the initial chip selection signal, the clock input end of the eighth trigger receives a second internal clock signal, and the data output end of the eighth trigger is connected with the reset end of the latch and outputs a second intermediate signal;
the output end of the latch is connected with the chip selection signal input end of the command decoding circuit.
In some embodiments, the delay time of the delay circuit is greater than the maximum value of the delay difference between the start time of the active level of the initial chip select signal and the time when the active signal of the i command address sub-signals arrives at the command decoding circuit, and the delay time of the delay circuit is less than half the period of the first internal clock.
Another aspect of the disclosed embodiments provides a memory comprising a signal processing circuit as described above.
In some embodiments, the memory comprises: fifth generation double rate synchronous dynamic random access memory DDR5.
The embodiment of the disclosure provides a signal processing circuit and a memory, wherein the signal processing circuit comprises: the command address sampling circuit is used for carrying out sampling processing on the initial command address signals at least twice every half of an external clock period to obtain at least two command address signals, and synchronously outputting the at least two command address signals; the initial command address signal includes N command address sub-signals, N is smaller than the number M of command address pins of the semiconductor memory, and M is an integer multiple of N. Thus, when the semiconductor memory enters the circuit probe test mode, the number of the command address pins for transmission is halved, and the signal processing circuit can correctly sample and decode the CA signal at the moment.
Drawings
FIG. 1 is a timing diagram of DDR5 DRAM sampling two cycle commands in normal operating mode;
FIG. 2 is a timing diagram of a DDR5 DRAM sampling two cycle commands in a circuit probe test mode in accordance with the prior art;
FIG. 3 is a schematic diagram of a command address sampling circuit shown in accordance with an exemplary embodiment;
FIG. 4 is a schematic diagram of a command address sampling circuit shown according to another exemplary embodiment;
FIG. 5 is a timing diagram of the command address sampling circuit of FIG. 4 sampling two-cycle command address signals;
FIG. 6 is a schematic diagram of a signal processing circuit shown in an exemplary embodiment;
FIG. 7 is a timing diagram of a conventional signal processing circuit for signal processing;
FIG. 8 is a schematic diagram of a chip select signal sampling circuit according to an exemplary embodiment;
fig. 9 is a timing diagram illustrating signal processing performed by the signal processing circuit according to an exemplary embodiment.
Detailed Description
The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the embodiments of the present disclosure and the accompanying drawings, it being apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical aspects of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.
When the DDR5 DRAM is operating in normal mode, the DRAM chip receives an initial command address signal from a Host (Host) through a command address pin. By way of example, the DRAM chip includes a total of 14 command address pins CA [0] -CA [13], with the initial command address signals sent by the host being noted CA [13:0]. The DRAM chip samples the initial command address signal CA [13:0] by using the parity clock signal PCLK_E/O obtained by dividing the external clock CTK, thereby obtaining a command address signal CA' [13:0] containing address information and command information.
Taking a two-cycle command as an example, as shown in fig. 1, in a normal operation mode, the first cycle of the initial command address signal CA [13:0] includes the command and part of the address information in the two-cycle command, and the second cycle of the initial command signal CA [13:0] includes the rest of the address information in the two-cycle command; dividing the external clock CTK into odd-even clock signals PCLK_O/E, and sampling the initial command address signals CA [13:0] at the rising edge of the odd clock signals PCLK_O at the first time T1 to obtain first sampling signals containing command address information C0; at the second time T2, the initial command address signal CA [13:0] is sampled at the rising edge of the even clock signal pclk_e to obtain a second sampled signal containing the remaining command address information C1, and then the second sampled signal is decoded to obtain a complete two-cycle command.
However, when the semiconductor memory enters the circuit probe test mode, the number of available CA pins is halved, for example, the initial command address signal can only be received through CA [0] -CA [6] pins, and the two-cycle command sent by the host can send the initial command address signal on the rising edge and the falling edge of the external clock CTK; as shown in FIG. 2, the rising edge of the first external clock CTK sends an initial command address signal CA [6:0] in the original first periodic signal in the two-period command, the initial command address signal comprising command address information C0_1, and the falling edge sends an initial command address signal CA [13:7] in the original first periodic signal in the two-period command, the initial command address signal comprising command address information C0_2; the rising edge of the second external clock CTK sends an initial command address signal CA [6:0] in the original second periodic signal in the two-period command, wherein the initial command address signal comprises command address information C1_1; the falling edge transmits an initial command address signal CA [13:7] in an original second periodic signal in the two-period command, wherein the initial command address signal comprises command address information C1_2; at this time, if the original sampling circuit is still used, the parity clock signal pclk_e/O after the frequency division of the external clock CTK is used to sample the two-period command at this time, only the information in the initial command address signal CA [6:0] in the two-period command can be obtained, so that the information in the initial command address signal CA [13:7] in the same command is lost, and the decoding operation cannot be performed correctly in the following steps.
In view of the above, the embodiments of the present disclosure provide a signal processing circuit for a semiconductor memory; the signal processing circuit includes: the command address sampling circuit is used for carrying out sampling processing on the initial command address signals at least twice every half of an external clock period to obtain at least two command address signals, and synchronously outputting the at least two command address signals; the initial command address signal includes N command address sub-signals, N is smaller than the number M of command address pins of the semiconductor memory, and M is an integer multiple of N.
In some embodiments, the semiconductor memory includes 14 command address pins, i.e., M is equal to 14, where N is selected to be equal to 7, although one skilled in the art may set different values of M and N according to specific needs.
Referring to fig. 3, in some embodiments, the command address sampling circuit 1000 includes: the first sampling sub-circuit 10 is configured to sample the initial command address signal CA [6:0] at the first time T1, and output a first command address signal Q0 containing the first command address information C0.
A second sampling sub-circuit 11 for sampling the initial command address signal CA [6:0] at the second time T2 and outputting a second command address signal Q1 containing the second command address information C1 in synchronization with the first command address signal Q0; the second time T2 is delayed by half an external clock CTK period from the first time T1.
In this embodiment, after the semiconductor memory enters the circuit probe test mode, as described above, taking the semiconductor memory receiving the single-cycle command address signal (1T CMD) as an example, the host will transmit the initial command address signal CA [6:0] at the first moment on the first rising edge of the external clock CTK, and the signal contains a part of the information C0 of the initial command address signal CA [13:0] of the semiconductor memory in the normal mode; the remaining information C1 is included in the initial command address signal CA [6:0] delayed by half the falling edge of the period of the external clock CTK from the first rising edge; thus, the semiconductor memory in the normal mode receives the initial command address signal including the single-cycle command address signal once, and 14 command address sub-signals in the initial command address signal CA [13:0] are changed into the semiconductor memory in the circuit probe test mode, which receives the initial command address signal twice at intervals of half an external clock period, and samples the initial command address signal CA [6:0] received each time to obtain a sampling signal composed of 7 command address sub-signals. The first sampling sub-circuit 10 samples the first transmitted initial command address signal CA [6:0] to obtain a first command address signal Q0 containing the first command address information C0, and the second sampling sub-circuit 11 samples the second transmitted initial command address signal CA [6:0] to obtain a second command address signal Q1 containing the first command address information C1, thereby realizing that a single-cycle command can still be correctly received in the circuit probe test mode.
Since the subsequent decoding process requires the first command address signal Q0 and the second command address signal Q1 to be aligned in time sequence for correct decoding, the first sampling sub-circuit 10 and the second sampling sub-circuit 11 need to synchronously output the first command address signal Q0 and the second command address signal Q1 although sampling is asynchronous, thereby generating a complete single-cycle command through decoding by the decoding circuit.
As an implementation manner of the present embodiment, as shown in fig. 3, the first sampling sub-circuit 10 includes a first flip-flop 101, a second flip-flop 102, and a third flip-flop 103.
The data input of the first flip-flop 101 receives the initial command address signal CA [6:0], the data output of which is coupled to the data input of the second flip-flop 102, and the clock input of the first flip-flop 101 receives the first internal clock signal PCLKDT.
The clock input of the second flip-flop 102 receives the first internal clock signal PCLKDT and the data output of the second flip-flop 102 is connected to the data input of the third flip-flop 103.
The clock input of the third flip-flop 103 receives the second internal clock signal PCLKBT, and the data output thereof outputs the first command address signal Q0.
The second sampling sub-circuit 11 comprises a fourth flip-flop 104 and a fifth flip-flop 105.
The data input of the fourth flip-flop 104 receives the initial command address signal CA [6:0], the data output of which is coupled to the data input of the fifth flip-flop 105, and the clock input of the fourth flip-flop 104 receives the second internal clock signal PCLKBT.
The clock input of the fifth flip-flop 105 receives the second internal clock signal PCLKBT, and the data output of the fifth flip-flop 105 outputs the second command address signal Q1.
Wherein the first internal clock signal PCLKDT is complementary to the second internal clock signal PCLKBT, and the first internal clock signal PCLKDT and the second internal clock signal PCLKBT are at the same frequency as the external clock CTK signal. Whereby asynchronous sampling synchronous output of the first sampling sub-circuit 10 and the second sampling sub-circuit 11 can be achieved.
Referring to fig. 4, in some embodiments, the semiconductor memory receives a two-cycle command after entering the circuit probe test mode, which, as previously described, requires four consecutive passes of the initial command address signal to complete the transmission, due to halving of the available command address pins. On the basis, the command address sampling circuit 1000 includes, in addition to the first sampling sub-circuit 10 and the second sampling sub-circuit 11, a third sampling sub-circuit 12 for sampling the initial command address signal CA [6:0] at a third time T3 and outputting a third command address signal Q2 including third command address information C2 in synchronization with the first command address signal Q0; the third time T3 is delayed by half an external clock CTK period from the second time T2.
A fourth sampling sub-circuit 13 for sampling the initial command address signal CA [6:0] at a fourth time T4 and outputting a fourth command address signal Q3 containing fourth command address information C3 in synchronization with the first command address signal Q0; the fourth time T4 is delayed by half an external clock CTK period from the third time T3.
As a specific implementation, referring to fig. 4, the command address sampling circuit 1000 adds a third sampling sub-circuit 12 and a fourth sampling sub-circuit 13 on the basis of the previous embodiment shown in fig. 3.
Wherein the third sampling sub-circuit 12 comprises a first flip-flop 101 and a sixth flip-flop 106 multiplexed with the first sampling sub-circuit 10.
The data input terminal of the sixth flip-flop 106 is connected to the data output terminal of the first flip-flop 101, the clock input terminal of the sixth flip-flop 106 receives the second internal clock signal PCLKBT, and the data output terminal of the sixth flip-flop outputs the third command address signal Q2.
The fourth sampling sub-circuit 13 includes a fourth flip-flop 104 multiplexed with the second sampling sub-circuit 11, and an output terminal of the fourth flip-flop 104 outputs a fourth command address signal Q3.
The first internal clock signal PCLKDT is complementary to the second internal clock signal PCLKBT, and the first internal clock signal PCLKDT and the second internal clock signal PCLKBT are the same frequency as the external clock CTK signal. Thereby, asynchronous sampling synchronous output of the first sampling sub-circuit 10, the second sampling sub-circuit 11, the third sampling sub-circuit 12 and the fourth sampling sub-circuit 13 can be realized.
It should be noted that, the third sampling sub-circuit 12 and the fourth sampling sub-circuit 13 partially multiplex the flip-flops in the first sampling sub-circuit 10 and the second sampling sub-circuit 11 may save circuit area and cost, and those skilled in the art may also choose not to multiplex the flip-flops to individually set the third sampling sub-circuit 12 and the fourth sampling sub-circuit 13, and the specific circuits will not be described here again.
FIG. 5 shows a timing diagram of the sampling output of the command address sampling circuit 1000 of FIG. 4 for a two-cycle command, as shown in FIG. 5, where the host sends a two-cycle command, including serial C0-C3 information.
At time T1, i.e., PCLKDT first rising edge, the first flip-flop 101 samples the CA [6:0] signal containing the C0 information, and the data output of the first flip-flop 101 outputs the sampled signal C0-1 containing the C0 information.
At time T2, i.e., PCLKBT first rising edge, the fourth flip-flop 104 samples the CA [6:0] signal containing C1 information, the data output of the fourth flip-flop 104 outputs the sampling signal C1-1 containing C1 information, the sixth flip-flop 106 samples the sampling signal C0-1 output by the first flip-flop 101, and the data output outputs the sampling signal C0-2 containing C0 information.
Then, at time T3, i.e. PCLKDT the second rising edge, the first flip-flop 101 samples the CA [6:0] signal containing the C2 information, and the data output terminal of the first flip-flop 101 outputs the sampling signal C2-1 containing the C2 information; the second flip-flop 102 samples the sampling signal C0-1 containing the C0 information outputted from the first flip-flop 101, and outputs the sampling signal C0-3 containing the C0 information.
At time T4, that is, PCLKBT the second rising edge, the third flip-flop 103 samples the sampling signal C0-3 containing the C0 information output by the second flip-flop 102, outputs the sampling signal C0-4 containing the C0 information, and uses the sampling signal C0-4 containing the C0 information as the first command address signal Q0 output by the first sampling sub-circuit 10; meanwhile, the fourth flip-flop 104 samples the CA [6:0] signal containing the C3 information, outputs a sampling signal C3-1 containing the C3 information, and takes the sampling signal C3-1 as a fourth command address signal Q3 output by the fourth sampling sub-circuit 13; the fifth flip-flop 105 resamples the sampling signal C1-1 containing the C1 information outputted from the fourth flip-flop 104, generates a sampling signal C1-2 containing the C1 information, and uses the sampling signal C1-2 as a second command address signal Q1 outputted from the second sampling sub-circuit 11; the sixth flip-flop 106 samples the sampling signal C2-1 containing the C2 information outputted from the first flip-flop 101, outputs the sampling signal C2-2 containing the C2 information, and uses the sampling signal C2-2 as the third command address signal Q2 outputted from the third sampling sub-circuit 12.
Through the multi-stage sampling, the information of the two-period command can be correctly sampled, all command address signals are aligned at the same clock edge, and synchronous output of asynchronous sampling signals is realized.
In some embodiments, as shown in fig. 6, the signal processing circuit 1 further includes a chip select signal sampling circuit 2000 and a command decoding circuit 3000; the command decoding circuit 3000 receives a part of the command address sub-signals of the command address sampling circuit 1000 and the first chip select signal generated by the chip select signal sampling circuit 2000, and decodes, for example, i command address sub-signals (CA [4:0 ]) selected from the N command address sub-signals (CA [6:0 ]) and the first chip select signal PCS obtained by sampling the initial chip select signal cs_n by the chip select signal sampling circuit 2000 to obtain the final command CMD. Where N is greater than i.
However, as described above, in some embodiments, the command address sampling circuit 1000 samples the initial command address signal, for example, the initial command address signal CA [6:0] in multiple stages to obtain the command address signal CA [6:0] including a plurality of command address sub-signals, and the chip select signal sampling circuit 2000 samples the initial chip select signal cs_n to generate the first chip select signal PCS without multiple stages, so that the time for transmitting the first chip select signal and the command address signal to the input of the command decoding circuit 3000 is different, as shown in fig. 7, the first chip select signal PCS obtained by sampling the initial chip select signal cs_n arrives at the input of the command decoding circuit 3000 earlier than the command address sub-signal CA [4:0] to cause the decoded command CMD waveform to have a glitch (glitch), which is mistaken for an erroneous command by a subsequent circuit unit.
In view of this, in some embodiments, a chip select signal sampling circuit 2000 is provided for sampling an initial chip select signal cs_n and outputting a first chip select signal PCS;
The command decoding circuit 3000 is configured to receive the first slice selection signal and i command address sub-signals, decode the same, and output a command signal; wherein i is less than N;
The time when the valid signal of the first chip select signal PCS reaches the command decoding circuit 3000 is later than the time when the valid signal of all i command address sub-signals reaches the command decoding circuit 3000, and the off time of the valid signal of the first chip select signal PCS is earlier than the off time of the valid signal of all i command address sub-signals.
Referring to fig. 8 and 9, as one implementation, the chip select signal sampling circuit 2000 includes a seventh flip-flop 201, an eighth flip-flop 202, a delay circuit 203, and a latch 204.
The data input terminal of the seventh flip-flop 201 receives the inverse signal of the initial chip select signal cs_n, the clock input terminal thereof receives the first internal clock signal PCLKDT, and the data output terminal thereof outputs the first intermediate signal ckt_cs; the original chip selection signal CS_n can be inverted to obtain a reverse signal of the original chip selection signal CS_n, or the reverse signal can be obtained according to specific situations by combining common means of a person skilled in the art; in order to obtain the first intermediate signal ckt_cs having the same waveform as the present embodiment, the data input terminal of the seventh flip-flop 201 may receive the initial chip select signal cs_n, and the output terminal thereof may be inverted to obtain the first intermediate signal ckt_cs, which is not described herein.
An input terminal of the delay circuit 203 receives the first intermediate signal ckt_cs, and an output terminal of the delay circuit 203 is connected to a set terminal of the latch 204 and outputs a first intermediate delay signal CKTD _cs.
The eighth flip-flop 202 has a data input receiving the inverse of the initial chip select signal cs_n, a clock input receiving the second internal clock signal PCLKBT, a data output coupled to the reset of the latch 204, and outputs the second intermediate signal ckb_cs.
An output terminal of the latch 204 is connected to a chip select signal input terminal of the command decoding circuit 3000, and outputs a first chip select signal PCS. As one implementation, latch 204 may be a select nor latch.
Fig. 9 shows a timing diagram of the chip select signal sampling circuit 2000, in which the seventh flip-flop 201 and the eighth flip-flop 202 sample the inverted signal of the initial chip select signal cs_n by half an external clock CTK period, respectively, and the second intermediate signal ckb_cs is delayed by half an external clock CTK period from the first intermediate signal ckt_cs, as shown.
The first intermediate delay signal CKTD _cs generated by the delay circuit 203 is delayed by Δt compared to the first intermediate signal ckt_cs, where Δt is the delay time of the delay circuit 203; by setting the time length of Δt, the start time of the active level of the first select signal PCS finally output by the latch 204 and the pulse width of the active level of the first select signal PCS can be adjusted. The time length of Δt is greater than the maximum value of the delay difference between the start time of the active level of the initial chip select signal and the time when the active signal arrives at the command decoding circuit in the i command address sub-signals, and the delay time length of the delay circuit 203 is less than the half period of the first internal clock signal PCLKDT. The delay circuit 203 may be composed of an even number of inverters connected in series, or other delay circuits may be used.
As shown in fig. 9, the effective levels of the command address sub-signals CA [4:0] output from the command address sampling circuit 1000 are on average at the high level, wherein the time when the effective level of the command address sub-signal CA [0] reaches the command decoding circuit is the latest; the rising edge of the first intermediate delay signal CKTD _cs obtained after the initial chip select signal cs_n is sampled by the seventh trigger 201 and delayed by the delay circuit 203 determines the starting time of the effective level of the first chip select signal PCS, and the time of the effective level of the first chip select signal PCS reaching the command decoding circuit is later than the time of the effective level of the command address sub-signal CA [0] reaching the command decoding circuit by setting the delay time Δt of the delay circuit 203; the rising edge of the second intermediate signal ckb_cs, which is obtained by sampling the initial chip select signal cs_n by the eighth flip-flop 202, determines the off-time of the active level of the first chip select signal PCS, and since the transmission path delay of the command address signal CA [0] is generally not greater than half an external clock period, it is ensured that the time when the active signal of the first chip select signal PCS reaches the command decoding circuit is later than the time when the active signal of all i command address sub-signals reaches the command decoding circuit, and the off-time of the active signal of the first chip select signal is earlier than the off-time of the active signal of all i command address sub-signals.
It should be noted that, based on the present embodiment, a person skilled in the art may set the start time and the stop time of the active level of the first select signal PCS according to the delay time of the specific command address sub-signal, so as to change the delay time Δt of the delay circuit 203, or further add a delay circuit to the input path of the second intermediate signal ckb_cs to the latch 204, which is not described herein.
Embodiments of the present disclosure also provide a memory including a signal processing circuit as described above.
In some embodiments, the memory is a fifth generation double rate synchronous dynamic random access memory DDR5.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.
The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure, but rather, the equivalent structural changes made by the present disclosure and the accompanying drawings under the inventive concept of the present disclosure, or the direct/indirect application in other related technical fields are included in the scope of the present disclosure.

Claims (11)

1. A signal processing circuit for a semiconductor memory, the signal processing circuit comprising: the command address sampling circuit is used for carrying out sampling processing on the initial command address signals at least twice every half of an external clock period to obtain at least two command address signals, and synchronously outputting the at least two command address signals; the initial command address signal comprises N command address sub-signals, wherein N is smaller than the number M of command address pins of the semiconductor memory, and M is an integer multiple of N;
the command address sampling circuit includes:
A first sampling sub-circuit for sampling the initial command address signal at a first time and outputting a first command address signal containing first command address information;
A second sampling sub-circuit for sampling the initial command address signal at a second time and outputting a second command address signal containing second command address information in synchronization with the first command address signal; the second time is delayed by half the external clock period from the first time.
2. The signal processing circuit of claim 1, wherein the command address sampling circuit further comprises:
A third sampling sub-circuit for sampling the initial command address signal at a third time and outputting a third command address signal containing third command address information in synchronization with the first command address signal; the third time is delayed by half of the external clock period than the second time;
A fourth sampling sub-circuit for sampling the initial command address signal at a fourth time and outputting a fourth command address signal containing fourth command address information in synchronization with the first command address signal; the fourth time is delayed from the third time by half of the external clock period.
3. The signal processing circuit of claim 2, wherein the first sampling sub-circuit comprises a first flip-flop, a second flip-flop, and a third flip-flop;
the data input end of the first trigger receives the initial command address signal, the data output end of the first trigger is connected with the data input end of the second trigger, and the clock input end of the first trigger receives a first internal clock signal;
The clock input end of the second trigger receives the first internal clock signal, and the data output end of the second trigger is connected with the data input end of the third trigger;
the clock input end of the third trigger receives a second internal clock signal, and the data output end of the third trigger outputs the first command address signal;
the first internal clock signal is complementary to the second internal clock signal, and the first internal clock signal and the second internal clock signal are the same frequency as the external clock signal.
4. A signal processing circuit according to claim 3, wherein the second sampling sub-circuit comprises a fourth flip-flop and a fifth flip-flop;
the data input end of the fourth trigger receives the initial command address signal, the data output end of the fourth trigger is connected with the data input end of the fifth trigger, and the clock input end of the fourth trigger receives the second internal clock signal;
The clock input end of the fifth trigger receives the second internal clock signal, and the data output end of the fifth trigger outputs the second command address signal.
5. The signal processing circuit of claim 4, wherein the third sampling sub-circuit comprises the first flip-flop and a sixth flip-flop multiplexed with the first sampling sub-circuit;
the data input end of the sixth trigger is connected with the data output end of the first trigger, the clock input end of the sixth trigger receives the second internal clock signal, and the data output end of the sixth trigger outputs the third command address signal.
6. The signal processing circuit of claim 5, wherein the fourth sampling sub-circuit comprises the fourth flip-flop multiplexed with the second sampling sub-circuit, a data output of the fourth flip-flop outputting the fourth command address signal.
7. The signal processing circuit according to any one of claims 3 to 6, further comprising: a chip select signal sampling circuit and a command decoding circuit;
the chip selection signal sampling circuit is used for sampling an initial chip selection signal and outputting a first chip selection signal;
The command decoding circuit is used for receiving the first slice selection signal and i command address sub-signals for decoding and outputting command signals; wherein i is less than N;
The time when the effective signal of the first slice signal reaches the command decoding circuit is later than the time when the effective signal of all i command address sub-signals reaches the command decoding circuit, and the cut-off time of the effective signal of the first slice signal is earlier than the cut-off time of the effective signal of all i command address sub-signals.
8. The signal processing circuit of claim 7, wherein the chip select signal sampling circuit comprises a seventh flip-flop, an eighth flip-flop, a delay circuit, and a latch;
the data input end of the seventh trigger receives the reverse signal of the initial chip selection signal, the clock input end of the seventh trigger receives a first internal clock signal, and the data output end of the seventh trigger outputs a first intermediate signal;
the input end of the delay circuit receives the first intermediate signal, and the output end of the delay circuit is connected with the set end of the latch and outputs a first intermediate delay signal;
The data input end of the eighth trigger receives the reverse signal of the initial chip selection signal, the clock input end of the eighth trigger receives a second internal clock signal, and the data output end of the eighth trigger is connected with the reset end of the latch and outputs a second intermediate signal;
the output end of the latch is connected with the chip selection signal input end of the command decoding circuit.
9. The signal processing circuit of claim 8, wherein the delay time of the delay circuit is greater than a maximum value of a delay difference between a start time of the initial chip select signal active level and a time of the active signal of the i command address sub-signals reaching the command decoding circuit, and the delay time of the delay circuit is less than a half period of the first internal clock.
10. A memory, characterized in that the memory comprises a signal processing circuit according to any one of claims 1 to 9.
11. The memory of claim 10, wherein the memory comprises: fifth generation double rate synchronous dynamic random access memory DDR5.
CN202311760895.4A 2023-12-20 2023-12-20 Signal processing circuit and memory Active CN117457048B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311760895.4A CN117457048B (en) 2023-12-20 2023-12-20 Signal processing circuit and memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311760895.4A CN117457048B (en) 2023-12-20 2023-12-20 Signal processing circuit and memory

Publications (2)

Publication Number Publication Date
CN117457048A CN117457048A (en) 2024-01-26
CN117457048B true CN117457048B (en) 2024-05-14

Family

ID=89591242

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311760895.4A Active CN117457048B (en) 2023-12-20 2023-12-20 Signal processing circuit and memory

Country Status (1)

Country Link
CN (1) CN117457048B (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7073099B1 (en) * 2002-05-30 2006-07-04 Marvell International Ltd. Method and apparatus for improving memory operation and yield
JP2006294074A (en) * 2005-03-14 2006-10-26 Fujitsu Ltd Semiconductor memory device
CN105306068A (en) * 2015-10-30 2016-02-03 南京理工大学 Parallel-serial conversion circuit based on clock phase modulation
CN113553277A (en) * 2021-06-24 2021-10-26 西安电子科技大学 High-throughput and low-delay PHY (physical layer) interface circuit device of DDR5SDRAM (synchronous dynamic random access memory)
CN116092544A (en) * 2021-09-02 2023-05-09 爱思开海力士有限公司 Command address control circuit and semiconductor device and semiconductor system including same
CN116153384A (en) * 2023-04-20 2023-05-23 长鑫存储技术有限公司 Chip test device
WO2023178805A1 (en) * 2022-03-23 2023-09-28 长鑫存储技术有限公司 Signal sampling circuit and semiconductor memory

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7073099B1 (en) * 2002-05-30 2006-07-04 Marvell International Ltd. Method and apparatus for improving memory operation and yield
JP2006294074A (en) * 2005-03-14 2006-10-26 Fujitsu Ltd Semiconductor memory device
CN105306068A (en) * 2015-10-30 2016-02-03 南京理工大学 Parallel-serial conversion circuit based on clock phase modulation
CN113553277A (en) * 2021-06-24 2021-10-26 西安电子科技大学 High-throughput and low-delay PHY (physical layer) interface circuit device of DDR5SDRAM (synchronous dynamic random access memory)
CN116092544A (en) * 2021-09-02 2023-05-09 爱思开海力士有限公司 Command address control circuit and semiconductor device and semiconductor system including same
WO2023178805A1 (en) * 2022-03-23 2023-09-28 长鑫存储技术有限公司 Signal sampling circuit and semiconductor memory
CN116153384A (en) * 2023-04-20 2023-05-23 长鑫存储技术有限公司 Chip test device

Also Published As

Publication number Publication date
CN117457048A (en) 2024-01-26

Similar Documents

Publication Publication Date Title
US6279073B1 (en) Configurable synchronizer for double data rate synchronous dynamic random access memory
US5973507A (en) Exclusive-or gate for use in delay using transmission gate circuitry
US6301190B1 (en) Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester
US7058799B2 (en) Apparatus and method for clock domain crossing with integrated decode
KR100523716B1 (en) Register without restriction of number of mounted memory devices and memory module having the same
KR100330072B1 (en) Semiconductor memory device
US6252441B1 (en) Synchronous data sampling circuit
KR900014970A (en) Synchronous circuit
US7843743B2 (en) Data output circuit for semiconductor memory apparatus
US6853317B2 (en) Circuit and method for generating mode register set code
KR100238869B1 (en) Semiconductor memory device for providing bust mode control signal
CN117457048B (en) Signal processing circuit and memory
US6188640B1 (en) Data output circuits for semiconductor memory devices
US4493095A (en) Counter having a plurality of cascaded flip-flops
CN116844605B (en) Signal sampling circuit and semiconductor memory
CN113517894B (en) Serial-parallel conversion circuit
US5161161A (en) Minimum pulsewidth test module on clocked logic integrated circuit
US20070133339A1 (en) Data interface device for accessing memory
JP3368572B2 (en) Period generator
KR100278271B1 (en) A clock frequency divider
KR100244430B1 (en) Test of semiconductor chip
JPH1032487A (en) Timing signal generation circuit
US20060064617A1 (en) Internal clock generator
KR20020024516A (en) Semiconductor integrated circuit
KR20070056505A (en) Data output circuit of semiconductor memory device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant